soc.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <init.h>
  6. #include <asm/io.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/mach-imx/boot_mode.h>
  11. #include <asm/mach-imx/hab.h>
  12. static char *get_reset_cause(char *);
  13. #if defined(CONFIG_IMX_HAB)
  14. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  15. .bank = 29,
  16. .word = 6,
  17. };
  18. #endif
  19. #define ROM_VERSION_ADDR 0x80
  20. u32 get_cpu_rev(void)
  21. {
  22. /* Check the ROM version for cpu revision */
  23. u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR);
  24. return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF);
  25. }
  26. #ifdef CONFIG_REVISION_TAG
  27. u32 __weak get_board_rev(void)
  28. {
  29. return get_cpu_rev();
  30. }
  31. #endif
  32. enum bt_mode get_boot_mode(void)
  33. {
  34. u32 bt0_cfg = 0;
  35. bt0_cfg = readl(CMC0_RBASE + 0x40);
  36. bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
  37. if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
  38. /* No low power boot */
  39. if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
  40. return DUAL_BOOT;
  41. else
  42. return SINGLE_BOOT;
  43. }
  44. return LOW_POWER_BOOT;
  45. }
  46. int arch_cpu_init(void)
  47. {
  48. return 0;
  49. }
  50. #ifdef CONFIG_BOARD_POSTCLK_INIT
  51. int board_postclk_init(void)
  52. {
  53. return 0;
  54. }
  55. #endif
  56. #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
  57. #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
  58. #define REFRESH_WORD0 0xA602 /* 1st refresh word */
  59. #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
  60. static void disable_wdog(u32 wdog_base)
  61. {
  62. writel(UNLOCK_WORD0, (wdog_base + 0x04));
  63. writel(UNLOCK_WORD1, (wdog_base + 0x04));
  64. writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
  65. writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
  66. writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
  67. writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
  68. writel(REFRESH_WORD1, (wdog_base + 0x04));
  69. }
  70. void init_wdog(void)
  71. {
  72. /*
  73. * ROM will configure WDOG1, disable it or enable it
  74. * depending on FUSE. The update bit is set for reconfigurable.
  75. * We have to use unlock sequence to reconfigure it.
  76. * WDOG2 is not touched by ROM, so it will have default value
  77. * which is enabled. We can directly configure it.
  78. * To simplify the codes, we still use same reconfigure
  79. * process as WDOG1. Because the update bit is not set for
  80. * WDOG2, the unlock sequence won't take effect really.
  81. * It actually directly configure the wdog.
  82. * In this function, we will disable both WDOG1 and WDOG2,
  83. * and set update bit for both. So that kernel can reconfigure them.
  84. */
  85. disable_wdog(WDG1_RBASE);
  86. disable_wdog(WDG2_RBASE);
  87. }
  88. void s_init(void)
  89. {
  90. /* Disable wdog */
  91. init_wdog();
  92. /* clock configuration. */
  93. clock_init();
  94. if (soc_rev() < CHIP_REV_2_0) {
  95. /* enable dumb pmic */
  96. writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
  97. }
  98. return;
  99. }
  100. #ifndef CONFIG_ULP_WATCHDOG
  101. void reset_cpu(ulong addr)
  102. {
  103. setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
  104. while (1)
  105. ;
  106. }
  107. #endif
  108. #if defined(CONFIG_DISPLAY_CPUINFO)
  109. const char *get_imx_type(u32 imxtype)
  110. {
  111. return "7ULP";
  112. }
  113. int print_cpuinfo(void)
  114. {
  115. u32 cpurev;
  116. char cause[18];
  117. cpurev = get_cpu_rev();
  118. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  119. get_imx_type((cpurev & 0xFF000) >> 12),
  120. (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
  121. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  122. printf("Reset cause: %s\n", get_reset_cause(cause));
  123. printf("Boot mode: ");
  124. switch (get_boot_mode()) {
  125. case LOW_POWER_BOOT:
  126. printf("Low power boot\n");
  127. break;
  128. case DUAL_BOOT:
  129. printf("Dual boot\n");
  130. break;
  131. case SINGLE_BOOT:
  132. default:
  133. printf("Single boot\n");
  134. break;
  135. }
  136. return 0;
  137. }
  138. #endif
  139. #define CMC_SRS_TAMPER (1 << 31)
  140. #define CMC_SRS_SECURITY (1 << 30)
  141. #define CMC_SRS_TZWDG (1 << 29)
  142. #define CMC_SRS_JTAG_RST (1 << 28)
  143. #define CMC_SRS_CORE1 (1 << 16)
  144. #define CMC_SRS_LOCKUP (1 << 15)
  145. #define CMC_SRS_SW (1 << 14)
  146. #define CMC_SRS_WDG (1 << 13)
  147. #define CMC_SRS_PIN_RESET (1 << 8)
  148. #define CMC_SRS_WARM (1 << 4)
  149. #define CMC_SRS_HVD (1 << 3)
  150. #define CMC_SRS_LVD (1 << 2)
  151. #define CMC_SRS_POR (1 << 1)
  152. #define CMC_SRS_WUP (1 << 0)
  153. static u32 reset_cause = -1;
  154. static char *get_reset_cause(char *ret)
  155. {
  156. u32 cause1, cause = 0, srs = 0;
  157. u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
  158. u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);
  159. if (!ret)
  160. return "null";
  161. srs = readl(reg_srs);
  162. cause1 = readl(reg_ssrs);
  163. writel(cause1, reg_ssrs);
  164. reset_cause = cause1;
  165. cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
  166. switch (cause) {
  167. case CMC_SRS_POR:
  168. sprintf(ret, "%s", "POR");
  169. break;
  170. case CMC_SRS_WUP:
  171. sprintf(ret, "%s", "WUP");
  172. break;
  173. case CMC_SRS_WARM:
  174. cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
  175. CMC_SRS_JTAG_RST);
  176. switch (cause) {
  177. case CMC_SRS_WDG:
  178. sprintf(ret, "%s", "WARM-WDG");
  179. break;
  180. case CMC_SRS_SW:
  181. sprintf(ret, "%s", "WARM-SW");
  182. break;
  183. case CMC_SRS_JTAG_RST:
  184. sprintf(ret, "%s", "WARM-JTAG");
  185. break;
  186. default:
  187. sprintf(ret, "%s", "WARM-UNKN");
  188. break;
  189. }
  190. break;
  191. default:
  192. sprintf(ret, "%s-%X", "UNKN", cause1);
  193. break;
  194. }
  195. debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1);
  196. return ret;
  197. }
  198. #ifdef CONFIG_ENV_IS_IN_MMC
  199. __weak int board_mmc_get_env_dev(int devno)
  200. {
  201. return CONFIG_SYS_MMC_ENV_DEV;
  202. }
  203. int mmc_get_env_dev(void)
  204. {
  205. int devno = 0;
  206. u32 bt1_cfg = 0;
  207. /* If not boot from sd/mmc, use default value */
  208. if (get_boot_mode() == LOW_POWER_BOOT)
  209. return CONFIG_SYS_MMC_ENV_DEV;
  210. bt1_cfg = readl(CMC1_RBASE + 0x40);
  211. devno = (bt1_cfg >> 9) & 0x7;
  212. return board_mmc_get_env_dev(devno);
  213. }
  214. #endif
  215. enum boot_device get_boot_device(void)
  216. {
  217. struct bootrom_sw_info **p =
  218. (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
  219. enum boot_device boot_dev = SD1_BOOT;
  220. u8 boot_type = (*p)->boot_dev_type;
  221. u8 boot_instance = (*p)->boot_dev_instance;
  222. switch (boot_type) {
  223. case BOOT_TYPE_SD:
  224. boot_dev = boot_instance + SD1_BOOT;
  225. break;
  226. case BOOT_TYPE_MMC:
  227. boot_dev = boot_instance + MMC1_BOOT;
  228. break;
  229. case BOOT_TYPE_USB:
  230. boot_dev = USB_BOOT;
  231. break;
  232. default:
  233. break;
  234. }
  235. return boot_dev;
  236. }