fsl_mcdmafec.c 16 KB

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  1. /*
  2. * (C) Copyright 2000-2004
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2007 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <common.h>
  11. #include <malloc.h>
  12. #include <command.h>
  13. #include <config.h>
  14. #include <net.h>
  15. #include <miiphy.h>
  16. #undef ET_DEBUG
  17. #undef MII_DEBUG
  18. /* Ethernet Transmit and Receive Buffers */
  19. #define DBUF_LENGTH 1520
  20. #define PKT_MAXBUF_SIZE 1518
  21. #define PKT_MINBUF_SIZE 64
  22. #define PKT_MAXBLR_SIZE 1536
  23. #define LAST_PKTBUFSRX PKTBUFSRX - 1
  24. #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
  25. #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
  26. #define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
  27. /* RxBD bits definitions */
  28. #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
  29. BD_ENET_RX_OV | BD_ENET_RX_TR)
  30. #include <asm/immap.h>
  31. #include <asm/fsl_mcdmafec.h>
  32. #include "MCD_dma.h"
  33. DECLARE_GLOBAL_DATA_PTR;
  34. struct fec_info_dma fec_info[] = {
  35. #ifdef CONFIG_SYS_FEC0_IOBASE
  36. {
  37. 0, /* index */
  38. CONFIG_SYS_FEC0_IOBASE, /* io base */
  39. CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
  40. CONFIG_SYS_FEC0_MIIBASE, /* mii base */
  41. -1, /* phy_addr */
  42. 0, /* duplex and speed */
  43. 0, /* phy name */
  44. 0, /* phyname init */
  45. 0, /* RX BD */
  46. 0, /* TX BD */
  47. 0, /* rx Index */
  48. 0, /* tx Index */
  49. 0, /* tx buffer */
  50. 0, /* initialized flag */
  51. (struct fec_info_dma *)-1, /* next */
  52. FEC0_RX_TASK, /* rxTask */
  53. FEC0_TX_TASK, /* txTask */
  54. FEC0_RX_PRIORITY, /* rxPri */
  55. FEC0_TX_PRIORITY, /* txPri */
  56. FEC0_RX_INIT, /* rxInit */
  57. FEC0_TX_INIT, /* txInit */
  58. 0, /* usedTbdIndex */
  59. 0, /* cleanTbdNum */
  60. },
  61. #endif
  62. #ifdef CONFIG_SYS_FEC1_IOBASE
  63. {
  64. 1, /* index */
  65. CONFIG_SYS_FEC1_IOBASE, /* io base */
  66. CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
  67. CONFIG_SYS_FEC1_MIIBASE, /* mii base */
  68. -1, /* phy_addr */
  69. 0, /* duplex and speed */
  70. 0, /* phy name */
  71. 0, /* phy name init */
  72. #ifdef CONFIG_SYS_DMA_USE_INTSRAM
  73. (cbd_t *)DBUF_LENGTH, /* RX BD */
  74. #else
  75. 0, /* RX BD */
  76. #endif
  77. 0, /* TX BD */
  78. 0, /* rx Index */
  79. 0, /* tx Index */
  80. 0, /* tx buffer */
  81. 0, /* initialized flag */
  82. (struct fec_info_dma *)-1, /* next */
  83. FEC1_RX_TASK, /* rxTask */
  84. FEC1_TX_TASK, /* txTask */
  85. FEC1_RX_PRIORITY, /* rxPri */
  86. FEC1_TX_PRIORITY, /* txPri */
  87. FEC1_RX_INIT, /* rxInit */
  88. FEC1_TX_INIT, /* txInit */
  89. 0, /* usedTbdIndex */
  90. 0, /* cleanTbdNum */
  91. }
  92. #endif
  93. };
  94. static int fec_send(struct eth_device *dev, void *packet, int length);
  95. static int fec_recv(struct eth_device *dev);
  96. static int fec_init(struct eth_device *dev, bd_t * bd);
  97. static void fec_halt(struct eth_device *dev);
  98. #ifdef ET_DEBUG
  99. static void dbg_fec_regs(struct eth_device *dev)
  100. {
  101. struct fec_info_dma *info = dev->priv;
  102. volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
  103. printf("=====\n");
  104. printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
  105. printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
  106. printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
  107. printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
  108. printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
  109. printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
  110. printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
  111. printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
  112. printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
  113. printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
  114. printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
  115. printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
  116. printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
  117. printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
  118. printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
  119. printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
  120. printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
  121. printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
  122. printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
  123. printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
  124. printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
  125. printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
  126. printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
  127. printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
  128. printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
  129. printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
  130. printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
  131. printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
  132. printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
  133. printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
  134. printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
  135. printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
  136. printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
  137. printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
  138. printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
  139. }
  140. #endif
  141. static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
  142. int dup_spd)
  143. {
  144. if ((dup_spd >> 16) == FULL) {
  145. /* Set maximum frame length */
  146. fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
  147. FEC_RCR_PROM | 0x100;
  148. fecp->tcr = FEC_TCR_FDEN;
  149. } else {
  150. /* Half duplex mode */
  151. fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
  152. FEC_RCR_MII_MODE | FEC_RCR_DRT;
  153. fecp->tcr &= ~FEC_TCR_FDEN;
  154. }
  155. if ((dup_spd & 0xFFFF) == _100BASET) {
  156. #ifdef MII_DEBUG
  157. printf("100Mbps\n");
  158. #endif
  159. bd->bi_ethspeed = 100;
  160. } else {
  161. #ifdef MII_DEBUG
  162. printf("10Mbps\n");
  163. #endif
  164. bd->bi_ethspeed = 10;
  165. }
  166. }
  167. static int fec_send(struct eth_device *dev, void *packet, int length)
  168. {
  169. struct fec_info_dma *info = dev->priv;
  170. cbd_t *pTbd, *pUsedTbd;
  171. u16 phyStatus;
  172. miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
  173. /* process all the consumed TBDs */
  174. while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
  175. pUsedTbd = &info->txbd[info->usedTbdIdx];
  176. if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
  177. #ifdef ET_DEBUG
  178. printf("Cannot clean TBD %d, in use\n",
  179. info->cleanTbdNum);
  180. #endif
  181. return 0;
  182. }
  183. /* clean this buffer descriptor */
  184. if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
  185. pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
  186. else
  187. pUsedTbd->cbd_sc = 0;
  188. /* update some indeces for a correct handling of the TBD ring */
  189. info->cleanTbdNum++;
  190. info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
  191. }
  192. /* Check for valid length of data. */
  193. if ((length > 1500) || (length <= 0)) {
  194. return -1;
  195. }
  196. /* Check the number of vacant TxBDs. */
  197. if (info->cleanTbdNum < 1) {
  198. printf("No available TxBDs ...\n");
  199. return -1;
  200. }
  201. /* Get the first TxBD to send the mac header */
  202. pTbd = &info->txbd[info->txIdx];
  203. pTbd->cbd_datlen = length;
  204. pTbd->cbd_bufaddr = (u32) packet;
  205. pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
  206. info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
  207. /* Enable DMA transmit task */
  208. MCD_continDma(info->txTask);
  209. info->cleanTbdNum -= 1;
  210. /* wait until frame is sent . */
  211. while (pTbd->cbd_sc & BD_ENET_TX_READY) {
  212. udelay(10);
  213. }
  214. return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
  215. }
  216. static int fec_recv(struct eth_device *dev)
  217. {
  218. struct fec_info_dma *info = dev->priv;
  219. volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
  220. cbd_t *prbd = &info->rxbd[info->rxIdx];
  221. u32 ievent;
  222. int frame_length, len = 0;
  223. /* Check if any critical events have happened */
  224. ievent = fecp->eir;
  225. if (ievent != 0) {
  226. fecp->eir = ievent;
  227. if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
  228. printf("fec_recv: error\n");
  229. fec_halt(dev);
  230. fec_init(dev, NULL);
  231. return 0;
  232. }
  233. if (ievent & FEC_EIR_HBERR) {
  234. /* Heartbeat error */
  235. fecp->tcr |= FEC_TCR_GTS;
  236. }
  237. if (ievent & FEC_EIR_GRA) {
  238. /* Graceful stop complete */
  239. if (fecp->tcr & FEC_TCR_GTS) {
  240. printf("fec_recv: tcr_gts\n");
  241. fec_halt(dev);
  242. fecp->tcr &= ~FEC_TCR_GTS;
  243. fec_init(dev, NULL);
  244. }
  245. }
  246. }
  247. if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
  248. if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
  249. !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
  250. ((prbd->cbd_datlen - 4) > 14)) {
  251. /* Get buffer address and size */
  252. frame_length = prbd->cbd_datlen - 4;
  253. /* Fill the buffer and pass it to upper layers */
  254. net_process_received_packet((uchar *)prbd->cbd_bufaddr,
  255. frame_length);
  256. len = frame_length;
  257. }
  258. /* Reset buffer descriptor as empty */
  259. if ((info->rxIdx) == (PKTBUFSRX - 1))
  260. prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
  261. else
  262. prbd->cbd_sc = BD_ENET_RX_EMPTY;
  263. prbd->cbd_datlen = PKTSIZE_ALIGN;
  264. /* Now, we have an empty RxBD, restart the DMA receive task */
  265. MCD_continDma(info->rxTask);
  266. /* Increment BD count */
  267. info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX;
  268. }
  269. return len;
  270. }
  271. static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
  272. {
  273. u8 currByte; /* byte for which to compute the CRC */
  274. int byte; /* loop - counter */
  275. int bit; /* loop - counter */
  276. u32 crc = 0xffffffff; /* initial value */
  277. for (byte = 0; byte < 6; byte++) {
  278. currByte = mac[byte];
  279. for (bit = 0; bit < 8; bit++) {
  280. if ((currByte & 0x01) ^ (crc & 0x01)) {
  281. crc >>= 1;
  282. crc = crc ^ 0xedb88320;
  283. } else {
  284. crc >>= 1;
  285. }
  286. currByte >>= 1;
  287. }
  288. }
  289. crc = crc >> 26;
  290. /* Set individual hash table register */
  291. if (crc >= 32) {
  292. fecp->ialr = (1 << (crc - 32));
  293. fecp->iaur = 0;
  294. } else {
  295. fecp->ialr = 0;
  296. fecp->iaur = (1 << crc);
  297. }
  298. /* Set physical address */
  299. fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
  300. fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
  301. /* Clear multicast address hash table */
  302. fecp->gaur = 0;
  303. fecp->galr = 0;
  304. }
  305. static int fec_init(struct eth_device *dev, bd_t * bd)
  306. {
  307. struct fec_info_dma *info = dev->priv;
  308. volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
  309. int i;
  310. uchar enetaddr[6];
  311. #ifdef ET_DEBUG
  312. printf("fec_init: iobase 0x%08x ...\n", info->iobase);
  313. #endif
  314. fecpin_setclear(dev, 1);
  315. fec_halt(dev);
  316. #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
  317. defined (CONFIG_SYS_DISCOVER_PHY)
  318. mii_init();
  319. set_fec_duplex_speed(fecp, bd, info->dup_spd);
  320. #else
  321. #ifndef CONFIG_SYS_DISCOVER_PHY
  322. set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
  323. #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
  324. #endif /* CONFIG_CMD_MII || CONFIG_MII */
  325. /* We use strictly polling mode only */
  326. fecp->eimr = 0;
  327. /* Clear any pending interrupt */
  328. fecp->eir = 0xffffffff;
  329. /* Set station address */
  330. if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE)
  331. eth_getenv_enetaddr("ethaddr", enetaddr);
  332. else
  333. eth_getenv_enetaddr("eth1addr", enetaddr);
  334. fec_set_hwaddr(fecp, enetaddr);
  335. /* Set Opcode/Pause Duration Register */
  336. fecp->opd = 0x00010020;
  337. /* Setup Buffers and Buffer Desriptors */
  338. info->rxIdx = 0;
  339. info->txIdx = 0;
  340. /* Setup Receiver Buffer Descriptors (13.14.24.18)
  341. * Settings: Empty, Wrap */
  342. for (i = 0; i < PKTBUFSRX; i++) {
  343. info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
  344. info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
  345. info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
  346. }
  347. info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
  348. /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
  349. * Settings: Last, Tx CRC */
  350. for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
  351. info->txbd[i].cbd_sc = 0;
  352. info->txbd[i].cbd_datlen = 0;
  353. info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
  354. }
  355. info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
  356. info->usedTbdIdx = 0;
  357. info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER;
  358. /* Set Rx FIFO alarm and granularity value */
  359. fecp->rfcr = 0x0c000000;
  360. fecp->rfar = 0x0000030c;
  361. /* Set Tx FIFO granularity value */
  362. fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
  363. fecp->tfar = 0x00000080;
  364. fecp->tfwr = 0x2;
  365. fecp->ctcwr = 0x03000000;
  366. /* Enable DMA receive task */
  367. MCD_startDma(info->rxTask, /* Dma channel */
  368. (s8 *) info->rxbd, /*Source Address */
  369. 0, /* Source increment */
  370. (s8 *) (&fecp->rfdr), /* dest */
  371. 4, /* dest increment */
  372. 0, /* DMA size */
  373. 4, /* xfer size */
  374. info->rxInit, /* initiator */
  375. info->rxPri, /* priority */
  376. (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */
  377. (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */
  378. );
  379. /* Enable DMA tx task with no ready buffer descriptors */
  380. MCD_startDma(info->txTask, /* Dma channel */
  381. (s8 *) info->txbd, /*Source Address */
  382. 0, /* Source increment */
  383. (s8 *) (&fecp->tfdr), /* dest */
  384. 4, /* dest incr */
  385. 0, /* DMA size */
  386. 4, /* xfer size */
  387. info->txInit, /* initiator */
  388. info->txPri, /* priority */
  389. (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */
  390. (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */
  391. );
  392. /* Now enable the transmit and receive processing */
  393. fecp->ecr |= FEC_ECR_ETHER_EN;
  394. return 1;
  395. }
  396. static void fec_halt(struct eth_device *dev)
  397. {
  398. struct fec_info_dma *info = dev->priv;
  399. volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
  400. int counter = 0xffff;
  401. /* issue graceful stop command to the FEC transmitter if necessary */
  402. fecp->tcr |= FEC_TCR_GTS;
  403. /* wait for graceful stop to register */
  404. while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ;
  405. /* Disable DMA tasks */
  406. MCD_killDma(info->txTask);
  407. MCD_killDma(info->rxTask);
  408. /* Disable the Ethernet Controller */
  409. fecp->ecr &= ~FEC_ECR_ETHER_EN;
  410. /* Clear FIFO status registers */
  411. fecp->rfsr &= FIFO_ERRSTAT;
  412. fecp->tfsr &= FIFO_ERRSTAT;
  413. fecp->frst = 0x01000000;
  414. /* Issue a reset command to the FEC chip */
  415. fecp->ecr |= FEC_ECR_RESET;
  416. /* wait at least 20 clock cycles */
  417. udelay(10000);
  418. #ifdef ET_DEBUG
  419. printf("Ethernet task stopped\n");
  420. #endif
  421. }
  422. int mcdmafec_initialize(bd_t * bis)
  423. {
  424. struct eth_device *dev;
  425. int i;
  426. #ifdef CONFIG_SYS_DMA_USE_INTSRAM
  427. u32 tmp = CONFIG_SYS_INTSRAM + 0x2000;
  428. #endif
  429. for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
  430. dev =
  431. (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
  432. sizeof *dev);
  433. if (dev == NULL)
  434. hang();
  435. memset(dev, 0, sizeof(*dev));
  436. sprintf(dev->name, "FEC%d", fec_info[i].index);
  437. dev->priv = &fec_info[i];
  438. dev->init = fec_init;
  439. dev->halt = fec_halt;
  440. dev->send = fec_send;
  441. dev->recv = fec_recv;
  442. /* setup Receive and Transmit buffer descriptor */
  443. #ifdef CONFIG_SYS_DMA_USE_INTSRAM
  444. fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
  445. tmp = (u32)fec_info[i].rxbd;
  446. fec_info[i].txbd =
  447. (cbd_t *)((u32)fec_info[i].txbd + tmp +
  448. (PKTBUFSRX * sizeof(cbd_t)));
  449. tmp = (u32)fec_info[i].txbd;
  450. fec_info[i].txbuf =
  451. (char *)((u32)fec_info[i].txbuf + tmp +
  452. (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
  453. tmp = (u32)fec_info[i].txbuf;
  454. #else
  455. fec_info[i].rxbd =
  456. (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
  457. (PKTBUFSRX * sizeof(cbd_t)));
  458. fec_info[i].txbd =
  459. (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
  460. (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
  461. fec_info[i].txbuf =
  462. (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
  463. #endif
  464. #ifdef ET_DEBUG
  465. printf("rxbd %x txbd %x\n",
  466. (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
  467. #endif
  468. fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
  469. eth_register(dev);
  470. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  471. int retval;
  472. struct mii_dev *mdiodev = mdio_alloc();
  473. if (!mdiodev)
  474. return -ENOMEM;
  475. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  476. mdiodev->read = mcffec_miiphy_read;
  477. mdiodev->write = mcffec_miiphy_write;
  478. retval = mdio_register(mdiodev);
  479. if (retval < 0)
  480. return retval;
  481. #endif
  482. if (i > 0)
  483. fec_info[i - 1].next = &fec_info[i];
  484. }
  485. fec_info[i - 1].next = &fec_info[0];
  486. /* default speed */
  487. bis->bi_ethspeed = 10;
  488. return 0;
  489. }