ddr3_spd.c 37 KB

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  1. /*
  2. * Copyright (C) Marvell International Ltd. and its affiliates
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <spl.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/soc.h>
  12. #include "ddr3_init.h"
  13. #if defined(MV88F78X60)
  14. #include "ddr3_axp_config.h"
  15. #elif defined(MV88F67XX)
  16. #include "ddr3_a370_config.h"
  17. #endif
  18. #if defined(MV88F672X)
  19. #include "ddr3_a375_config.h"
  20. #endif
  21. #ifdef DUNIT_SPD
  22. /* DIMM SPD offsets */
  23. #define SPD_DEV_TYPE_BYTE 2
  24. #define SPD_MODULE_TYPE_BYTE 3
  25. #define SPD_MODULE_MASK 0xf
  26. #define SPD_MODULE_TYPE_RDIMM 1
  27. #define SPD_MODULE_TYPE_UDIMM 2
  28. #define SPD_DEV_DENSITY_BYTE 4
  29. #define SPD_DEV_DENSITY_MASK 0xf
  30. #define SPD_ROW_NUM_BYTE 5
  31. #define SPD_ROW_NUM_MIN 12
  32. #define SPD_ROW_NUM_OFF 3
  33. #define SPD_ROW_NUM_MASK (7 << SPD_ROW_NUM_OFF)
  34. #define SPD_COL_NUM_BYTE 5
  35. #define SPD_COL_NUM_MIN 9
  36. #define SPD_COL_NUM_OFF 0
  37. #define SPD_COL_NUM_MASK (7 << SPD_COL_NUM_OFF)
  38. #define SPD_MODULE_ORG_BYTE 7
  39. #define SPD_MODULE_SDRAM_DEV_WIDTH_OFF 0
  40. #define SPD_MODULE_SDRAM_DEV_WIDTH_MASK (7 << SPD_MODULE_SDRAM_DEV_WIDTH_OFF)
  41. #define SPD_MODULE_BANK_NUM_MIN 1
  42. #define SPD_MODULE_BANK_NUM_OFF 3
  43. #define SPD_MODULE_BANK_NUM_MASK (7 << SPD_MODULE_BANK_NUM_OFF)
  44. #define SPD_BUS_WIDTH_BYTE 8
  45. #define SPD_BUS_WIDTH_OFF 0
  46. #define SPD_BUS_WIDTH_MASK (7 << SPD_BUS_WIDTH_OFF)
  47. #define SPD_BUS_ECC_OFF 3
  48. #define SPD_BUS_ECC_MASK (3 << SPD_BUS_ECC_OFF)
  49. #define SPD_MTB_DIVIDEND_BYTE 10
  50. #define SPD_MTB_DIVISOR_BYTE 11
  51. #define SPD_TCK_BYTE 12
  52. #define SPD_SUP_CAS_LAT_LSB_BYTE 14
  53. #define SPD_SUP_CAS_LAT_MSB_BYTE 15
  54. #define SPD_TAA_BYTE 16
  55. #define SPD_TWR_BYTE 17
  56. #define SPD_TRCD_BYTE 18
  57. #define SPD_TRRD_BYTE 19
  58. #define SPD_TRP_BYTE 20
  59. #define SPD_TRAS_MSB_BYTE 21
  60. #define SPD_TRAS_MSB_MASK 0xf
  61. #define SPD_TRC_MSB_BYTE 21
  62. #define SPD_TRC_MSB_MASK 0xf0
  63. #define SPD_TRAS_LSB_BYTE 22
  64. #define SPD_TRC_LSB_BYTE 23
  65. #define SPD_TRFC_LSB_BYTE 24
  66. #define SPD_TRFC_MSB_BYTE 25
  67. #define SPD_TWTR_BYTE 26
  68. #define SPD_TRTP_BYTE 27
  69. #define SPD_TFAW_MSB_BYTE 28
  70. #define SPD_TFAW_MSB_MASK 0xf
  71. #define SPD_TFAW_LSB_BYTE 29
  72. #define SPD_OPT_FEATURES_BYTE 30
  73. #define SPD_THERMAL_REFRESH_OPT_BYTE 31
  74. #define SPD_ADDR_MAP_BYTE 63
  75. #define SPD_ADDR_MAP_MIRROR_OFFS 0
  76. #define SPD_RDIMM_RC_BYTE 69
  77. #define SPD_RDIMM_RC_NIBBLE_MASK 0xF
  78. #define SPD_RDIMM_RC_NUM 16
  79. /* Dimm Memory Type values */
  80. #define SPD_MEM_TYPE_SDRAM 0x4
  81. #define SPD_MEM_TYPE_DDR1 0x7
  82. #define SPD_MEM_TYPE_DDR2 0x8
  83. #define SPD_MEM_TYPE_DDR3 0xB
  84. #define DIMM_MODULE_MANU_OFFS 64
  85. #define DIMM_MODULE_MANU_SIZE 8
  86. #define DIMM_MODULE_VEN_OFFS 73
  87. #define DIMM_MODULE_VEN_SIZE 25
  88. #define DIMM_MODULE_ID_OFFS 99
  89. #define DIMM_MODULE_ID_SIZE 18
  90. /* enumeration for voltage levels. */
  91. enum dimm_volt_if {
  92. TTL_5V_TOLERANT,
  93. LVTTL,
  94. HSTL_1_5V,
  95. SSTL_3_3V,
  96. SSTL_2_5V,
  97. VOLTAGE_UNKNOWN,
  98. };
  99. /* enumaration for SDRAM CAS Latencies. */
  100. enum dimm_sdram_cas {
  101. SD_CL_1 = 1,
  102. SD_CL_2,
  103. SD_CL_3,
  104. SD_CL_4,
  105. SD_CL_5,
  106. SD_CL_6,
  107. SD_CL_7,
  108. SD_FAULT
  109. };
  110. /* enumeration for memory types */
  111. enum memory_type {
  112. MEM_TYPE_SDRAM,
  113. MEM_TYPE_DDR1,
  114. MEM_TYPE_DDR2,
  115. MEM_TYPE_DDR3
  116. };
  117. /* DIMM information structure */
  118. typedef struct dimm_info {
  119. /* DIMM dimensions */
  120. u32 num_of_module_ranks;
  121. u32 data_width;
  122. u32 rank_capacity;
  123. u32 num_of_devices;
  124. u32 sdram_width;
  125. u32 num_of_banks_on_each_device;
  126. u32 sdram_capacity;
  127. u32 num_of_row_addr;
  128. u32 num_of_col_addr;
  129. u32 addr_mirroring;
  130. u32 err_check_type; /* ECC , PARITY.. */
  131. u32 type_info; /* DDR2 only */
  132. /* DIMM timing parameters */
  133. u32 supported_cas_latencies;
  134. u32 refresh_interval;
  135. u32 min_cycle_time;
  136. u32 min_row_precharge_time;
  137. u32 min_row_active_to_row_active;
  138. u32 min_ras_to_cas_delay;
  139. u32 min_write_recovery_time; /* DDR3/2 only */
  140. u32 min_write_to_read_cmd_delay; /* DDR3/2 only */
  141. u32 min_read_to_prech_cmd_delay; /* DDR3/2 only */
  142. u32 min_active_to_precharge;
  143. u32 min_refresh_recovery; /* DDR3/2 only */
  144. u32 min_cas_lat_time;
  145. u32 min_four_active_win_delay;
  146. u8 dimm_rc[SPD_RDIMM_RC_NUM];
  147. /* DIMM vendor ID */
  148. u32 vendor;
  149. } MV_DIMM_INFO;
  150. static int ddr3_spd_sum_init(MV_DIMM_INFO *info, MV_DIMM_INFO *sum_info,
  151. u32 dimm);
  152. static u32 ddr3_get_max_val(u32 spd_val, u32 dimm_num, u32 static_val);
  153. static u32 ddr3_get_min_val(u32 spd_val, u32 dimm_num, u32 static_val);
  154. static int ddr3_spd_init(MV_DIMM_INFO *info, u32 dimm_addr, u32 dimm_width);
  155. static u32 ddr3_div(u32 val, u32 divider, u32 sub);
  156. extern u8 spd_data[SPD_SIZE];
  157. extern u32 odt_config[ODT_OPT];
  158. extern u16 odt_static[ODT_OPT][MAX_CS];
  159. extern u16 odt_dynamic[ODT_OPT][MAX_CS];
  160. #if !(defined(DB_88F6710) || defined(DB_88F6710_PCAC) || defined(RD_88F6710))
  161. /*
  162. * Name: ddr3_get_dimm_num - Find number of dimms and their addresses
  163. * Desc:
  164. * Args: dimm_addr - array of dimm addresses
  165. * Notes:
  166. * Returns: None.
  167. */
  168. static u32 ddr3_get_dimm_num(u32 *dimm_addr)
  169. {
  170. u32 dimm_cur_addr;
  171. u8 data[3];
  172. u32 dimm_num = 0;
  173. int ret;
  174. /* Read the dimm eeprom */
  175. for (dimm_cur_addr = MAX_DIMM_ADDR; dimm_cur_addr > MIN_DIMM_ADDR;
  176. dimm_cur_addr--) {
  177. data[SPD_DEV_TYPE_BYTE] = 0;
  178. /* Far-End DIMM must be connected */
  179. if ((dimm_num == 0) && (dimm_cur_addr < FAR_END_DIMM_ADDR))
  180. return 0;
  181. ret = i2c_read(dimm_cur_addr, 0, 1, (uchar *)data, 3);
  182. if (!ret) {
  183. if (data[SPD_DEV_TYPE_BYTE] == SPD_MEM_TYPE_DDR3) {
  184. dimm_addr[dimm_num] = dimm_cur_addr;
  185. dimm_num++;
  186. }
  187. }
  188. }
  189. return dimm_num;
  190. }
  191. #endif
  192. /*
  193. * Name: dimmSpdInit - Get the SPD parameters.
  194. * Desc: Read the DIMM SPD parameters into given struct parameter.
  195. * Args: dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator.
  196. * info - DIMM information structure.
  197. * Notes:
  198. * Returns: MV_OK if function could read DIMM parameters, 0 otherwise.
  199. */
  200. int ddr3_spd_init(MV_DIMM_INFO *info, u32 dimm_addr, u32 dimm_width)
  201. {
  202. u32 tmp;
  203. u32 time_base;
  204. int ret;
  205. __maybe_unused u32 rc;
  206. __maybe_unused u8 vendor_high, vendor_low;
  207. if (dimm_addr != 0) {
  208. memset(spd_data, 0, SPD_SIZE * sizeof(u8));
  209. ret = i2c_read(dimm_addr, 0, 1, (uchar *)spd_data, SPD_SIZE);
  210. if (ret)
  211. return MV_DDR3_TRAINING_ERR_TWSI_FAIL;
  212. }
  213. /* Check if DDR3 */
  214. if (spd_data[SPD_DEV_TYPE_BYTE] != SPD_MEM_TYPE_DDR3)
  215. return MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE;
  216. /* Error Check Type */
  217. /* No byte for error check in DDR3 SPD, use DDR2 convention */
  218. info->err_check_type = 0;
  219. /* Check if ECC */
  220. if ((spd_data[SPD_BUS_WIDTH_BYTE] & 0x18) >> 3)
  221. info->err_check_type = 1;
  222. DEBUG_INIT_FULL_C("DRAM err_check_type ", info->err_check_type, 1);
  223. switch (spd_data[SPD_MODULE_TYPE_BYTE]) {
  224. case 1:
  225. /* support RDIMM */
  226. info->type_info = SPD_MODULE_TYPE_RDIMM;
  227. break;
  228. case 2:
  229. /* support UDIMM */
  230. info->type_info = SPD_MODULE_TYPE_UDIMM;
  231. break;
  232. case 11: /* LRDIMM current not supported */
  233. default:
  234. info->type_info = (spd_data[SPD_MODULE_TYPE_BYTE]);
  235. break;
  236. }
  237. /* Size Calculations: */
  238. /* Number Of Row Addresses - 12/13/14/15/16 */
  239. info->num_of_row_addr =
  240. (spd_data[SPD_ROW_NUM_BYTE] & SPD_ROW_NUM_MASK) >>
  241. SPD_ROW_NUM_OFF;
  242. info->num_of_row_addr += SPD_ROW_NUM_MIN;
  243. DEBUG_INIT_FULL_C("DRAM num_of_row_addr ", info->num_of_row_addr, 2);
  244. /* Number Of Column Addresses - 9/10/11/12 */
  245. info->num_of_col_addr =
  246. (spd_data[SPD_COL_NUM_BYTE] & SPD_COL_NUM_MASK) >>
  247. SPD_COL_NUM_OFF;
  248. info->num_of_col_addr += SPD_COL_NUM_MIN;
  249. DEBUG_INIT_FULL_C("DRAM num_of_col_addr ", info->num_of_col_addr, 1);
  250. /* Number Of Ranks = number of CS on Dimm - 1/2/3/4 Ranks */
  251. info->num_of_module_ranks =
  252. (spd_data[SPD_MODULE_ORG_BYTE] & SPD_MODULE_BANK_NUM_MASK) >>
  253. SPD_MODULE_BANK_NUM_OFF;
  254. info->num_of_module_ranks += SPD_MODULE_BANK_NUM_MIN;
  255. DEBUG_INIT_FULL_C("DRAM numOfModuleBanks ", info->num_of_module_ranks,
  256. 1);
  257. /* Data Width - 8/16/32/64 bits */
  258. info->data_width =
  259. 1 << (3 + (spd_data[SPD_BUS_WIDTH_BYTE] & SPD_BUS_WIDTH_MASK));
  260. DEBUG_INIT_FULL_C("DRAM data_width ", info->data_width, 1);
  261. /* Number Of Banks On Each Device - 8/16/32/64 banks */
  262. info->num_of_banks_on_each_device =
  263. 1 << (3 + ((spd_data[SPD_DEV_DENSITY_BYTE] >> 4) & 0x7));
  264. DEBUG_INIT_FULL_C("DRAM num_of_banks_on_each_device ",
  265. info->num_of_banks_on_each_device, 1);
  266. /* Total SDRAM capacity - 256Mb/512Mb/1Gb/2Gb/4Gb/8Gb/16Gb - MegaBits */
  267. info->sdram_capacity =
  268. spd_data[SPD_DEV_DENSITY_BYTE] & SPD_DEV_DENSITY_MASK;
  269. /* Sdram Width - 4/8/16/32 bits */
  270. info->sdram_width = 1 << (2 + (spd_data[SPD_MODULE_ORG_BYTE] &
  271. SPD_MODULE_SDRAM_DEV_WIDTH_MASK));
  272. DEBUG_INIT_FULL_C("DRAM sdram_width ", info->sdram_width, 1);
  273. /* CS (Rank) Capacity - MB */
  274. /*
  275. * DDR3 device uiDensity val are: (device capacity/8) *
  276. * (Module_width/Device_width)
  277. */
  278. /* Jedec SPD DDR3 - page 7, Save spd_data in Mb - 2048=2GB */
  279. if (dimm_width == 32) {
  280. info->rank_capacity =
  281. ((1 << info->sdram_capacity) * 256 *
  282. (info->data_width / info->sdram_width)) << 16;
  283. /* CS size = CS size / 2 */
  284. } else {
  285. info->rank_capacity =
  286. ((1 << info->sdram_capacity) * 256 *
  287. (info->data_width / info->sdram_width) * 0x2) << 16;
  288. /* 0x2 => 0x100000-1Mbit / 8-bit->byte / 0x10000 */
  289. }
  290. DEBUG_INIT_FULL_C("DRAM rank_capacity[31] ", info->rank_capacity, 1);
  291. /* Number of devices includeing Error correction */
  292. info->num_of_devices =
  293. ((info->data_width / info->sdram_width) *
  294. info->num_of_module_ranks) + info->err_check_type;
  295. DEBUG_INIT_FULL_C("DRAM num_of_devices ", info->num_of_devices, 1);
  296. /* Address Mapping from Edge connector to DRAM - mirroring option */
  297. info->addr_mirroring =
  298. spd_data[SPD_ADDR_MAP_BYTE] & (1 << SPD_ADDR_MAP_MIRROR_OFFS);
  299. /* Timings - All in ps */
  300. time_base = (1000 * spd_data[SPD_MTB_DIVIDEND_BYTE]) /
  301. spd_data[SPD_MTB_DIVISOR_BYTE];
  302. /* Minimum Cycle Time At Max CasLatancy */
  303. info->min_cycle_time = spd_data[SPD_TCK_BYTE] * time_base;
  304. DEBUG_INIT_FULL_C("DRAM tCKmin ", info->min_cycle_time, 1);
  305. /* Refresh Interval */
  306. /* No byte for refresh interval in DDR3 SPD, use DDR2 convention */
  307. /*
  308. * JEDEC param are 0 <= Tcase <= 85: 7.8uSec, 85 <= Tcase
  309. * <= 95: 3.9uSec
  310. */
  311. info->refresh_interval = 7800000; /* Set to 7.8uSec */
  312. DEBUG_INIT_FULL_C("DRAM refresh_interval ", info->refresh_interval, 1);
  313. /* Suported Cas Latencies - DDR 3: */
  314. /*
  315. * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
  316. *******-******-******-******-******-******-******-*******-*******
  317. CAS = 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 *
  318. *********************************************************-*******
  319. *******-******-******-******-******-******-******-*******-*******
  320. * bit15 |bit14 |bit13 |bit12 |bit11 |bit10 | bit9 | bit8 *
  321. *******-******-******-******-******-******-******-*******-*******
  322. CAS = TBD | 18 | 17 | 16 | 15 | 14 | 13 | 12 *
  323. */
  324. /* DDR3 include 2 byte of CAS support */
  325. info->supported_cas_latencies =
  326. (spd_data[SPD_SUP_CAS_LAT_MSB_BYTE] << 8) |
  327. spd_data[SPD_SUP_CAS_LAT_LSB_BYTE];
  328. DEBUG_INIT_FULL_C("DRAM supported_cas_latencies ",
  329. info->supported_cas_latencies, 1);
  330. /* Minimum Cycle Time At Max CasLatancy */
  331. info->min_cas_lat_time = (spd_data[SPD_TAA_BYTE] * time_base);
  332. /*
  333. * This field divided by the cycleTime will give us the CAS latency
  334. * to config
  335. */
  336. /*
  337. * For DDR3 and DDR2 includes Write Recovery Time field.
  338. * Other SDRAM ignore
  339. */
  340. info->min_write_recovery_time = spd_data[SPD_TWR_BYTE] * time_base;
  341. DEBUG_INIT_FULL_C("DRAM min_write_recovery_time ",
  342. info->min_write_recovery_time, 1);
  343. /* Mininmum Ras to Cas Delay */
  344. info->min_ras_to_cas_delay = spd_data[SPD_TRCD_BYTE] * time_base;
  345. DEBUG_INIT_FULL_C("DRAM min_ras_to_cas_delay ",
  346. info->min_ras_to_cas_delay, 1);
  347. /* Minimum Row Active to Row Active Time */
  348. info->min_row_active_to_row_active =
  349. spd_data[SPD_TRRD_BYTE] * time_base;
  350. DEBUG_INIT_FULL_C("DRAM min_row_active_to_row_active ",
  351. info->min_row_active_to_row_active, 1);
  352. /* Minimum Row Precharge Delay Time */
  353. info->min_row_precharge_time = spd_data[SPD_TRP_BYTE] * time_base;
  354. DEBUG_INIT_FULL_C("DRAM min_row_precharge_time ",
  355. info->min_row_precharge_time, 1);
  356. /* Minimum Active to Precharge Delay Time - tRAS ps */
  357. info->min_active_to_precharge =
  358. (spd_data[SPD_TRAS_MSB_BYTE] & SPD_TRAS_MSB_MASK) << 8;
  359. info->min_active_to_precharge |= spd_data[SPD_TRAS_LSB_BYTE];
  360. info->min_active_to_precharge *= time_base;
  361. DEBUG_INIT_FULL_C("DRAM min_active_to_precharge ",
  362. info->min_active_to_precharge, 1);
  363. /* Minimum Refresh Recovery Delay Time - tRFC ps */
  364. info->min_refresh_recovery = spd_data[SPD_TRFC_MSB_BYTE] << 8;
  365. info->min_refresh_recovery |= spd_data[SPD_TRFC_LSB_BYTE];
  366. info->min_refresh_recovery *= time_base;
  367. DEBUG_INIT_FULL_C("DRAM min_refresh_recovery ",
  368. info->min_refresh_recovery, 1);
  369. /*
  370. * For DDR3 and DDR2 includes Internal Write To Read Command Delay
  371. * field.
  372. */
  373. info->min_write_to_read_cmd_delay = spd_data[SPD_TWTR_BYTE] * time_base;
  374. DEBUG_INIT_FULL_C("DRAM min_write_to_read_cmd_delay ",
  375. info->min_write_to_read_cmd_delay, 1);
  376. /*
  377. * For DDR3 and DDR2 includes Internal Read To Precharge Command Delay
  378. * field.
  379. */
  380. info->min_read_to_prech_cmd_delay = spd_data[SPD_TRTP_BYTE] * time_base;
  381. DEBUG_INIT_FULL_C("DRAM min_read_to_prech_cmd_delay ",
  382. info->min_read_to_prech_cmd_delay, 1);
  383. /*
  384. * For DDR3 includes Minimum Activate to Activate/Refresh Command
  385. * field
  386. */
  387. tmp = ((spd_data[SPD_TFAW_MSB_BYTE] & SPD_TFAW_MSB_MASK) << 8) |
  388. spd_data[SPD_TFAW_LSB_BYTE];
  389. info->min_four_active_win_delay = tmp * time_base;
  390. DEBUG_INIT_FULL_C("DRAM min_four_active_win_delay ",
  391. info->min_four_active_win_delay, 1);
  392. #if defined(MV88F78X60) || defined(MV88F672X)
  393. /* Registered DIMM support */
  394. if (info->type_info == SPD_MODULE_TYPE_RDIMM) {
  395. for (rc = 2; rc < 6; rc += 2) {
  396. tmp = spd_data[SPD_RDIMM_RC_BYTE + rc / 2];
  397. info->dimm_rc[rc] =
  398. spd_data[SPD_RDIMM_RC_BYTE + rc / 2] &
  399. SPD_RDIMM_RC_NIBBLE_MASK;
  400. info->dimm_rc[rc + 1] =
  401. (spd_data[SPD_RDIMM_RC_BYTE + rc / 2] >> 4) &
  402. SPD_RDIMM_RC_NIBBLE_MASK;
  403. }
  404. vendor_low = spd_data[66];
  405. vendor_high = spd_data[65];
  406. info->vendor = (vendor_high << 8) + vendor_low;
  407. DEBUG_INIT_C("DDR3 Training Sequence - Registered DIMM vendor ID 0x",
  408. info->vendor, 4);
  409. info->dimm_rc[0] = RDIMM_RC0;
  410. info->dimm_rc[1] = RDIMM_RC1;
  411. info->dimm_rc[2] = RDIMM_RC2;
  412. info->dimm_rc[8] = RDIMM_RC8;
  413. info->dimm_rc[9] = RDIMM_RC9;
  414. info->dimm_rc[10] = RDIMM_RC10;
  415. info->dimm_rc[11] = RDIMM_RC11;
  416. }
  417. #endif
  418. return MV_OK;
  419. }
  420. /*
  421. * Name: ddr3_spd_sum_init - Get the SPD parameters.
  422. * Desc: Read the DIMM SPD parameters into given struct parameter.
  423. * Args: dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator.
  424. * info - DIMM information structure.
  425. * Notes:
  426. * Returns: MV_OK if function could read DIMM parameters, 0 otherwise.
  427. */
  428. int ddr3_spd_sum_init(MV_DIMM_INFO *info, MV_DIMM_INFO *sum_info, u32 dimm)
  429. {
  430. if (dimm == 0) {
  431. memcpy(sum_info, info, sizeof(MV_DIMM_INFO));
  432. return MV_OK;
  433. }
  434. if (sum_info->type_info != info->type_info) {
  435. DEBUG_INIT_S("DDR3 Dimm Compare - DIMM type does not match - FAIL\n");
  436. return MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH;
  437. }
  438. if (sum_info->err_check_type > info->err_check_type) {
  439. sum_info->err_check_type = info->err_check_type;
  440. DEBUG_INIT_S("DDR3 Dimm Compare - ECC does not match. ECC is disabled\n");
  441. }
  442. if (sum_info->data_width != info->data_width) {
  443. DEBUG_INIT_S("DDR3 Dimm Compare - DRAM bus width does not match - FAIL\n");
  444. return MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH;
  445. }
  446. if (sum_info->min_cycle_time < info->min_cycle_time)
  447. sum_info->min_cycle_time = info->min_cycle_time;
  448. if (sum_info->refresh_interval < info->refresh_interval)
  449. sum_info->refresh_interval = info->refresh_interval;
  450. sum_info->supported_cas_latencies &= info->supported_cas_latencies;
  451. if (sum_info->min_cas_lat_time < info->min_cas_lat_time)
  452. sum_info->min_cas_lat_time = info->min_cas_lat_time;
  453. if (sum_info->min_write_recovery_time < info->min_write_recovery_time)
  454. sum_info->min_write_recovery_time =
  455. info->min_write_recovery_time;
  456. if (sum_info->min_ras_to_cas_delay < info->min_ras_to_cas_delay)
  457. sum_info->min_ras_to_cas_delay = info->min_ras_to_cas_delay;
  458. if (sum_info->min_row_active_to_row_active <
  459. info->min_row_active_to_row_active)
  460. sum_info->min_row_active_to_row_active =
  461. info->min_row_active_to_row_active;
  462. if (sum_info->min_row_precharge_time < info->min_row_precharge_time)
  463. sum_info->min_row_precharge_time = info->min_row_precharge_time;
  464. if (sum_info->min_active_to_precharge < info->min_active_to_precharge)
  465. sum_info->min_active_to_precharge =
  466. info->min_active_to_precharge;
  467. if (sum_info->min_refresh_recovery < info->min_refresh_recovery)
  468. sum_info->min_refresh_recovery = info->min_refresh_recovery;
  469. if (sum_info->min_write_to_read_cmd_delay <
  470. info->min_write_to_read_cmd_delay)
  471. sum_info->min_write_to_read_cmd_delay =
  472. info->min_write_to_read_cmd_delay;
  473. if (sum_info->min_read_to_prech_cmd_delay <
  474. info->min_read_to_prech_cmd_delay)
  475. sum_info->min_read_to_prech_cmd_delay =
  476. info->min_read_to_prech_cmd_delay;
  477. if (sum_info->min_four_active_win_delay <
  478. info->min_four_active_win_delay)
  479. sum_info->min_four_active_win_delay =
  480. info->min_four_active_win_delay;
  481. if (sum_info->min_write_to_read_cmd_delay <
  482. info->min_write_to_read_cmd_delay)
  483. sum_info->min_write_to_read_cmd_delay =
  484. info->min_write_to_read_cmd_delay;
  485. return MV_OK;
  486. }
  487. /*
  488. * Name: ddr3_dunit_setup
  489. * Desc: Set the controller with the timing values.
  490. * Args: ecc_ena - User ECC setup
  491. * Notes:
  492. * Returns:
  493. */
  494. int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width)
  495. {
  496. u32 reg, tmp, cwl;
  497. u32 ddr_clk_time;
  498. MV_DIMM_INFO dimm_info[2];
  499. MV_DIMM_INFO sum_info;
  500. u32 stat_val, spd_val;
  501. u32 cs, cl, cs_num, cs_ena;
  502. u32 dimm_num = 0;
  503. int status;
  504. u32 rc;
  505. __maybe_unused u32 dimm_cnt, cs_count, dimm;
  506. __maybe_unused u32 dimm_addr[2] = { 0, 0 };
  507. #if defined(DB_88F6710) || defined(DB_88F6710_PCAC) || defined(RD_88F6710)
  508. /* Armada 370 - SPD is not available on DIMM */
  509. /*
  510. * Set MC registers according to Static SPD values Values -
  511. * must be set manually
  512. */
  513. /*
  514. * We only have one optional DIMM for the DB and we already got the
  515. * SPD matching values
  516. */
  517. status = ddr3_spd_init(&dimm_info[0], 0, *ddr_width);
  518. if (MV_OK != status)
  519. return status;
  520. dimm_num = 1;
  521. /* Use JP8 to enable multiCS support for Armada 370 DB */
  522. if (!ddr3_check_config(EEPROM_MODULE_ADDR, CONFIG_MULTI_CS))
  523. dimm_info[0].num_of_module_ranks = 1;
  524. status = ddr3_spd_sum_init(&dimm_info[0], &sum_info, 0);
  525. if (MV_OK != status)
  526. return status;
  527. #else
  528. /* Dynamic D-Unit Setup - Read SPD values */
  529. #ifdef DUNIT_SPD
  530. dimm_num = ddr3_get_dimm_num(dimm_addr);
  531. if (dimm_num == 0) {
  532. #ifdef MIXED_DIMM_STATIC
  533. DEBUG_INIT_S("DDR3 Training Sequence - No DIMMs detected\n");
  534. #else
  535. DEBUG_INIT_S("DDR3 Training Sequence - FAILED (Wrong DIMMs Setup)\n");
  536. return MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP;
  537. #endif
  538. } else {
  539. DEBUG_INIT_C("DDR3 Training Sequence - Number of DIMMs detected: ",
  540. dimm_num, 1);
  541. }
  542. for (dimm = 0; dimm < dimm_num; dimm++) {
  543. status = ddr3_spd_init(&dimm_info[dimm], dimm_addr[dimm],
  544. *ddr_width);
  545. if (MV_OK != status)
  546. return status;
  547. status = ddr3_spd_sum_init(&dimm_info[dimm], &sum_info, dimm);
  548. if (MV_OK != status)
  549. return status;
  550. }
  551. #endif
  552. #endif
  553. /* Set number of enabled CS */
  554. cs_num = 0;
  555. #ifdef DUNIT_STATIC
  556. cs_num = ddr3_get_cs_num_from_reg();
  557. #endif
  558. #ifdef DUNIT_SPD
  559. for (dimm = 0; dimm < dimm_num; dimm++)
  560. cs_num += dimm_info[dimm].num_of_module_ranks;
  561. #endif
  562. if (cs_num > MAX_CS) {
  563. DEBUG_INIT_C("DDR3 Training Sequence - Number of CS exceed limit - ",
  564. MAX_CS, 1);
  565. return MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT;
  566. }
  567. /* Set bitmap of enabled CS */
  568. cs_ena = 0;
  569. #ifdef DUNIT_STATIC
  570. cs_ena = ddr3_get_cs_ena_from_reg();
  571. #endif
  572. #ifdef DUNIT_SPD
  573. dimm = 0;
  574. if (dimm_num) {
  575. for (cs = 0; cs < MAX_CS; cs += 2) {
  576. if (((1 << cs) & DIMM_CS_BITMAP) &&
  577. !(cs_ena & (1 << cs))) {
  578. if (dimm_info[dimm].num_of_module_ranks == 1)
  579. cs_ena |= (0x1 << cs);
  580. else if (dimm_info[dimm].num_of_module_ranks == 2)
  581. cs_ena |= (0x3 << cs);
  582. else if (dimm_info[dimm].num_of_module_ranks == 3)
  583. cs_ena |= (0x7 << cs);
  584. else if (dimm_info[dimm].num_of_module_ranks == 4)
  585. cs_ena |= (0xF << cs);
  586. dimm++;
  587. if (dimm == dimm_num)
  588. break;
  589. }
  590. }
  591. }
  592. #endif
  593. if (cs_ena > 0xF) {
  594. DEBUG_INIT_C("DDR3 Training Sequence - Number of enabled CS exceed limit - ",
  595. MAX_CS, 1);
  596. return MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT;
  597. }
  598. DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - Number of CS = ", cs_num, 1);
  599. /* Check Ratio - '1' - 2:1, '0' - 1:1 */
  600. if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
  601. ddr_clk_time = hclk_time / 2;
  602. else
  603. ddr_clk_time = hclk_time;
  604. #ifdef DUNIT_STATIC
  605. /* Get target CL value from set register */
  606. reg = (reg_read(REG_DDR3_MR0_ADDR) >> 2);
  607. reg = ((((reg >> 1) & 0xE)) | (reg & 0x1)) & 0xF;
  608. cl = ddr3_get_max_val(ddr3_div(sum_info.min_cas_lat_time,
  609. ddr_clk_time, 0),
  610. dimm_num, ddr3_valid_cl_to_cl(reg));
  611. #else
  612. cl = ddr3_div(sum_info.min_cas_lat_time, ddr_clk_time, 0);
  613. #endif
  614. if (cl < 5)
  615. cl = 5;
  616. DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - Cas Latency = ", cl, 1);
  617. /* {0x00001400} - DDR SDRAM Configuration Register */
  618. reg = 0x73004000;
  619. stat_val = ddr3_get_static_mc_value(
  620. REG_SDRAM_CONFIG_ADDR, REG_SDRAM_CONFIG_ECC_OFFS, 0x1, 0, 0);
  621. if (ecc_ena && ddr3_get_min_val(sum_info.err_check_type, dimm_num,
  622. stat_val)) {
  623. reg |= (1 << REG_SDRAM_CONFIG_ECC_OFFS);
  624. reg |= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
  625. DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - ECC Enabled\n");
  626. } else {
  627. DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - ECC Disabled\n");
  628. }
  629. if (sum_info.type_info == SPD_MODULE_TYPE_RDIMM) {
  630. #ifdef DUNIT_STATIC
  631. DEBUG_INIT_S("DDR3 Training Sequence - FAIL - Illegal R-DIMM setup\n");
  632. return MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP;
  633. #endif
  634. reg |= (1 << REG_SDRAM_CONFIG_REGDIMM_OFFS);
  635. DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - R-DIMM\n");
  636. } else {
  637. DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - U-DIMM\n");
  638. }
  639. #ifndef MV88F67XX
  640. #ifdef DUNIT_STATIC
  641. if (ddr3_get_min_val(sum_info.data_width, dimm_num, BUS_WIDTH) == 64) {
  642. #else
  643. if (*ddr_width == 64) {
  644. #endif
  645. reg |= (1 << REG_SDRAM_CONFIG_WIDTH_OFFS);
  646. DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 64Bits\n");
  647. } else {
  648. DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 32Bits\n");
  649. }
  650. #else
  651. DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 16Bits\n");
  652. #endif
  653. #if defined(MV88F672X)
  654. if (*ddr_width == 32) {
  655. reg |= (1 << REG_SDRAM_CONFIG_WIDTH_OFFS);
  656. DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 32Bits\n");
  657. } else {
  658. DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 16Bits\n");
  659. }
  660. #endif
  661. stat_val = ddr3_get_static_mc_value(REG_SDRAM_CONFIG_ADDR, 0,
  662. REG_SDRAM_CONFIG_RFRS_MASK, 0, 0);
  663. tmp = ddr3_get_min_val(sum_info.refresh_interval / hclk_time,
  664. dimm_num, stat_val);
  665. #ifdef TREFI_USER_EN
  666. tmp = min(TREFI_USER / hclk_time, tmp);
  667. #endif
  668. DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - RefreshInterval/Hclk = ", tmp, 4);
  669. reg |= tmp;
  670. if (cl != 3)
  671. reg |= (1 << 16); /* If 2:1 need to set P2DWr */
  672. #if defined(MV88F672X)
  673. reg |= (1 << 27); /* PhyRfRST = Disable */
  674. #endif
  675. reg_write(REG_SDRAM_CONFIG_ADDR, reg);
  676. /*{0x00001404} - DDR SDRAM Configuration Register */
  677. reg = 0x3630B800;
  678. #ifdef DUNIT_SPD
  679. reg |= (DRAM_2T << REG_DUNIT_CTRL_LOW_2T_OFFS);
  680. #endif
  681. reg_write(REG_DUNIT_CTRL_LOW_ADDR, reg);
  682. /* {0x00001408} - DDR SDRAM Timing (Low) Register */
  683. reg = 0x0;
  684. /* tRAS - (0:3,20) */
  685. spd_val = ddr3_div(sum_info.min_active_to_precharge,
  686. ddr_clk_time, 1);
  687. stat_val = ddr3_get_static_mc_value(REG_SDRAM_TIMING_LOW_ADDR,
  688. 0, 0xF, 16, 0x10);
  689. tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
  690. DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRAS-1 = ", tmp, 1);
  691. reg |= (tmp & 0xF);
  692. reg |= ((tmp & 0x10) << 16); /* to bit 20 */
  693. /* tRCD - (4:7) */
  694. spd_val = ddr3_div(sum_info.min_ras_to_cas_delay, ddr_clk_time, 1);
  695. stat_val = ddr3_get_static_mc_value(REG_SDRAM_TIMING_LOW_ADDR,
  696. 4, 0xF, 0, 0);
  697. tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
  698. DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRCD-1 = ", tmp, 1);
  699. reg |= ((tmp & 0xF) << 4);
  700. /* tRP - (8:11) */
  701. spd_val = ddr3_div(sum_info.min_row_precharge_time, ddr_clk_time, 1);
  702. stat_val = ddr3_get_static_mc_value(REG_SDRAM_TIMING_LOW_ADDR,
  703. 8, 0xF, 0, 0);
  704. tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
  705. DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRP-1 = ", tmp, 1);
  706. reg |= ((tmp & 0xF) << 8);
  707. /* tWR - (12:15) */
  708. spd_val = ddr3_div(sum_info.min_write_recovery_time, ddr_clk_time, 1);
  709. stat_val = ddr3_get_static_mc_value(REG_SDRAM_TIMING_LOW_ADDR,
  710. 12, 0xF, 0, 0);
  711. tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
  712. DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tWR-1 = ", tmp, 1);
  713. reg |= ((tmp & 0xF) << 12);
  714. /* tWTR - (16:19) */
  715. spd_val = ddr3_div(sum_info.min_write_to_read_cmd_delay, ddr_clk_time, 1);
  716. stat_val = ddr3_get_static_mc_value(REG_SDRAM_TIMING_LOW_ADDR,
  717. 16, 0xF, 0, 0);
  718. tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
  719. DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tWTR-1 = ", tmp, 1);
  720. reg |= ((tmp & 0xF) << 16);
  721. /* tRRD - (24:27) */
  722. spd_val = ddr3_div(sum_info.min_row_active_to_row_active, ddr_clk_time, 1);
  723. stat_val = ddr3_get_static_mc_value(REG_SDRAM_TIMING_LOW_ADDR,
  724. 24, 0xF, 0, 0);
  725. tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
  726. DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRRD-1 = ", tmp, 1);
  727. reg |= ((tmp & 0xF) << 24);
  728. /* tRTP - (28:31) */
  729. spd_val = ddr3_div(sum_info.min_read_to_prech_cmd_delay, ddr_clk_time, 1);
  730. stat_val = ddr3_get_static_mc_value(REG_SDRAM_TIMING_LOW_ADDR,
  731. 28, 0xF, 0, 0);
  732. tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
  733. DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRTP-1 = ", tmp, 1);
  734. reg |= ((tmp & 0xF) << 28);
  735. if (cl < 7)
  736. reg = 0x33137663;
  737. reg_write(REG_SDRAM_TIMING_LOW_ADDR, reg);
  738. /*{0x0000140C} - DDR SDRAM Timing (High) Register */
  739. /* Add cycles to R2R W2W */
  740. reg = 0x39F8FF80;
  741. /* tRFC - (0:6,16:18) */
  742. spd_val = ddr3_div(sum_info.min_refresh_recovery, ddr_clk_time, 1);
  743. stat_val = ddr3_get_static_mc_value(REG_SDRAM_TIMING_HIGH_ADDR,
  744. 0, 0x7F, 9, 0x380);
  745. tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
  746. DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRFC-1 = ", tmp, 1);
  747. reg |= (tmp & 0x7F);
  748. reg |= ((tmp & 0x380) << 9); /* to bit 16 */
  749. reg_write(REG_SDRAM_TIMING_HIGH_ADDR, reg);
  750. /*{0x00001410} - DDR SDRAM Address Control Register */
  751. reg = 0x000F0000;
  752. /* tFAW - (24:28) */
  753. #if (defined(MV88F78X60) || defined(MV88F672X))
  754. tmp = sum_info.min_four_active_win_delay;
  755. spd_val = ddr3_div(tmp, ddr_clk_time, 0);
  756. stat_val = ddr3_get_static_mc_value(REG_SDRAM_ADDRESS_CTRL_ADDR,
  757. 24, 0x3F, 0, 0);
  758. tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
  759. DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tFAW = ", tmp, 1);
  760. reg |= ((tmp & 0x3F) << 24);
  761. #else
  762. tmp = sum_info.min_four_active_win_delay -
  763. 4 * (sum_info.min_row_active_to_row_active);
  764. spd_val = ddr3_div(tmp, ddr_clk_time, 0);
  765. stat_val = ddr3_get_static_mc_value(REG_SDRAM_ADDRESS_CTRL_ADDR,
  766. 24, 0x1F, 0, 0);
  767. tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
  768. DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tFAW-4*tRRD = ", tmp, 1);
  769. reg |= ((tmp & 0x1F) << 24);
  770. #endif
  771. /* SDRAM device capacity */
  772. #ifdef DUNIT_STATIC
  773. reg |= (reg_read(REG_SDRAM_ADDRESS_CTRL_ADDR) & 0xF0FFFF);
  774. #endif
  775. #ifdef DUNIT_SPD
  776. cs_count = 0;
  777. dimm_cnt = 0;
  778. for (cs = 0; cs < MAX_CS; cs++) {
  779. if (cs_ena & (1 << cs) & DIMM_CS_BITMAP) {
  780. if (dimm_info[dimm_cnt].num_of_module_ranks == cs_count) {
  781. dimm_cnt++;
  782. cs_count = 0;
  783. }
  784. cs_count++;
  785. if (dimm_info[dimm_cnt].sdram_capacity < 0x3) {
  786. reg |= ((dimm_info[dimm_cnt].sdram_capacity + 1) <<
  787. (REG_SDRAM_ADDRESS_SIZE_OFFS +
  788. (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs)));
  789. } else if (dimm_info[dimm_cnt].sdram_capacity > 0x3) {
  790. reg |= ((dimm_info[dimm_cnt].sdram_capacity & 0x3) <<
  791. (REG_SDRAM_ADDRESS_SIZE_OFFS +
  792. (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs)));
  793. reg |= ((dimm_info[dimm_cnt].sdram_capacity & 0x4) <<
  794. (REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS + cs));
  795. }
  796. }
  797. }
  798. /* SDRAM device structure */
  799. cs_count = 0;
  800. dimm_cnt = 0;
  801. for (cs = 0; cs < MAX_CS; cs++) {
  802. if (cs_ena & (1 << cs) & DIMM_CS_BITMAP) {
  803. if (dimm_info[dimm_cnt].num_of_module_ranks == cs_count) {
  804. dimm_cnt++;
  805. cs_count = 0;
  806. }
  807. cs_count++;
  808. if (dimm_info[dimm_cnt].sdram_width == 16)
  809. reg |= (1 << (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs));
  810. }
  811. }
  812. #endif
  813. reg_write(REG_SDRAM_ADDRESS_CTRL_ADDR, reg);
  814. /*{0x00001418} - DDR SDRAM Operation Register */
  815. reg = 0xF00;
  816. for (cs = 0; cs < MAX_CS; cs++) {
  817. if (cs_ena & (1 << cs))
  818. reg &= ~(1 << (cs + REG_SDRAM_OPERATION_CS_OFFS));
  819. }
  820. reg_write(REG_SDRAM_OPERATION_ADDR, reg);
  821. /*{0x00001420} - DDR SDRAM Extended Mode Register */
  822. reg = 0x00000004;
  823. reg_write(REG_SDRAM_EXT_MODE_ADDR, reg);
  824. /*{0x00001424} - DDR Controller Control (High) Register */
  825. #if (defined(MV88F78X60) || defined(MV88F672X))
  826. reg = 0x0000D3FF;
  827. #else
  828. reg = 0x0100D1FF;
  829. #endif
  830. reg_write(REG_DDR_CONT_HIGH_ADDR, reg);
  831. /*{0x0000142C} - DDR3 Timing Register */
  832. reg = 0x014C2F38;
  833. #if defined(MV88F78X60) || defined(MV88F672X)
  834. reg = 0x1FEC2F38;
  835. #endif
  836. reg_write(0x142C, reg);
  837. /*{0x00001484} - MBus CPU Block Register */
  838. #ifdef MV88F67XX
  839. if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
  840. reg_write(REG_MBUS_CPU_BLOCK_ADDR, 0x0000E907);
  841. #endif
  842. /*
  843. * In case of mixed dimm and on-board devices setup paramters will
  844. * be taken statically
  845. */
  846. /*{0x00001494} - DDR SDRAM ODT Control (Low) Register */
  847. reg = odt_config[cs_ena];
  848. reg_write(REG_SDRAM_ODT_CTRL_LOW_ADDR, reg);
  849. /*{0x00001498} - DDR SDRAM ODT Control (High) Register */
  850. reg = 0x00000000;
  851. reg_write(REG_SDRAM_ODT_CTRL_HIGH_ADDR, reg);
  852. /*{0x0000149C} - DDR Dunit ODT Control Register */
  853. reg = cs_ena;
  854. reg_write(REG_DUNIT_ODT_CTRL_ADDR, reg);
  855. /*{0x000014A0} - DDR Dunit ODT Control Register */
  856. #if defined(MV88F672X)
  857. reg = 0x000006A9;
  858. reg_write(REG_DRAM_FIFO_CTRL_ADDR, reg);
  859. #endif
  860. /*{0x000014C0} - DRAM address and Control Driving Strenght */
  861. reg_write(REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR, 0x192435e9);
  862. /*{0x000014C4} - DRAM Data and DQS Driving Strenght */
  863. reg_write(REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR, 0xB2C35E9);
  864. #if (defined(MV88F78X60) || defined(MV88F672X))
  865. /*{0x000014CC} - DRAM Main Pads Calibration Machine Control Register */
  866. reg = reg_read(REG_DRAM_MAIN_PADS_CAL_ADDR);
  867. reg_write(REG_DRAM_MAIN_PADS_CAL_ADDR, reg | (1 << 0));
  868. #endif
  869. #if defined(MV88F672X)
  870. /* DRAM Main Pads Calibration Machine Control Register */
  871. /* 0x14CC[4:3] - CalUpdateControl = IntOnly */
  872. reg = reg_read(REG_DRAM_MAIN_PADS_CAL_ADDR);
  873. reg &= 0xFFFFFFE7;
  874. reg |= (1 << 3);
  875. reg_write(REG_DRAM_MAIN_PADS_CAL_ADDR, reg);
  876. #endif
  877. #ifdef DUNIT_SPD
  878. cs_count = 0;
  879. dimm_cnt = 0;
  880. for (cs = 0; cs < MAX_CS; cs++) {
  881. if ((1 << cs) & DIMM_CS_BITMAP) {
  882. if ((1 << cs) & cs_ena) {
  883. if (dimm_info[dimm_cnt].num_of_module_ranks ==
  884. cs_count) {
  885. dimm_cnt++;
  886. cs_count = 0;
  887. }
  888. cs_count++;
  889. reg_write(REG_CS_SIZE_SCRATCH_ADDR + (cs * 0x8),
  890. dimm_info[dimm_cnt].rank_capacity - 1);
  891. } else {
  892. reg_write(REG_CS_SIZE_SCRATCH_ADDR + (cs * 0x8), 0);
  893. }
  894. }
  895. }
  896. #endif
  897. /*{0x00020184} - Close FastPath - 2G */
  898. reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, 0);
  899. /*{0x00001538} - Read Data Sample Delays Register */
  900. reg = 0;
  901. for (cs = 0; cs < MAX_CS; cs++) {
  902. if (cs_ena & (1 << cs))
  903. reg |= (cl << (REG_READ_DATA_SAMPLE_DELAYS_OFFS * cs));
  904. }
  905. reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, reg);
  906. DEBUG_INIT_FULL_C("DDR3 - SPD-SET - Read Data Sample Delays = ", reg,
  907. 1);
  908. /*{0x0000153C} - Read Data Ready Delay Register */
  909. reg = 0;
  910. for (cs = 0; cs < MAX_CS; cs++) {
  911. if (cs_ena & (1 << cs)) {
  912. reg |= ((cl + 2) <<
  913. (REG_READ_DATA_READY_DELAYS_OFFS * cs));
  914. }
  915. }
  916. reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg);
  917. DEBUG_INIT_FULL_C("DDR3 - SPD-SET - Read Data Ready Delays = ", reg, 1);
  918. /* Set MR registers */
  919. /* MR0 */
  920. reg = 0x00000600;
  921. tmp = ddr3_cl_to_valid_cl(cl);
  922. reg |= ((tmp & 0x1) << 2);
  923. reg |= ((tmp & 0xE) << 3); /* to bit 4 */
  924. for (cs = 0; cs < MAX_CS; cs++) {
  925. if (cs_ena & (1 << cs)) {
  926. reg_write(REG_DDR3_MR0_CS_ADDR +
  927. (cs << MR_CS_ADDR_OFFS), reg);
  928. }
  929. }
  930. /* MR1 */
  931. reg = 0x00000044 & REG_DDR3_MR1_ODT_MASK;
  932. if (cs_num > 1)
  933. reg = 0x00000046 & REG_DDR3_MR1_ODT_MASK;
  934. for (cs = 0; cs < MAX_CS; cs++) {
  935. if (cs_ena & (1 << cs)) {
  936. reg |= odt_static[cs_ena][cs];
  937. reg_write(REG_DDR3_MR1_CS_ADDR +
  938. (cs << MR_CS_ADDR_OFFS), reg);
  939. }
  940. }
  941. /* MR2 */
  942. if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
  943. tmp = hclk_time / 2;
  944. else
  945. tmp = hclk_time;
  946. if (tmp >= 2500)
  947. cwl = 5; /* CWL = 5 */
  948. else if (tmp >= 1875 && tmp < 2500)
  949. cwl = 6; /* CWL = 6 */
  950. else if (tmp >= 1500 && tmp < 1875)
  951. cwl = 7; /* CWL = 7 */
  952. else if (tmp >= 1250 && tmp < 1500)
  953. cwl = 8; /* CWL = 8 */
  954. else if (tmp >= 1070 && tmp < 1250)
  955. cwl = 9; /* CWL = 9 */
  956. else if (tmp >= 935 && tmp < 1070)
  957. cwl = 10; /* CWL = 10 */
  958. else if (tmp >= 833 && tmp < 935)
  959. cwl = 11; /* CWL = 11 */
  960. else if (tmp >= 750 && tmp < 833)
  961. cwl = 12; /* CWL = 12 */
  962. else {
  963. cwl = 12; /* CWL = 12 */
  964. printf("Unsupported hclk %d MHz\n", tmp);
  965. }
  966. reg = ((cwl - 5) << REG_DDR3_MR2_CWL_OFFS);
  967. for (cs = 0; cs < MAX_CS; cs++) {
  968. if (cs_ena & (1 << cs)) {
  969. reg &= REG_DDR3_MR2_ODT_MASK;
  970. reg |= odt_dynamic[cs_ena][cs];
  971. reg_write(REG_DDR3_MR2_CS_ADDR +
  972. (cs << MR_CS_ADDR_OFFS), reg);
  973. }
  974. }
  975. /* MR3 */
  976. reg = 0x00000000;
  977. for (cs = 0; cs < MAX_CS; cs++) {
  978. if (cs_ena & (1 << cs)) {
  979. reg_write(REG_DDR3_MR3_CS_ADDR +
  980. (cs << MR_CS_ADDR_OFFS), reg);
  981. }
  982. }
  983. /* {0x00001428} - DDR ODT Timing (Low) Register */
  984. reg = 0;
  985. reg |= (((cl - cwl + 1) & 0xF) << 4);
  986. reg |= (((cl - cwl + 6) & 0xF) << 8);
  987. reg |= ((((cl - cwl + 6) >> 4) & 0x1) << 21);
  988. reg |= (((cl - 1) & 0xF) << 12);
  989. reg |= (((cl + 6) & 0x1F) << 16);
  990. reg_write(REG_ODT_TIME_LOW_ADDR, reg);
  991. /* {0x0000147C} - DDR ODT Timing (High) Register */
  992. reg = 0x00000071;
  993. reg |= ((cwl - 1) << 8);
  994. reg |= ((cwl + 5) << 12);
  995. reg_write(REG_ODT_TIME_HIGH_ADDR, reg);
  996. #ifdef DUNIT_SPD
  997. /*{0x000015E0} - DDR3 Rank Control Register */
  998. reg = cs_ena;
  999. cs_count = 0;
  1000. dimm_cnt = 0;
  1001. for (cs = 0; cs < MAX_CS; cs++) {
  1002. if (cs_ena & (1 << cs) & DIMM_CS_BITMAP) {
  1003. if (dimm_info[dimm_cnt].num_of_module_ranks == cs_count) {
  1004. dimm_cnt++;
  1005. cs_count = 0;
  1006. }
  1007. cs_count++;
  1008. if (dimm_info[dimm_cnt].addr_mirroring &&
  1009. (cs == 1 || cs == 3) &&
  1010. (sum_info.type_info != SPD_MODULE_TYPE_RDIMM)) {
  1011. reg |= (1 << (REG_DDR3_RANK_CTRL_MIRROR_OFFS + cs));
  1012. DEBUG_INIT_FULL_C("DDR3 - SPD-SET - Setting Address Mirroring for CS = ",
  1013. cs, 1);
  1014. }
  1015. }
  1016. }
  1017. reg_write(REG_DDR3_RANK_CTRL_ADDR, reg);
  1018. #endif
  1019. /*{0xD00015E4} - ZQDS Configuration Register */
  1020. reg = 0x00203c18;
  1021. reg_write(REG_ZQC_CONF_ADDR, reg);
  1022. /* {0x00015EC} - DDR PHY */
  1023. #if defined(MV88F78X60)
  1024. reg = 0xF800AAA5;
  1025. if (mv_ctrl_rev_get() == MV_78XX0_B0_REV)
  1026. reg = 0xF800A225;
  1027. #else
  1028. reg = 0xDE000025;
  1029. #if defined(MV88F672X)
  1030. reg = 0xF800A225;
  1031. #endif
  1032. #endif
  1033. reg_write(REG_DRAM_PHY_CONFIG_ADDR, reg);
  1034. #if (defined(MV88F78X60) || defined(MV88F672X))
  1035. /* Registered DIMM support - supported only in AXP A0 devices */
  1036. /* Currently supported for SPD detection only */
  1037. /*
  1038. * Flow is according to the Registered DIMM chapter in the
  1039. * Functional Spec
  1040. */
  1041. if (sum_info.type_info == SPD_MODULE_TYPE_RDIMM) {
  1042. DEBUG_INIT_S("DDR3 Training Sequence - Registered DIMM detected\n");
  1043. /* Set commands parity completion */
  1044. reg = reg_read(REG_REGISTERED_DRAM_CTRL_ADDR);
  1045. reg &= ~REG_REGISTERED_DRAM_CTRL_PARITY_MASK;
  1046. reg |= 0x8;
  1047. reg_write(REG_REGISTERED_DRAM_CTRL_ADDR, reg);
  1048. /* De-assert M_RESETn and assert M_CKE */
  1049. reg_write(REG_SDRAM_INIT_CTRL_ADDR,
  1050. 1 << REG_SDRAM_INIT_CKE_ASSERT_OFFS);
  1051. do {
  1052. reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &
  1053. (1 << REG_SDRAM_INIT_CKE_ASSERT_OFFS);
  1054. } while (reg);
  1055. for (rc = 0; rc < SPD_RDIMM_RC_NUM; rc++) {
  1056. if (rc != 6 && rc != 7) {
  1057. /* Set CWA Command */
  1058. reg = (REG_SDRAM_OPERATION_CMD_CWA &
  1059. ~(0xF << REG_SDRAM_OPERATION_CS_OFFS));
  1060. reg |= ((dimm_info[0].dimm_rc[rc] &
  1061. REG_SDRAM_OPERATION_CWA_DATA_MASK) <<
  1062. REG_SDRAM_OPERATION_CWA_DATA_OFFS);
  1063. reg |= rc << REG_SDRAM_OPERATION_CWA_RC_OFFS;
  1064. /* Configure - Set Delay - tSTAB/tMRD */
  1065. if (rc == 2 || rc == 10)
  1066. reg |= (0x1 << REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS);
  1067. /* 0x1418 - SDRAM Operation Register */
  1068. reg_write(REG_SDRAM_OPERATION_ADDR, reg);
  1069. /*
  1070. * Poll the "cmd" field in the SDRAM OP
  1071. * register for 0x0
  1072. */
  1073. do {
  1074. reg = reg_read(REG_SDRAM_OPERATION_ADDR) &
  1075. (REG_SDRAM_OPERATION_CMD_MASK);
  1076. } while (reg);
  1077. }
  1078. }
  1079. }
  1080. #endif
  1081. return MV_OK;
  1082. }
  1083. /*
  1084. * Name: ddr3_div - this function divides integers
  1085. * Desc:
  1086. * Args: val - the value
  1087. * divider - the divider
  1088. * sub - substruction value
  1089. * Notes:
  1090. * Returns: required value
  1091. */
  1092. u32 ddr3_div(u32 val, u32 divider, u32 sub)
  1093. {
  1094. return val / divider + (val % divider > 0 ? 1 : 0) - sub;
  1095. }
  1096. /*
  1097. * Name: ddr3_get_max_val
  1098. * Desc:
  1099. * Args:
  1100. * Notes:
  1101. * Returns:
  1102. */
  1103. u32 ddr3_get_max_val(u32 spd_val, u32 dimm_num, u32 static_val)
  1104. {
  1105. #ifdef DUNIT_STATIC
  1106. if (dimm_num > 0) {
  1107. if (spd_val >= static_val)
  1108. return spd_val;
  1109. else
  1110. return static_val;
  1111. } else {
  1112. return static_val;
  1113. }
  1114. #else
  1115. return spd_val;
  1116. #endif
  1117. }
  1118. /*
  1119. * Name: ddr3_get_min_val
  1120. * Desc:
  1121. * Args:
  1122. * Notes:
  1123. * Returns:
  1124. */
  1125. u32 ddr3_get_min_val(u32 spd_val, u32 dimm_num, u32 static_val)
  1126. {
  1127. #ifdef DUNIT_STATIC
  1128. if (dimm_num > 0) {
  1129. if (spd_val <= static_val)
  1130. return spd_val;
  1131. else
  1132. return static_val;
  1133. } else
  1134. return static_val;
  1135. #else
  1136. return spd_val;
  1137. #endif
  1138. }
  1139. #endif