ddr3_sdram.c 17 KB

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  1. /*
  2. * Copyright (C) Marvell International Ltd. and its affiliates
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <spl.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/soc.h>
  12. #include "ddr3_hw_training.h"
  13. #include "xor.h"
  14. #include "xor_regs.h"
  15. static void ddr3_flush_l1_line(u32 line);
  16. extern u32 pbs_pattern[2][LEN_16BIT_PBS_PATTERN];
  17. extern u32 pbs_pattern_32b[2][LEN_PBS_PATTERN];
  18. #if defined(MV88F78X60)
  19. extern u32 pbs_pattern_64b[2][LEN_PBS_PATTERN];
  20. #endif
  21. extern u32 pbs_dq_mapping[PUP_NUM_64BIT][DQ_NUM];
  22. #if defined(MV88F78X60) || defined(MV88F672X)
  23. /* PBS locked dq (per pup) */
  24. u32 pbs_locked_dq[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
  25. u32 pbs_locked_dm[MAX_PUP_NUM] = { 0 };
  26. u32 pbs_locked_value[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
  27. int per_bit_data[MAX_PUP_NUM][DQ_NUM];
  28. #endif
  29. static u32 sdram_data[LEN_KILLER_PATTERN] __aligned(32) = { 0 };
  30. static struct crc_dma_desc dma_desc __aligned(32) = { 0 };
  31. #define XOR_TIMEOUT 0x8000000
  32. struct xor_channel_t {
  33. struct crc_dma_desc *desc;
  34. unsigned long desc_phys_addr;
  35. };
  36. #define XOR_CAUSE_DONE_MASK(chan) ((0x1 | 0x2) << (chan * 16))
  37. void xor_waiton_eng(int chan)
  38. {
  39. int timeout;
  40. timeout = 0;
  41. while (!(reg_read(XOR_CAUSE_REG(XOR_UNIT(chan))) &
  42. XOR_CAUSE_DONE_MASK(XOR_CHAN(chan)))) {
  43. if (timeout > XOR_TIMEOUT)
  44. goto timeout;
  45. timeout++;
  46. }
  47. timeout = 0;
  48. while (mv_xor_state_get(chan) != MV_IDLE) {
  49. if (timeout > XOR_TIMEOUT)
  50. goto timeout;
  51. timeout++;
  52. }
  53. /* Clear int */
  54. reg_write(XOR_CAUSE_REG(XOR_UNIT(chan)),
  55. ~(XOR_CAUSE_DONE_MASK(XOR_CHAN(chan))));
  56. timeout:
  57. return;
  58. }
  59. static int special_compare_pattern(u32 uj)
  60. {
  61. if ((uj == 30) || (uj == 31) || (uj == 61) || (uj == 62) ||
  62. (uj == 93) || (uj == 94) || (uj == 126) || (uj == 127))
  63. return 1;
  64. return 0;
  65. }
  66. /*
  67. * Compare code extracted as its used by multiple functions. This
  68. * reduces code-size and makes it easier to maintain it. Additionally
  69. * the code is not indented that much and therefore easier to read.
  70. */
  71. static void compare_pattern_v1(u32 uj, u32 *pup, u32 *pattern,
  72. u32 pup_groups, int debug_dqs)
  73. {
  74. u32 val;
  75. u32 uk;
  76. u32 var1;
  77. u32 var2;
  78. __maybe_unused u32 dq;
  79. if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0xFF)) {
  80. for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
  81. val = CMP_BYTE_SHIFT * uk;
  82. var1 = ((sdram_data[uj] >> val) & CMP_BYTE_MASK);
  83. var2 = ((pattern[uj] >> val) & CMP_BYTE_MASK);
  84. if (var1 != var2) {
  85. *pup |= (1 << (uk + (PUP_NUM_32BIT *
  86. (uj % pup_groups))));
  87. #ifdef MV_DEBUG_DQS
  88. if (!debug_dqs)
  89. continue;
  90. for (dq = 0; dq < DQ_NUM; dq++) {
  91. val = uk + (PUP_NUM_32BIT *
  92. (uj % pup_groups));
  93. if (((var1 >> dq) & 0x1) !=
  94. ((var2 >> dq) & 0x1))
  95. per_bit_data[val][dq] = 1;
  96. else
  97. per_bit_data[val][dq] = 0;
  98. }
  99. #endif
  100. }
  101. }
  102. }
  103. }
  104. static void compare_pattern_v2(u32 uj, u32 *pup, u32 *pattern)
  105. {
  106. u32 val;
  107. u32 uk;
  108. u32 var1;
  109. u32 var2;
  110. if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0x3)) {
  111. /* Found error */
  112. for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
  113. val = CMP_BYTE_SHIFT * uk;
  114. var1 = (sdram_data[uj] >> val) & CMP_BYTE_MASK;
  115. var2 = (pattern[uj] >> val) & CMP_BYTE_MASK;
  116. if (var1 != var2)
  117. *pup |= (1 << (uk % PUP_NUM_16BIT));
  118. }
  119. }
  120. }
  121. /*
  122. * Name: ddr3_sdram_compare
  123. * Desc: Execute compare per PUP
  124. * Args: unlock_pup Bit array of the unlock pups
  125. * new_locked_pup Output bit array of the pups with failed compare
  126. * pattern Pattern to compare
  127. * pattern_len Length of pattern (in bytes)
  128. * sdram_offset offset address to the SDRAM
  129. * write write to the SDRAM before read
  130. * mask compare pattern with mask;
  131. * mask_pattern Mask to compare pattern
  132. *
  133. * Notes:
  134. * Returns: MV_OK if success, other error code if fail.
  135. */
  136. int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
  137. u32 *new_locked_pup, u32 *pattern,
  138. u32 pattern_len, u32 sdram_offset, int write,
  139. int mask, u32 *mask_pattern,
  140. int special_compare)
  141. {
  142. u32 uj;
  143. __maybe_unused u32 pup_groups;
  144. __maybe_unused u32 dq;
  145. #if !defined(MV88F67XX)
  146. if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
  147. pup_groups = 2;
  148. else
  149. pup_groups = 1;
  150. #endif
  151. ddr3_reset_phy_read_fifo();
  152. /* Check if need to write to sdram before read */
  153. if (write == 1)
  154. ddr3_dram_sram_burst((u32)pattern, sdram_offset, pattern_len);
  155. ddr3_dram_sram_burst(sdram_offset, (u32)sdram_data, pattern_len);
  156. /* Compare read result to write */
  157. for (uj = 0; uj < pattern_len; uj++) {
  158. if (special_compare && special_compare_pattern(uj))
  159. continue;
  160. #if defined(MV88F78X60) || defined(MV88F672X)
  161. compare_pattern_v1(uj, new_locked_pup, pattern, pup_groups, 1);
  162. #elif defined(MV88F67XX)
  163. compare_pattern_v2(uj, new_locked_pup, pattern);
  164. #endif
  165. }
  166. return MV_OK;
  167. }
  168. #if defined(MV88F78X60) || defined(MV88F672X)
  169. /*
  170. * Name: ddr3_sdram_dm_compare
  171. * Desc: Execute compare per PUP
  172. * Args: unlock_pup Bit array of the unlock pups
  173. * new_locked_pup Output bit array of the pups with failed compare
  174. * pattern Pattern to compare
  175. * pattern_len Length of pattern (in bytes)
  176. * sdram_offset offset address to the SDRAM
  177. * write write to the SDRAM before read
  178. * mask compare pattern with mask;
  179. * mask_pattern Mask to compare pattern
  180. *
  181. * Notes:
  182. * Returns: MV_OK if success, other error code if fail.
  183. */
  184. int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
  185. u32 *new_locked_pup, u32 *pattern,
  186. u32 sdram_offset)
  187. {
  188. u32 uj, uk, var1, var2, pup_groups;
  189. u32 val;
  190. u32 pup = 0;
  191. if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
  192. pup_groups = 2;
  193. else
  194. pup_groups = 1;
  195. ddr3_dram_sram_burst((u32)pattern, SDRAM_PBS_TX_OFFS,
  196. LEN_PBS_PATTERN);
  197. ddr3_dram_sram_burst(SDRAM_PBS_TX_OFFS, (u32)sdram_data,
  198. LEN_PBS_PATTERN);
  199. /* Validate the correctness of the results */
  200. for (uj = 0; uj < LEN_PBS_PATTERN; uj++)
  201. compare_pattern_v1(uj, &pup, pattern, pup_groups, 0);
  202. /* Test the DM Signals */
  203. *(u32 *)(SDRAM_PBS_TX_OFFS + 0x10) = 0x12345678;
  204. *(u32 *)(SDRAM_PBS_TX_OFFS + 0x14) = 0x12345678;
  205. sdram_data[0] = *(u32 *)(SDRAM_PBS_TX_OFFS + 0x10);
  206. sdram_data[1] = *(u32 *)(SDRAM_PBS_TX_OFFS + 0x14);
  207. for (uj = 0; uj < 2; uj++) {
  208. if (((sdram_data[uj]) != (pattern[uj])) &&
  209. (*new_locked_pup != 0xFF)) {
  210. for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
  211. val = CMP_BYTE_SHIFT * uk;
  212. var1 = ((sdram_data[uj] >> val) & CMP_BYTE_MASK);
  213. var2 = ((pattern[uj] >> val) & CMP_BYTE_MASK);
  214. if (var1 != var2) {
  215. *new_locked_pup |= (1 << (uk +
  216. (PUP_NUM_32BIT * (uj % pup_groups))));
  217. *new_locked_pup |= pup;
  218. }
  219. }
  220. }
  221. }
  222. return MV_OK;
  223. }
  224. /*
  225. * Name: ddr3_sdram_pbs_compare
  226. * Desc: Execute SRAM compare per PUP and DQ.
  227. * Args: pup_locked bit array of locked pups
  228. * is_tx Indicate whether Rx or Tx
  229. * pbs_pattern_idx Index of PBS pattern
  230. * pbs_curr_val The PBS value
  231. * pbs_lock_val The value to set to locked PBS
  232. * skew_array Global array to update with the compare results
  233. * ai_unlock_pup_dq_array bit array of the locked / unlocked pups per dq.
  234. * Notes:
  235. * Returns: MV_OK if success, other error code if fail.
  236. */
  237. int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked,
  238. int is_tx, u32 pbs_pattern_idx,
  239. u32 pbs_curr_val, u32 pbs_lock_val,
  240. u32 *skew_array, u8 *unlock_pup_dq_array,
  241. u32 ecc)
  242. {
  243. /* bit array failed dq per pup for current compare */
  244. u32 pbs_write_pup[DQ_NUM] = { 0 };
  245. u32 update_pup; /* pup as HW convention */
  246. u32 max_pup; /* maximal pup index */
  247. u32 pup_addr;
  248. u32 ui, dq, pup;
  249. int var1, var2;
  250. u32 sdram_offset, pup_groups, tmp_pup;
  251. u32 *pattern_ptr;
  252. u32 val;
  253. /* Choose pattern */
  254. switch (dram_info->ddr_width) {
  255. #if defined(MV88F672X)
  256. case 16:
  257. pattern_ptr = (u32 *)&pbs_pattern[pbs_pattern_idx];
  258. break;
  259. #endif
  260. case 32:
  261. pattern_ptr = (u32 *)&pbs_pattern_32b[pbs_pattern_idx];
  262. break;
  263. #if defined(MV88F78X60)
  264. case 64:
  265. pattern_ptr = (u32 *)&pbs_pattern_64b[pbs_pattern_idx];
  266. break;
  267. #endif
  268. default:
  269. return MV_FAIL;
  270. }
  271. max_pup = dram_info->num_of_std_pups;
  272. sdram_offset = SDRAM_PBS_I_OFFS + pbs_pattern_idx * SDRAM_PBS_NEXT_OFFS;
  273. if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
  274. pup_groups = 2;
  275. else
  276. pup_groups = 1;
  277. ddr3_reset_phy_read_fifo();
  278. /* Check if need to write to sdram before read */
  279. if (is_tx == 1) {
  280. ddr3_dram_sram_burst((u32)pattern_ptr, sdram_offset,
  281. LEN_PBS_PATTERN);
  282. }
  283. ddr3_dram_sram_read(sdram_offset, (u32)sdram_data, LEN_PBS_PATTERN);
  284. /* Compare read result to write */
  285. for (ui = 0; ui < LEN_PBS_PATTERN; ui++) {
  286. if ((sdram_data[ui]) != (pattern_ptr[ui])) {
  287. /* found error */
  288. /* error in low pup group */
  289. for (pup = 0; pup < PUP_NUM_32BIT; pup++) {
  290. val = CMP_BYTE_SHIFT * pup;
  291. var1 = ((sdram_data[ui] >> val) &
  292. CMP_BYTE_MASK);
  293. var2 = ((pattern_ptr[ui] >> val) &
  294. CMP_BYTE_MASK);
  295. if (var1 != var2) {
  296. if (dram_info->ddr_width > 16) {
  297. tmp_pup = (pup + PUP_NUM_32BIT *
  298. (ui % pup_groups));
  299. } else {
  300. tmp_pup = (pup % PUP_NUM_16BIT);
  301. }
  302. update_pup = (1 << tmp_pup);
  303. if (ecc && (update_pup != 0x1))
  304. continue;
  305. /*
  306. * Pup is failed - Go over all DQs and
  307. * look for failures
  308. */
  309. for (dq = 0; dq < DQ_NUM; dq++) {
  310. val = tmp_pup * (1 - ecc) +
  311. ecc * ECC_PUP;
  312. if (((var1 >> dq) & 0x1) !=
  313. ((var2 >> dq) & 0x1)) {
  314. if (pbs_locked_dq[val][dq] == 1 &&
  315. pbs_locked_value[val][dq] != pbs_curr_val)
  316. continue;
  317. /*
  318. * Activate write to
  319. * update PBS to
  320. * pbs_lock_val
  321. */
  322. pbs_write_pup[dq] |=
  323. update_pup;
  324. /*
  325. * Update the
  326. * unlock_pup_dq_array
  327. */
  328. unlock_pup_dq_array[dq] &=
  329. ~update_pup;
  330. /*
  331. * Lock PBS value for
  332. * failed bits in
  333. * compare operation
  334. */
  335. skew_array[tmp_pup * DQ_NUM + dq] =
  336. pbs_curr_val;
  337. }
  338. }
  339. }
  340. }
  341. }
  342. }
  343. pup_addr = (is_tx == 1) ? PUP_PBS_TX : PUP_PBS_RX;
  344. /* Set last failed bits PBS to min / max pbs value */
  345. for (dq = 0; dq < DQ_NUM; dq++) {
  346. for (pup = 0; pup < max_pup; pup++) {
  347. if (pbs_write_pup[dq] & (1 << pup)) {
  348. val = pup * (1 - ecc) + ecc * ECC_PUP;
  349. if (pbs_locked_dq[val][dq] == 1 &&
  350. pbs_locked_value[val][dq] != pbs_curr_val)
  351. continue;
  352. /* Mark the dq as locked */
  353. pbs_locked_dq[val][dq] = 1;
  354. pbs_locked_value[val][dq] = pbs_curr_val;
  355. ddr3_write_pup_reg(pup_addr +
  356. pbs_dq_mapping[val][dq],
  357. CS0, val, 0, pbs_lock_val);
  358. }
  359. }
  360. }
  361. return MV_OK;
  362. }
  363. #endif
  364. /*
  365. * Name: ddr3_sdram_direct_compare
  366. * Desc: Execute compare per PUP without DMA (no burst mode)
  367. * Args: unlock_pup Bit array of the unlock pups
  368. * new_locked_pup Output bit array of the pups with failed compare
  369. * pattern Pattern to compare
  370. * pattern_len Length of pattern (in bytes)
  371. * sdram_offset offset address to the SDRAM
  372. * write write to the SDRAM before read
  373. * mask compare pattern with mask;
  374. * auiMaskPatter Mask to compare pattern
  375. *
  376. * Notes:
  377. * Returns: MV_OK if success, other error code if fail.
  378. */
  379. int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
  380. u32 *new_locked_pup, u32 *pattern,
  381. u32 pattern_len, u32 sdram_offset,
  382. int write, int mask, u32 *mask_pattern)
  383. {
  384. u32 uj, uk, pup_groups;
  385. u32 *sdram_addr; /* used to read from SDRAM */
  386. sdram_addr = (u32 *)sdram_offset;
  387. if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
  388. pup_groups = 2;
  389. else
  390. pup_groups = 1;
  391. /* Check if need to write before read */
  392. if (write == 1) {
  393. for (uk = 0; uk < pattern_len; uk++) {
  394. *sdram_addr = pattern[uk];
  395. sdram_addr++;
  396. }
  397. }
  398. sdram_addr = (u32 *)sdram_offset;
  399. for (uk = 0; uk < pattern_len; uk++) {
  400. sdram_data[uk] = *sdram_addr;
  401. sdram_addr++;
  402. }
  403. /* Compare read result to write */
  404. for (uj = 0; uj < pattern_len; uj++) {
  405. if (dram_info->ddr_width > 16) {
  406. compare_pattern_v1(uj, new_locked_pup, pattern,
  407. pup_groups, 0);
  408. } else {
  409. compare_pattern_v2(uj, new_locked_pup, pattern);
  410. }
  411. }
  412. return MV_OK;
  413. }
  414. /*
  415. * Name: ddr3_dram_sram_burst
  416. * Desc: Read from the SDRAM in burst of 64 bytes
  417. * Args: src
  418. * dst
  419. * Notes: Using the XOR mechanism
  420. * Returns: MV_OK if success, other error code if fail.
  421. */
  422. int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len)
  423. {
  424. u32 chan, byte_count, cs_num, byte;
  425. struct xor_channel_t channel;
  426. chan = 0;
  427. byte_count = len * 4;
  428. /* Wait for previous transfer completion */
  429. while (mv_xor_state_get(chan) != MV_IDLE)
  430. ;
  431. /* Build the channel descriptor */
  432. channel.desc = &dma_desc;
  433. /* Enable Address Override and set correct src and dst */
  434. if (src < SRAM_BASE) {
  435. /* src is DRAM CS, dst is SRAM */
  436. cs_num = (src / (1 + SDRAM_CS_SIZE));
  437. reg_write(XOR_ADDR_OVRD_REG(0, 0),
  438. ((cs_num << 1) | (1 << 0)));
  439. channel.desc->src_addr0 = (src % (1 + SDRAM_CS_SIZE));
  440. channel.desc->dst_addr = dst;
  441. } else {
  442. /* src is SRAM, dst is DRAM CS */
  443. cs_num = (dst / (1 + SDRAM_CS_SIZE));
  444. reg_write(XOR_ADDR_OVRD_REG(0, 0),
  445. ((cs_num << 25) | (1 << 24)));
  446. channel.desc->src_addr0 = (src);
  447. channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE));
  448. channel.desc->src_addr0 = src;
  449. channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE));
  450. }
  451. channel.desc->src_addr1 = 0;
  452. channel.desc->byte_cnt = byte_count;
  453. channel.desc->next_desc_ptr = 0;
  454. channel.desc->status = 1 << 31;
  455. channel.desc->desc_cmd = 0x0;
  456. channel.desc_phys_addr = (unsigned long)&dma_desc;
  457. ddr3_flush_l1_line((u32)&dma_desc);
  458. /* Issue the transfer */
  459. if (mv_xor_transfer(chan, MV_DMA, channel.desc_phys_addr) != MV_OK)
  460. return MV_FAIL;
  461. /* Wait for completion */
  462. xor_waiton_eng(chan);
  463. if (dst > SRAM_BASE) {
  464. for (byte = 0; byte < byte_count; byte += 0x20)
  465. cache_inv(dst + byte);
  466. }
  467. return MV_OK;
  468. }
  469. /*
  470. * Name: ddr3_flush_l1_line
  471. * Desc:
  472. * Args:
  473. * Notes:
  474. * Returns: MV_OK if success, other error code if fail.
  475. */
  476. static void ddr3_flush_l1_line(u32 line)
  477. {
  478. u32 reg;
  479. #if defined(MV88F672X)
  480. reg = 1;
  481. #else
  482. reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR) &
  483. (1 << REG_SAMPLE_RESET_CPU_ARCH_OFFS);
  484. #ifdef MV88F67XX
  485. reg = ~reg & (1 << REG_SAMPLE_RESET_CPU_ARCH_OFFS);
  486. #endif
  487. #endif
  488. if (reg) {
  489. /* V7 Arch mode */
  490. flush_l1_v7(line);
  491. flush_l1_v7(line + CACHE_LINE_SIZE);
  492. } else {
  493. /* V6 Arch mode */
  494. flush_l1_v6(line);
  495. flush_l1_v6(line + CACHE_LINE_SIZE);
  496. }
  497. }
  498. int ddr3_dram_sram_read(u32 src, u32 dst, u32 len)
  499. {
  500. u32 ui;
  501. u32 *dst_ptr, *src_ptr;
  502. dst_ptr = (u32 *)dst;
  503. src_ptr = (u32 *)src;
  504. for (ui = 0; ui < len; ui++) {
  505. *dst_ptr = *src_ptr;
  506. dst_ptr++;
  507. src_ptr++;
  508. }
  509. return MV_OK;
  510. }
  511. int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
  512. u32 *new_locked_pup, u32 *pattern,
  513. u32 pattern_len, u32 sdram_offset, int write,
  514. int mask, u32 *mask_pattern,
  515. int special_compare)
  516. {
  517. u32 uj, pup_groups;
  518. if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
  519. pup_groups = 2;
  520. else
  521. pup_groups = 1;
  522. ddr3_reset_phy_read_fifo();
  523. /* Check if need to write to sdram before read */
  524. if (write == 1)
  525. ddr3_dram_sram_burst((u32)pattern, sdram_offset, pattern_len);
  526. ddr3_dram_sram_burst(sdram_offset, (u32)sdram_data, pattern_len);
  527. /* Compare read result to write */
  528. for (uj = 0; uj < pattern_len; uj++) {
  529. if (special_compare && special_compare_pattern(uj))
  530. continue;
  531. if (dram_info->ddr_width > 16) {
  532. compare_pattern_v1(uj, new_locked_pup, pattern,
  533. pup_groups, 1);
  534. } else {
  535. compare_pattern_v2(uj, new_locked_pup, pattern);
  536. }
  537. }
  538. return MV_OK;
  539. }
  540. void ddr3_reset_phy_read_fifo(void)
  541. {
  542. u32 reg;
  543. /* reset read FIFO */
  544. reg = reg_read(REG_DRAM_TRAINING_ADDR);
  545. /* Start Auto Read Leveling procedure */
  546. reg |= (1 << REG_DRAM_TRAINING_RL_OFFS);
  547. /* 0x15B0 - Training Register */
  548. reg_write(REG_DRAM_TRAINING_ADDR, reg);
  549. reg = reg_read(REG_DRAM_TRAINING_2_ADDR);
  550. reg |= ((1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS) +
  551. (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS));
  552. /* [0] = 1 - Enable SW override, [4] = 1 - FIFO reset */
  553. /* 0x15B8 - Training SW 2 Register */
  554. reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
  555. do {
  556. reg = reg_read(REG_DRAM_TRAINING_2_ADDR) &
  557. (1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS);
  558. } while (reg); /* Wait for '0' */
  559. reg = reg_read(REG_DRAM_TRAINING_ADDR);
  560. /* Clear Auto Read Leveling procedure */
  561. reg &= ~(1 << REG_DRAM_TRAINING_RL_OFFS);
  562. /* 0x15B0 - Training Register */
  563. reg_write(REG_DRAM_TRAINING_ADDR, reg);
  564. }