ddr3_init.h 3.7 KB

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  1. /*
  2. * Copyright (C) Marvell International Ltd. and its affiliates
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #ifndef __DDR3_INIT_H
  7. #define __DDR3_INIT_H
  8. /*
  9. * Debug
  10. */
  11. /*
  12. * MV_DEBUG_INIT need to be defines, otherwise the output of the
  13. * DDR2 training code is not complete and misleading
  14. */
  15. #define MV_DEBUG_INIT
  16. #ifdef MV_DEBUG_INIT
  17. #define DEBUG_INIT_S(s) puts(s)
  18. #define DEBUG_INIT_D(d, l) printf("%x", d)
  19. #define DEBUG_INIT_D_10(d, l) printf("%d", d)
  20. #else
  21. #define DEBUG_INIT_S(s)
  22. #define DEBUG_INIT_D(d, l)
  23. #define DEBUG_INIT_D_10(d, l)
  24. #endif
  25. #ifdef MV_DEBUG_INIT_FULL
  26. #define DEBUG_INIT_FULL_S(s) puts(s)
  27. #define DEBUG_INIT_FULL_D(d, l) printf("%x", d)
  28. #define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d)
  29. #define DEBUG_WR_REG(reg, val) \
  30. { DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
  31. DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
  32. #define DEBUG_RD_REG(reg, val) \
  33. { DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
  34. DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
  35. #else
  36. #define DEBUG_INIT_FULL_S(s)
  37. #define DEBUG_INIT_FULL_D(d, l)
  38. #define DEBUG_INIT_FULL_D_10(d, l)
  39. #define DEBUG_WR_REG(reg, val)
  40. #define DEBUG_RD_REG(reg, val)
  41. #endif
  42. #define DEBUG_INIT_FULL_C(s, d, l) \
  43. { DEBUG_INIT_FULL_S(s); DEBUG_INIT_FULL_D(d, l); DEBUG_INIT_FULL_S("\n"); }
  44. #define DEBUG_INIT_C(s, d, l) \
  45. { DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
  46. #define MV_MBUS_REGS_OFFSET (0x20000)
  47. #include "ddr3_hw_training.h"
  48. #define MAX_DIMM_NUM 2
  49. #define SPD_SIZE 128
  50. #ifdef MV88F78X60
  51. #include "ddr3_axp.h"
  52. #elif defined(MV88F67XX)
  53. #include "ddr3_a370.h"
  54. #elif defined(MV88F672X)
  55. #include "ddr3_a375.h"
  56. #endif
  57. /* DRR training Error codes */
  58. /* Stage 0 errors */
  59. #define MV_DDR3_TRAINING_ERR_BAD_SAR 0xDD300001
  60. /* Stage 1 errors */
  61. #define MV_DDR3_TRAINING_ERR_TWSI_FAIL 0xDD301001
  62. #define MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH 0xDD301001
  63. #define MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE 0xDD301003
  64. #define MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH 0xDD301004
  65. #define MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP 0xDD301005
  66. #define MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT 0xDD301006
  67. #define MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT 0xDD301007
  68. #define MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP 0xDD301008
  69. /* Stage 2 errors */
  70. #define MV_DDR3_TRAINING_ERR_HW_FAIL_BASE 0xDD302000
  71. typedef enum config_type {
  72. CONFIG_ECC,
  73. CONFIG_MULTI_CS,
  74. CONFIG_BUS_WIDTH
  75. } MV_CONFIG_TYPE;
  76. enum log_level {
  77. MV_LOG_LEVEL_0,
  78. MV_LOG_LEVEL_1,
  79. MV_LOG_LEVEL_2,
  80. MV_LOG_LEVEL_3
  81. };
  82. int ddr3_hw_training(u32 target_freq, u32 ddr_width,
  83. int xor_bypass, u32 scrub_offs, u32 scrub_size,
  84. int dqs_clk_aligned, int debug_mode, int reg_dimm_skip_wl);
  85. void ddr3_print_version(void);
  86. void fix_pll_val(u8 target_fab);
  87. u8 ddr3_get_eprom_fabric(void);
  88. u32 ddr3_get_fab_opt(void);
  89. u32 ddr3_get_cpu_freq(void);
  90. u32 ddr3_get_vco_freq(void);
  91. int ddr3_check_config(u32 addr, MV_CONFIG_TYPE config_type);
  92. u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2,
  93. u32 mask2);
  94. u32 ddr3_cl_to_valid_cl(u32 cl);
  95. u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl);
  96. u32 ddr3_get_cs_num_from_reg(void);
  97. u32 ddr3_get_cs_ena_from_reg(void);
  98. u8 mv_ctrl_rev_get(void);
  99. u32 ddr3_get_log_level(void);
  100. /* SPD */
  101. int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width);
  102. /*
  103. * Accessor functions for the registers
  104. */
  105. static inline void reg_write(u32 addr, u32 val)
  106. {
  107. writel(val, INTER_REGS_BASE + addr);
  108. }
  109. static inline u32 reg_read(u32 addr)
  110. {
  111. return readl(INTER_REGS_BASE + addr);
  112. }
  113. static inline void reg_bit_set(u32 addr, u32 mask)
  114. {
  115. setbits_le32(INTER_REGS_BASE + addr, mask);
  116. }
  117. static inline void reg_bit_clr(u32 addr, u32 mask)
  118. {
  119. clrbits_le32(INTER_REGS_BASE + addr, mask);
  120. }
  121. #endif /* __DDR3_INIT_H */