ddr3_hw_training.h 14 KB

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  1. /*
  2. * Copyright (C) Marvell International Ltd. and its affiliates
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #ifndef __DDR3_TRAINING_H
  7. #define __DDR3_TRAINING_H
  8. #include "ddr3_init.h"
  9. #ifdef MV88F78X60
  10. #include "ddr3_axp.h"
  11. #elif defined(MV88F67XX)
  12. #include "ddr3_a370.h"
  13. #elif defined(MV88F672X)
  14. #include "ddr3_a375.h"
  15. #endif
  16. /* The following is a list of Marvell status */
  17. #define MV_ERROR (-1)
  18. #define MV_OK (0x00) /* Operation succeeded */
  19. #define MV_FAIL (0x01) /* Operation failed */
  20. #define MV_BAD_VALUE (0x02) /* Illegal value (general) */
  21. #define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
  22. #define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
  23. #define MV_BAD_PTR (0x05) /* Illegal pointer value */
  24. #define MV_BAD_SIZE (0x06) /* Illegal size */
  25. #define MV_BAD_STATE (0x07) /* Illegal state of state machine */
  26. #define MV_SET_ERROR (0x08) /* Set operation failed */
  27. #define MV_GET_ERROR (0x09) /* Get operation failed */
  28. #define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */
  29. #define MV_NOT_FOUND (0x0B) /* Item not found */
  30. #define MV_NO_MORE (0x0C) /* No more items found */
  31. #define MV_NO_SUCH (0x0D) /* No such item */
  32. #define MV_TIMEOUT (0x0E) /* Time Out */
  33. #define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */
  34. #define MV_NOT_SUPPORTED (0x10) /* This request is not support */
  35. #define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
  36. #define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
  37. #define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
  38. #define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
  39. #define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
  40. #define MV_INIT_ERROR (0x16) /* Error occurred while INIT process */
  41. #define MV_HW_ERROR (0x17) /* Hardware error */
  42. #define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
  43. #define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
  44. #define MV_NOT_READY (0x1A) /* The other side is not ready yet */
  45. #define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */
  46. #define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */
  47. #define MV_NOT_STARTED (0x1D) /* Not started yet */
  48. #define MV_BUSY (0x1E) /* Item is busy. */
  49. #define MV_TERMINATE (0x1F) /* Item terminates it's work. */
  50. #define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
  51. #define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
  52. #define MV_WRITE_PROTECT (0x22) /* Write protected */
  53. #define MV_INVALID (int)(-1)
  54. /*
  55. * Debug (Enable/Disable modules) and Error report
  56. */
  57. #ifdef BASIC_DEBUG
  58. #define MV_DEBUG_WL
  59. #define MV_DEBUG_RL
  60. #define MV_DEBUG_DQS_RESULTS
  61. #endif
  62. #ifdef FULL_DEBUG
  63. #define MV_DEBUG_WL
  64. #define MV_DEBUG_RL
  65. #define MV_DEBUG_DQS
  66. #define MV_DEBUG_PBS
  67. #define MV_DEBUG_DFS
  68. #define MV_DEBUG_MAIN_FULL
  69. #define MV_DEBUG_DFS_FULL
  70. #define MV_DEBUG_DQS_FULL
  71. #define MV_DEBUG_RL_FULL
  72. #define MV_DEBUG_WL_FULL
  73. #endif
  74. /*
  75. * General Consts
  76. */
  77. #define SDRAM_READ_WRITE_LEN_IN_WORDS 16
  78. #define SDRAM_READ_WRITE_LEN_IN_DOUBLE_WORDS 8
  79. #define CACHE_LINE_SIZE 0x20
  80. #define SDRAM_CS_BASE 0x0
  81. #define SRAM_BASE 0x40000000
  82. #define SRAM_SIZE 0xFFF
  83. #define LEN_64BIT_STD_PATTERN 16
  84. #define LEN_64BIT_KILLER_PATTERN 128
  85. #define LEN_64BIT_SPECIAL_PATTERN 128
  86. #define LEN_64BIT_PBS_PATTERN 16
  87. #define LEN_WL_SUP_PATTERN 32
  88. #define LEN_16BIT_STD_PATTERN 4
  89. #define LEN_16BIT_KILLER_PATTERN 128
  90. #define LEN_16BIT_SPECIAL_PATTERN 128
  91. #define LEN_16BIT_PBS_PATTERN 4
  92. #define CMP_BYTE_SHIFT 8
  93. #define CMP_BYTE_MASK 0xFF
  94. #define PUP_SIZE 8
  95. #define S 0
  96. #define C 1
  97. #define P 2
  98. #define D 3
  99. #define DQS 6
  100. #define PS 2
  101. #define DS 3
  102. #define PE 4
  103. #define DE 5
  104. #define CS0 0
  105. #define MAX_DIMM_NUM 2
  106. #define MAX_DELAY 0x1F
  107. /*
  108. * Invertion limit and phase1 limit are WA for the RL @ 1:1 design bug -
  109. * Armada 370 & AXP Z1
  110. */
  111. #define MAX_DELAY_INV_LIMIT 0x5
  112. #define MIN_DELAY_PHASE_1_LIMIT 0x10
  113. #define MAX_DELAY_INV (0x3F - MAX_DELAY_INV_LIMIT)
  114. #define MIN_DELAY 0
  115. #define MAX_PUP_NUM 9
  116. #define ECC_PUP 8
  117. #define DQ_NUM 8
  118. #define DQS_DQ_NUM 8
  119. #define INIT_WL_DELAY 13
  120. #define INIT_RL_DELAY 15
  121. #define TWLMRD_DELAY 20
  122. #define TCLK_3_DELAY 3
  123. #define ECC_BIT 8
  124. #define DMA_SIZE 64
  125. #define MV_DMA_0 0
  126. #define MAX_TRAINING_RETRY 10
  127. #define PUP_RL_MODE 0x2
  128. #define PUP_WL_MODE 0
  129. #define PUP_PBS_TX 0x10
  130. #define PUP_PBS_TX_DM 0x1A
  131. #define PUP_PBS_RX 0x30
  132. #define PUP_DQS_WR 0x1
  133. #define PUP_DQS_RD 0x3
  134. #define PUP_BC 10
  135. #define PUP_DELAY_MASK 0x1F
  136. #define PUP_PHASE_MASK 0x7
  137. #define PUP_NUM_64BIT 8
  138. #define PUP_NUM_32BIT 4
  139. #define PUP_NUM_16BIT 2
  140. /* control PHY registers */
  141. #define CNTRL_PUP_DESKEW 0x10
  142. /* WL */
  143. #define COUNT_WL_HI_FREQ 2
  144. #define COUNT_WL 2
  145. #define COUNT_WL_RFRS 9
  146. #define WL_HI_FREQ_SHIFT 2
  147. #define WL_HI_FREQ_STATE 1
  148. #define COUNT_HW_WL 2
  149. /* RL */
  150. /*
  151. * RL_MODE - this define uses the RL mode SW RL instead of the functional
  152. * window SW RL
  153. */
  154. #define RL_MODE
  155. #define RL_WINDOW_WA
  156. #define MAX_PHASE_1TO1 2
  157. #define MAX_PHASE_2TO1 4
  158. #define MAX_PHASE_RL_UL_1TO1 0
  159. #define MAX_PHASE_RL_L_1TO1 4
  160. #define MAX_PHASE_RL_UL_2TO1 3
  161. #define MAX_PHASE_RL_L_2TO1 7
  162. #define RL_UNLOCK_STATE 0
  163. #define RL_WINDOW_STATE 1
  164. #define RL_FINAL_STATE 2
  165. #define RL_RETRY_COUNT 2
  166. #define COUNT_HW_RL 2
  167. /* PBS */
  168. #define MAX_PBS 31
  169. #define MIN_PBS 0
  170. #define COUNT_PBS_PATTERN 2
  171. #define COUNT_PBS_STARTOVER 2
  172. #define COUNT_PBS_REPEAT 3
  173. #define COUNT_PBS_COMP_RETRY_NUM 2
  174. #define PBS_DIFF_LIMIT 31
  175. #define PATTERN_PBS_TX_A 0x55555555
  176. #define PATTERN_PBS_TX_B 0xAAAAAAAA
  177. /* DQS */
  178. #define ADLL_ERROR 0x55
  179. #define ADLL_MAX 31
  180. #define ADLL_MIN 0
  181. #define MIN_WIN_SIZE 4
  182. #define VALID_WIN_THRS MIN_WIN_SIZE
  183. #define MODE_2TO1 1
  184. #define MODE_1TO1 0
  185. /*
  186. * Macros
  187. */
  188. #define IS_PUP_ACTIVE(_data_, _pup_) (((_data_) >> (_pup_)) & 0x1)
  189. /*
  190. * Internal ERROR codes
  191. */
  192. #define MV_DDR3_TRAINING_ERR_WR_LVL_HW 0xDD302001
  193. #define MV_DDR3_TRAINING_ERR_LOAD_PATTERNS 0xDD302002
  194. #define MV_DDR3_TRAINING_ERR_WR_LVL_HI_FREQ 0xDD302003
  195. #define MV_DDR3_TRAINING_ERR_DFS_H2L 0xDD302004
  196. #define MV_DDR3_TRAINING_ERR_DRAM_COMPARE 0xDD302005
  197. #define MV_DDR3_TRAINING_ERR_WIN_LIMITS 0xDD302006
  198. #define MV_DDR3_TRAINING_ERR_PUP_RANGE 0xDD302025
  199. #define MV_DDR3_TRAINING_ERR_DQS_LOW_LIMIT_SEARCH 0xDD302007
  200. #define MV_DDR3_TRAINING_ERR_DQS_HIGH_LIMIT_SEARCH 0xDD302008
  201. #define MV_DDR3_TRAINING_ERR_DQS_PATTERN 0xDD302009
  202. #define MV_DDR3_TRAINING_ERR_PBS_ADLL_SHR_1PHASE 0xDD302010
  203. #define MV_DDR3_TRAINING_ERR_PBS_TX_MAX_VAL 0xDD302011
  204. #define MV_DDR3_TRAINING_ERR_PBS_RX_PER_BIT 0xDD302012
  205. #define MV_DDR3_TRAINING_ERR_PBS_TX_PER_BIT 0xDD302013
  206. #define MV_DDR3_TRAINING_ERR_PBS_RX_MAX_VAL 0xDD302014
  207. #define MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_SRAM_CMP 0xDD302015
  208. #define MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_MAX_VAL 0xDD302016
  209. #define MV_DDR3_TRAINING_ERR_RD_LVL_RL_PATTERN 0xDD302017
  210. #define MV_DDR3_TRAINING_ERR_RD_LVL_RL_PUP_UNLOCK 0xDD302018
  211. #define MV_DDR3_TRAINING_ERR_RD_LVL_PUP_UNLOCK 0xDD302019
  212. #define MV_DDR3_TRAINING_ERR_WR_LVL_SW 0xDD302020
  213. #define MV_DDR3_TRAINING_ERR_PRBS_RX 0xDD302021
  214. #define MV_DDR3_TRAINING_ERR_DQS_RX 0xDD302022
  215. #define MV_DDR3_TRAINING_ERR_PRBS_TX 0xDD302023
  216. #define MV_DDR3_TRAINING_ERR_DQS_TX 0xDD302024
  217. /*
  218. * DRAM information structure
  219. */
  220. typedef struct dram_info {
  221. u32 num_cs;
  222. u32 cs_ena;
  223. u32 num_of_std_pups; /* Q value = ddrWidth/8 - Without ECC!! */
  224. u32 num_of_total_pups; /* numOfStdPups + eccEna */
  225. u32 target_frequency; /* DDR Frequency */
  226. u32 ddr_width; /* 32/64 Bit or 16/32 Bit */
  227. u32 ecc_ena; /* 0/1 */
  228. u32 wl_val[MAX_CS][MAX_PUP_NUM][7];
  229. u32 rl_val[MAX_CS][MAX_PUP_NUM][7];
  230. u32 rl_max_phase;
  231. u32 rl_min_phase;
  232. u32 wl_max_phase;
  233. u32 wl_min_phase;
  234. u32 rd_smpl_dly;
  235. u32 rd_rdy_dly;
  236. u32 cl;
  237. u32 cwl;
  238. u32 mode_2t;
  239. int rl400_bug;
  240. int multi_cs_mr_support;
  241. int reg_dimm;
  242. } MV_DRAM_INFO;
  243. enum training_modes {
  244. DQS_WR_MODE,
  245. WL_MODE_,
  246. RL_MODE_,
  247. DQS_RD_MODE,
  248. PBS_TX_DM_MODE,
  249. PBS_TX_MODE,
  250. PBS_RX_MODE,
  251. MAX_TRAINING_MODE,
  252. };
  253. typedef struct dram_training_init {
  254. u32 reg_addr;
  255. u32 reg_value;
  256. } MV_DRAM_TRAINING_INIT;
  257. typedef struct dram_mv_init {
  258. u32 reg_addr;
  259. u32 reg_value;
  260. } MV_DRAM_MC_INIT;
  261. /* Board/Soc revisions define */
  262. enum board_rev {
  263. Z1,
  264. Z1_PCAC,
  265. Z1_RD_SLED,
  266. A0,
  267. A0_AMC
  268. };
  269. typedef struct dram_modes {
  270. char *mode_name;
  271. u8 cpu_freq;
  272. u8 fab_freq;
  273. u8 chip_id;
  274. int chip_board_rev;
  275. MV_DRAM_MC_INIT *regs;
  276. MV_DRAM_TRAINING_INIT *vals;
  277. } MV_DRAM_MODES;
  278. /*
  279. * Function Declarations
  280. */
  281. u32 cache_inv(u32 addr);
  282. void flush_l1_v7(u32 line);
  283. void flush_l1_v6(u32 line);
  284. u32 ddr3_cl_to_valid_cl(u32 cl);
  285. u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl);
  286. void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay);
  287. u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup);
  288. int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked, int is_tx,
  289. u32 pbs_pattern_idx, u32 pbs_curr_val,
  290. u32 pbs_lock_val, u32 *skew_array,
  291. u8 *unlock_pup_dq_array, u32 ecc);
  292. int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
  293. u32 *new_locked_pup, u32 *pattern,
  294. u32 pattern_len, u32 sdram_offset, int write,
  295. int mask, u32 *mask_pattern, int b_special_compare);
  296. int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
  297. u32 *new_locked_pup, u32 *pattern, u32 pattern_len,
  298. u32 sdram_offset, int write, int mask,
  299. u32 *mask_pattern, int b_special_compare);
  300. int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
  301. u32 *new_locked_pup, u32 *pattern,
  302. u32 pattern_len, u32 sdram_offset, int write,
  303. int mask, u32 *mask_pattern);
  304. int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
  305. u32 *new_locked_pup, u32 *pattern,
  306. u32 sdram_offset);
  307. int ddr3_dram_sram_read(u32 src, u32 dst, u32 len);
  308. int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume);
  309. int ddr3_read_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
  310. int ddr3_read_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
  311. int ddr3_write_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
  312. int ddr3_write_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
  313. int ddr3_write_leveling_hw_reg_dimm(u32 freq, MV_DRAM_INFO *dram_info);
  314. int ddr3_wl_supplement(MV_DRAM_INFO *dram_info);
  315. int ddr3_dfs_high_2_low(u32 freq, MV_DRAM_INFO *dram_info);
  316. int ddr3_dfs_low_2_high(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
  317. int ddr3_pbs_tx(MV_DRAM_INFO *dram_info);
  318. int ddr3_pbs_rx(MV_DRAM_INFO *dram_info);
  319. int ddr3_load_pbs_patterns(MV_DRAM_INFO *dram_info);
  320. int ddr3_dqs_centralization_rx(MV_DRAM_INFO *dram_info);
  321. int ddr3_dqs_centralization_tx(MV_DRAM_INFO *dram_info);
  322. int ddr3_load_dqs_patterns(MV_DRAM_INFO *dram_info);
  323. void ddr3_static_training_init(void);
  324. u8 ddr3_get_eprom_fabric(void);
  325. void ddr3_set_performance_params(MV_DRAM_INFO *dram_info);
  326. int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len);
  327. void ddr3_save_training(MV_DRAM_INFO *dram_info);
  328. int ddr3_read_training_results(void);
  329. int ddr3_training_suspend_resume(MV_DRAM_INFO *dram_info);
  330. int ddr3_get_min_max_read_sample_delay(u32 cs_enable, u32 reg, u32 *min,
  331. u32 *max, u32 *cs_max);
  332. int ddr3_get_min_max_rl_phase(MV_DRAM_INFO *dram_info, u32 *min, u32 *max,
  333. u32 cs);
  334. int ddr3_odt_activate(int activate);
  335. int ddr3_odt_read_dynamic_config(MV_DRAM_INFO *dram_info);
  336. void ddr3_print_freq(u32 freq);
  337. void ddr3_reset_phy_read_fifo(void);
  338. #endif /* __DDR3_TRAINING_H */