ddr3_axp_mc_static.h 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284
  1. /*
  2. * Copyright (C) Marvell International Ltd. and its affiliates
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #ifndef __AXP_MC_STATIC_H
  7. #define __AXP_MC_STATIC_H
  8. MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
  9. #ifdef CONFIG_DDR_32BIT
  10. {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
  11. #else /*CONFIG_DDR_64BIT */
  12. {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
  13. #endif
  14. {0x00001404, 0x3630b800}, /*Dunit Control Low Register */
  15. {0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
  16. /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
  17. {0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
  18. #ifdef DB_78X60_PCAC
  19. {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
  20. #else
  21. {0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
  22. #endif
  23. {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
  24. {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
  25. {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
  26. {0x00001424, 0x0000D3FF}, /*Dunit Control High Register */
  27. {0x00001428, 0x000F8830}, /*Dunit Control High Register */
  28. {0x0000142C, 0x214C2F38}, /*Dunit Control High Register */
  29. {0x0000147C, 0x0000c671},
  30. {0x000014a0, 0x000002A9},
  31. {0x000014a8, 0x00000101}, /*2:1 */
  32. {0x00020220, 0x00000007},
  33. {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
  34. {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
  35. {0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
  36. {0x000014C0, 0x192434e9}, /* DRAM address and Control Driving Strenght */
  37. {0x000014C4, 0x092434e9}, /* DRAM Data and DQS Driving Strenght */
  38. {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
  39. {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
  40. {0x0001504, 0x7FFFFFF1}, /* CS0 Size */
  41. {0x000150C, 0x00000000}, /* CS1 Size */
  42. {0x0001514, 0x00000000}, /* CS2 Size */
  43. {0x000151C, 0x00000000}, /* CS3 Size */
  44. /* {0x00001524, 0x0000C800}, */
  45. {0x00001538, 0x0000000b}, /*Read Data Sample Delays Register */
  46. {0x0000153C, 0x0000000d}, /*Read Data Ready Delay Register */
  47. {0x000015D0, 0x00000640}, /*MR0 */
  48. {0x000015D4, 0x00000046}, /*MR1 */
  49. {0x000015D8, 0x00000010}, /*MR2 */
  50. {0x000015DC, 0x00000000}, /*MR3 */
  51. {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
  52. {0x000015EC, 0xd800aa25}, /*DDR PHY */
  53. {0x0, 0x0}
  54. };
  55. MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = {
  56. #ifdef CONFIG_DDR_32BIT
  57. {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
  58. #else /*CONFIG_DDR_64BIT */
  59. {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
  60. #endif
  61. {0x00001404, 0x3630b800}, /*Dunit Control Low Register */
  62. {0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
  63. /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
  64. {0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
  65. #ifdef DB_78X60_PCAC
  66. {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
  67. #else
  68. {0x00001410, 0x040F000C}, /*DDR SDRAM Open Pages Control Register */
  69. #endif
  70. {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
  71. {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
  72. {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
  73. {0x00001424, 0x0000D3FF}, /*Dunit Control High Register */
  74. {0x00001428, 0x000F8830}, /*Dunit Control High Register */
  75. {0x0000142C, 0x214C2F38}, /*Dunit Control High Register */
  76. {0x0000147C, 0x0000c671},
  77. {0x000014a0, 0x000002A9},
  78. {0x000014a8, 0x00000101}, /*2:1 */
  79. {0x00020220, 0x00000007},
  80. {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
  81. {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
  82. {0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
  83. {0x000014C0, 0x192434e9}, /* DRAM address and Control Driving Strenght */
  84. {0x000014C4, 0x092434e9}, /* DRAM Data and DQS Driving Strenght */
  85. {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
  86. {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
  87. {0x0001504, 0x3FFFFFF1}, /* CS0 Size */
  88. {0x000150C, 0x00000000}, /* CS1 Size */
  89. {0x0001514, 0x00000000}, /* CS2 Size */
  90. {0x000151C, 0x00000000}, /* CS3 Size */
  91. /* {0x00001524, 0x0000C800}, */
  92. {0x00001538, 0x0000000b}, /*Read Data Sample Delays Register */
  93. {0x0000153C, 0x0000000d}, /*Read Data Ready Delay Register */
  94. {0x000015D0, 0x00000640}, /*MR0 */
  95. {0x000015D4, 0x00000046}, /*MR1 */
  96. {0x000015D8, 0x00000010}, /*MR2 */
  97. {0x000015DC, 0x00000000}, /*MR3 */
  98. {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
  99. {0x000015EC, 0xd800aa25}, /*DDR PHY */
  100. {0x0, 0x0}
  101. };
  102. MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
  103. #ifdef CONFIG_DDR_32BIT
  104. {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */
  105. #else /* CONFIG_DDR_64BIT */
  106. {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */
  107. #endif
  108. {0x00001404, 0x3630B840}, /*Dunit Control Low Register */
  109. {0x00001408, 0x33137663}, /*DDR SDRAM Timing (Low) Register */
  110. {0x0000140C, 0x38000C55}, /*DDR SDRAM Timing (High) Register */
  111. {0x00001410, 0x040F0000}, /*DDR SDRAM Address Control Register */
  112. {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
  113. {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
  114. {0x0000141C, 0x00000672}, /*DDR SDRAM Mode Register */
  115. {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
  116. {0x00001424, 0x0100D3FF}, /*Dunit Control High Register */
  117. {0x00001428, 0x000D6720}, /*Dunit Control High Register */
  118. {0x0000142C, 0x014C2F38}, /*Dunit Control High Register */
  119. {0x0000147C, 0x00006571},
  120. {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
  121. {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
  122. {0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
  123. {0x000014a0, 0x000002A9},
  124. {0x000014a8, 0x00000101}, /*2:1 */
  125. {0x00020220, 0x00000007},
  126. {0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */
  127. {0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
  128. {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
  129. {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
  130. {0x0001504, 0x7FFFFFF1}, /* CS0 Size */
  131. {0x000150C, 0x00000000}, /* CS1 Size */
  132. {0x0001514, 0x00000000}, /* CS2 Size */
  133. {0x000151C, 0x00000000}, /* CS3 Size */
  134. {0x00001538, 0x00000008}, /*Read Data Sample Delays Register */
  135. {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
  136. {0x000015D0, 0x00000630}, /*MR0 */
  137. {0x000015D4, 0x00000046}, /*MR1 */
  138. {0x000015D8, 0x00000008}, /*MR2 */
  139. {0x000015DC, 0x00000000}, /*MR3 */
  140. {0x000015E4, 0x00203c18}, /*ZQDS Configuration Register */
  141. /* {0x000015EC, 0xDE000025}, *//*DDR PHY */
  142. {0x000015EC, 0xF800AA25}, /*DDR PHY */
  143. {0x0, 0x0}
  144. };
  145. MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
  146. #ifdef CONFIG_DDR_32BIT
  147. {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */
  148. #else /*CONFIG_DDR_64BIT */
  149. {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
  150. #endif
  151. {0x00001404, 0x3630B040}, /*Dunit Control Low Register */
  152. {0x00001408, 0x44149887}, /*DDR SDRAM Timing (Low) Register */
  153. /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
  154. {0x0000140C, 0x38D83FE0}, /*DDR SDRAM Timing (High) Register */
  155. #ifdef DB_78X60_PCAC
  156. {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
  157. #else
  158. {0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
  159. #endif
  160. {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
  161. {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
  162. {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
  163. {0x00001424, 0x0100D1FF}, /*Dunit Control High Register */
  164. {0x00001428, 0x000F8830}, /*Dunit Control High Register */
  165. {0x0000142C, 0x214C2F38}, /*Dunit Control High Register */
  166. {0x0000147C, 0x0000c671},
  167. {0x000014a8, 0x00000101}, /*2:1 */
  168. {0x00020220, 0x00000007},
  169. {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
  170. {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
  171. {0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
  172. {0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */
  173. {0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
  174. {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
  175. {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
  176. {0x0001504, 0x7FFFFFF1}, /* CS0 Size */
  177. {0x000150C, 0x00000000}, /* CS1 Size */
  178. {0x0001514, 0x00000000}, /* CS2 Size */
  179. {0x000151C, 0x00000000}, /* CS3 Size */
  180. /* {0x00001524, 0x0000C800}, */
  181. {0x00001538, 0x0000000b}, /*Read Data Sample Delays Register */
  182. {0x0000153C, 0x0000000d}, /*Read Data Ready Delay Register */
  183. {0x000015D0, 0x00000650}, /*MR0 */
  184. {0x000015D4, 0x00000046}, /*MR1 */
  185. {0x000015D8, 0x00000010}, /*MR2 */
  186. {0x000015DC, 0x00000000}, /*MR3 */
  187. {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
  188. {0x000015EC, 0xDE000025}, /*DDR PHY */
  189. {0x0, 0x0}
  190. };
  191. MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = {
  192. #ifdef CONFIG_DDR_32BIT
  193. {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */
  194. #else /*CONFIG_DDR_64BIT */
  195. {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */
  196. /*{0x00001400, 0x7304CC30}, *//*DDR SDRAM Configuration Register */
  197. #endif
  198. {0x00001404, 0x3630B840}, /*Dunit Control Low Register */
  199. {0x00001408, 0x33137663}, /*DDR SDRAM Timing (Low) Register */
  200. {0x0000140C, 0x38000C55}, /*DDR SDRAM Timing (High) Register */
  201. {0x00001410, 0x040F0000}, /*DDR SDRAM Address Control Register */
  202. {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
  203. {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
  204. {0x0000141C, 0x00000672}, /*DDR SDRAM Mode Register */
  205. {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
  206. {0x00001424, 0x0100F1FF}, /*Dunit Control High Register */
  207. {0x00001428, 0x000D6720}, /*Dunit Control High Register */
  208. {0x0000142C, 0x014C2F38}, /*Dunit Control High Register */
  209. {0x0000147C, 0x00006571},
  210. {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
  211. {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
  212. {0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */
  213. {0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */
  214. {0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
  215. {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
  216. {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
  217. {0x0001504, 0x7FFFFFF1}, /* CS0 Size */
  218. {0x000150C, 0x00000000}, /* CS1 Size */
  219. {0x0001514, 0x00000000}, /* CS2 Size */
  220. {0x000151C, 0x00000000}, /* CS3 Size */
  221. {0x00001538, 0x00000008}, /*Read Data Sample Delays Register */
  222. {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
  223. {0x000015D0, 0x00000630}, /*MR0 */
  224. {0x000015D4, 0x00000046}, /*MR1 */
  225. {0x000015D8, 0x00000008}, /*MR2 */
  226. {0x000015DC, 0x00000000}, /*MR3 */
  227. {0x000015E4, 0x00203c18}, /*ZQDS Configuration Register */
  228. {0x000015EC, 0xDE000025}, /*DDR PHY */
  229. {0x0, 0x0}
  230. };
  231. #endif /* __AXP_MC_STATIC_H */