ddr3_axp_config.h 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151
  1. /*
  2. * Copyright (C) Marvell International Ltd. and its affiliates
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #ifndef __DDR3_AXP_CONFIG_H
  7. #define __DDR3_AXP_CONFIG_H
  8. /*
  9. * DDR3_LOG_LEVEL Information
  10. *
  11. * Level 0: Provides an error code in a case of failure, RL, WL errors
  12. * and other algorithm failure
  13. * Level 1: Provides the D-Unit setup (SPD/Static configuration)
  14. * Level 2: Provides the windows margin as a results of DQS centeralization
  15. * Level 3: Provides the windows margin of each DQ as a results of DQS
  16. * centeralization
  17. */
  18. #ifdef CONFIG_DDR_LOG_LEVEL
  19. #define DDR3_LOG_LEVEL CONFIG_DDR_LOG_LEVEL
  20. #else
  21. #define DDR3_LOG_LEVEL 0
  22. #endif
  23. #define DDR3_PBS 1
  24. /* This flag allows the execution of SW WL/RL upon HW failure */
  25. #define DDR3_RUN_SW_WHEN_HW_FAIL 1
  26. /*
  27. * General Configurations
  28. *
  29. * The following parameters are required for proper setup:
  30. *
  31. * DDR_TARGET_FABRIC - Set desired fabric configuration
  32. * (for sample@Reset fabfreq parameter)
  33. * DRAM_ECC - Set ECC support 1/0
  34. * BUS_WIDTH - 64/32 bit
  35. * CONFIG_SPD_EEPROM - Enables auto detection of DIMMs and their timing values
  36. * DQS_CLK_ALIGNED - Set this if CLK and DQS signals are aligned on board
  37. * MIXED_DIMM_STATIC - Mixed DIMM + On board devices support (ODT registers
  38. * values are taken statically)
  39. * DDR3_TRAINING_DEBUG - Debug prints of internal code
  40. */
  41. #define DDR_TARGET_FABRIC 5
  42. /* Only enable ECC if the board selects it */
  43. #ifdef CONFIG_BOARD_ECC_SUPPORT
  44. #define DRAM_ECC 1
  45. #else
  46. #define DRAM_ECC 0
  47. #endif
  48. #ifdef CONFIG_DDR_32BIT
  49. #define BUS_WIDTH 32
  50. #else
  51. #define BUS_WIDTH 64
  52. #endif
  53. #undef DQS_CLK_ALIGNED
  54. #undef MIXED_DIMM_STATIC
  55. #define DDR3_TRAINING_DEBUG 0
  56. #define REG_DIMM_SKIP_WL 0
  57. /* Marvell boards specific configurations */
  58. #if defined(DB_78X60_PCAC)
  59. #undef CONFIG_SPD_EEPROM
  60. #define STATIC_TRAINING
  61. #endif
  62. #if defined(DB_78X60_AMC)
  63. #undef CONFIG_SPD_EEPROM
  64. #undef DRAM_ECC
  65. #define DRAM_ECC 1
  66. #endif
  67. #ifdef CONFIG_SPD_EEPROM
  68. /*
  69. * DIMM support parameters:
  70. * DRAM_2T - Set Desired 2T Mode - 0 - 1T, 0x1 - 2T, 0x2 - 3T
  71. * DIMM_CS_BITMAP - bitmap representing the optional CS in DIMMs
  72. * (0xF=CS0+CS1+CS2+CS3, 0xC=CS2+CS3...)
  73. */
  74. #define DRAM_2T 0x0
  75. #define DIMM_CS_BITMAP 0xF
  76. #define DUNIT_SPD
  77. #endif
  78. #ifdef DRAM_ECC
  79. /*
  80. * ECC support parameters:
  81. *
  82. * U_BOOT_START_ADDR, U_BOOT_SCRUB_SIZE - relevant when using ECC and need
  83. * to configure the scrubbing area
  84. */
  85. #define TRAINING_SIZE 0x20000
  86. #define U_BOOT_START_ADDR 0
  87. #define U_BOOT_SCRUB_SIZE 0x1000000 /* TRAINING_SIZE */
  88. #endif
  89. /*
  90. * Registered DIMM Support - In case registered DIMM is attached,
  91. * please supply the following values:
  92. * (see JEDEC - JESD82-29A "Definition of the SSTE32882 Registering Clock
  93. * Driver with Parity and Quad Chip
  94. * Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications")
  95. * RC0: Global Features Control Word
  96. * RC1: Clock Driver Enable Control Word
  97. * RC2: Timing Control Word
  98. * RC3-RC5 - taken from SPD
  99. * RC8: Additional IBT Setting Control Word
  100. * RC9: Power Saving Settings Control Word
  101. * RC10: Encoding for RDIMM Operating Speed
  102. * RC11: Operating Voltage VDD and VREFCA Control Word
  103. */
  104. #define RDIMM_RC0 0
  105. #define RDIMM_RC1 0
  106. #define RDIMM_RC2 0
  107. #define RDIMM_RC8 0
  108. #define RDIMM_RC9 0
  109. #define RDIMM_RC10 0x2
  110. #define RDIMM_RC11 0x0
  111. #if defined(MIXED_DIMM_STATIC) || !defined(CONFIG_SPD_EEPROM)
  112. #define DUNIT_STATIC
  113. #endif
  114. #if defined(MIXED_DIMM_STATIC) || defined(CONFIG_SPD_EEPROM)
  115. /*
  116. * This flag allows the user to change the dram refresh cycle in ps,
  117. * only in case of SPD or MIX DIMM topology
  118. */
  119. #define TREFI_USER_EN
  120. #ifdef TREFI_USER_EN
  121. #define TREFI_USER 3900000
  122. #endif
  123. #endif
  124. #ifdef CONFIG_SPD_EEPROM
  125. /*
  126. * AUTO_DETECTION_SUPPORT - relevant ONLY for Marvell DB boards.
  127. * Enables I2C auto detection different options
  128. */
  129. #if defined(CONFIG_DB_88F78X60) || defined(CONFIG_DB_88F78X60_REV2) || \
  130. defined(CONFIG_DB_784MP_GP)
  131. #define AUTO_DETECTION_SUPPORT
  132. #endif
  133. #endif
  134. #endif /* __DDR3_AXP_CONFIG_H */