lpddr2.c 4.1 KB

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  1. /*
  2. * (C) Copyright 2015, Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <asm/io.h>
  7. #include <asm/arch/imx-regs.h>
  8. #include <asm/arch/siul.h>
  9. #include <asm/arch/lpddr2.h>
  10. #include <asm/arch/mmdc.h>
  11. volatile int mscr_offset_ck0;
  12. void lpddr2_config_iomux(uint8_t module)
  13. {
  14. int i;
  15. switch (module) {
  16. case DDR0:
  17. mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0);
  18. writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0));
  19. writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0));
  20. writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1));
  21. writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0));
  22. writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1));
  23. for (i = _DDR0_DM0; i <= _DDR0_DM3; i++)
  24. writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
  25. for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++)
  26. writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
  27. for (i = _DDR0_A0; i <= _DDR0_A9; i++)
  28. writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
  29. for (i = _DDR0_D0; i <= _DDR0_D31; i++)
  30. writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
  31. break;
  32. case DDR1:
  33. writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0));
  34. writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0));
  35. writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1));
  36. writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0));
  37. writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1));
  38. for (i = _DDR1_DM0; i <= _DDR1_DM3; i++)
  39. writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
  40. for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++)
  41. writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
  42. for (i = _DDR1_A0; i <= _DDR1_A9; i++)
  43. writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
  44. for (i = _DDR1_D0; i <= _DDR1_D31; i++)
  45. writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
  46. break;
  47. }
  48. }
  49. void config_mmdc(uint8_t module)
  50. {
  51. unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR;
  52. writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR);
  53. writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0);
  54. writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1);
  55. writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2);
  56. writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP);
  57. writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC);
  58. writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC);
  59. writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR);
  60. writel(_MDCTL, mmdc_addr + MMDC_MDCTL);
  61. writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0);
  62. while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) {
  63. }
  64. writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR);
  65. /* Perform ZQ calibration */
  66. writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL);
  67. writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL);
  68. while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) {
  69. }
  70. /* Enable MMDC with CS0 */
  71. writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL);
  72. /* Complete the initialization sequence as defined by JEDEC */
  73. writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR);
  74. writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR);
  75. writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR);
  76. writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR);
  77. /* Set the amount of DRAM */
  78. /* Set DQS settings based on board type */
  79. switch (module) {
  80. case MMDC0:
  81. writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP);
  82. writel(MMDC_MPRDDLCTL_MODULE0_VALUE,
  83. mmdc_addr + MMDC_MPRDDLCTL);
  84. writel(MMDC_MPWRDLCTL_MODULE0_VALUE,
  85. mmdc_addr + MMDC_MPWRDLCTL);
  86. writel(MMDC_MPDGCTRL0_MODULE0_VALUE,
  87. mmdc_addr + MMDC_MPDGCTRL0);
  88. writel(MMDC_MPDGCTRL1_MODULE0_VALUE,
  89. mmdc_addr + MMDC_MPDGCTRL1);
  90. break;
  91. case MMDC1:
  92. writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP);
  93. writel(MMDC_MPRDDLCTL_MODULE1_VALUE,
  94. mmdc_addr + MMDC_MPRDDLCTL);
  95. writel(MMDC_MPWRDLCTL_MODULE1_VALUE,
  96. mmdc_addr + MMDC_MPWRDLCTL);
  97. writel(MMDC_MPDGCTRL0_MODULE1_VALUE,
  98. mmdc_addr + MMDC_MPDGCTRL0);
  99. writel(MMDC_MPDGCTRL1_MODULE1_VALUE,
  100. mmdc_addr + MMDC_MPDGCTRL1);
  101. break;
  102. }
  103. writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD);
  104. writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC);
  105. writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF);
  106. writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL);
  107. writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR);
  108. }