luan.c 5.9 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * John Otken, jotken@softadvances.com
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <asm/ppc4xx.h>
  10. #include <asm/processor.h>
  11. #include <asm/ppc4xx-isram.h>
  12. #include <spd_sdram.h>
  13. #include "epld.h"
  14. DECLARE_GLOBAL_DATA_PTR;
  15. extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  16. /*************************************************************************
  17. * int board_early_init_f()
  18. *
  19. ************************************************************************/
  20. int board_early_init_f(void)
  21. {
  22. u32 mfr;
  23. mtebc( PB0AP, 0x03800000 ); /* set chip selects */
  24. mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
  25. mtebc( PB1AP, 0x03800000 );
  26. mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
  27. mtebc( PB2AP, 0x03800000 );
  28. mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
  29. mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */
  30. mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */
  31. mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */
  32. mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */
  33. mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */
  34. mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
  35. mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */
  36. mtdcr( UIC1SR, 0xffffffff );
  37. mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */
  38. mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */
  39. mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */
  40. mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */
  41. mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */
  42. mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
  43. mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */
  44. mtdcr( UIC0SR, 0xffffffff );
  45. mfsdr(SDR0_MFR, mfr);
  46. mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
  47. mtsdr(SDR0_MFR, mfr);
  48. return 0;
  49. }
  50. /*************************************************************************
  51. * int misc_init_r()
  52. *
  53. ************************************************************************/
  54. int misc_init_r(void)
  55. {
  56. volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE;
  57. /* set modes of operation */
  58. x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
  59. EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
  60. /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
  61. x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
  62. /* put Ethernet+PHY in reset */
  63. x->ethuart &= ~EPLD2_RESET_ETH_N;
  64. udelay(10000);
  65. /* take Ethernet+PHY out of reset */
  66. x->ethuart |= EPLD2_RESET_ETH_N;
  67. return 0;
  68. }
  69. /*************************************************************************
  70. * int checkboard()
  71. *
  72. ************************************************************************/
  73. int checkboard(void)
  74. {
  75. char buf[64];
  76. int i = getenv_f("serial#", buf, sizeof(buf));
  77. printf("Board: Luan - AMCC PPC440SP Evaluation Board");
  78. if (i > 0) {
  79. puts(", serial# ");
  80. puts(buf);
  81. }
  82. putc('\n');
  83. return 0;
  84. }
  85. /*
  86. * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
  87. * board specific values.
  88. */
  89. u32 ddr_clktr(u32 default_val) {
  90. return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
  91. }
  92. /*************************************************************************
  93. * hw_watchdog_reset
  94. *
  95. * This routine is called to reset (keep alive) the watchdog timer
  96. *
  97. ************************************************************************/
  98. #if defined(CONFIG_HW_WATCHDOG)
  99. void hw_watchdog_reset(void)
  100. {
  101. }
  102. #endif
  103. /*************************************************************************
  104. * int on_off()
  105. *
  106. ************************************************************************/
  107. static int on_off( const char *s )
  108. {
  109. if (strcmp(s, "on") == 0) {
  110. return 1;
  111. } else if (strcmp(s, "off") == 0) {
  112. return 0;
  113. }
  114. return -1;
  115. }
  116. /*************************************************************************
  117. * void l2cache_disable()
  118. *
  119. ************************************************************************/
  120. static void l2cache_disable(void)
  121. {
  122. mtdcr( L2_CACHE_CFG, 0 );
  123. }
  124. /*************************************************************************
  125. * void l2cache_enable()
  126. *
  127. ************************************************************************/
  128. static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
  129. {
  130. mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
  131. mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */
  132. mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
  133. while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ; /* poll L2_SR for completion */
  134. mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
  135. mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
  136. mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */
  137. mtdcr( L2_CACHE_SNP1, 0 );
  138. __asm__ volatile ("sync"); /* msync */
  139. mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */
  140. __asm__ volatile ("sync");
  141. }
  142. /*************************************************************************
  143. * int l2cache_status()
  144. *
  145. ************************************************************************/
  146. static int l2cache_status(void)
  147. {
  148. return (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0;
  149. }
  150. /*************************************************************************
  151. * int do_l2cache()
  152. *
  153. ************************************************************************/
  154. int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] )
  155. {
  156. switch (argc) {
  157. case 2: /* on / off */
  158. switch (on_off(argv[1])) {
  159. case 0: l2cache_disable();
  160. break;
  161. case 1: l2cache_enable();
  162. break;
  163. }
  164. /* FALL TROUGH */
  165. case 1: /* get status */
  166. printf ("L2 Cache is %s\n",
  167. l2cache_status() ? "ON" : "OFF");
  168. return 0;
  169. default:
  170. return cmd_usage(cmdtp);
  171. }
  172. return 0;
  173. }
  174. U_BOOT_CMD(
  175. l2cache, 2, 1, do_l2cache,
  176. "enable or disable L2 cache",
  177. "[on, off]\n"
  178. " - enable or disable L2 cache"
  179. );