bamboo.c 60 KB

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  1. /*
  2. * (C) Copyright 2005-2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <asm/processor.h>
  9. #include <asm/ppc4xx-gpio.h>
  10. #include <spd_sdram.h>
  11. #include <asm/ppc440.h>
  12. #include "bamboo.h"
  13. DECLARE_GLOBAL_DATA_PTR;
  14. void ext_bus_cntlr_init(void);
  15. void configure_ppc440ep_pins(void);
  16. int is_nand_selected(void);
  17. /*************************************************************************
  18. *
  19. * Bamboo has one bank onboard sdram (plus DIMM)
  20. *
  21. * Fixed memory is composed of :
  22. * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
  23. * 13 row add bits, 10 column add bits (but 12 row used only).
  24. * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
  25. * 12 row add bits, 10 column add bits.
  26. * Prepare a subset (only the used ones) of SPD data
  27. *
  28. * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
  29. * the corresponding bank is divided by 2 due to number of Row addresses
  30. * 12 in the ECC module
  31. *
  32. * Assumes: 64 MB, ECC, non-registered
  33. * PLB @ 133 MHz
  34. *
  35. ************************************************************************/
  36. const unsigned char cfg_simulate_spd_eeprom[128] = {
  37. 0x80, /* number of SPD bytes used: 128 */
  38. 0x08, /* total number bytes in SPD device = 256 */
  39. 0x07, /* DDR ram */
  40. #ifdef CONFIG_DDR_ECC
  41. 0x0C, /* num Row Addr: 12 */
  42. #else
  43. 0x0D, /* num Row Addr: 13 */
  44. #endif
  45. 0x09, /* numColAddr: 9 */
  46. 0x01, /* numBanks: 1 */
  47. 0x20, /* Module data width: 32 bits */
  48. 0x00, /* Module data width continued: +0 */
  49. 0x04, /* 2.5 Volt */
  50. 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
  51. 0x00, /* SDRAM Access from clock */
  52. #ifdef CONFIG_DDR_ECC
  53. 0x02, /* ECC ON : 02 OFF : 00 */
  54. #else
  55. 0x00, /* ECC ON : 02 OFF : 00 */
  56. #endif
  57. 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
  58. 0,
  59. 0,
  60. 0x01, /* wcsbc = 1 */
  61. 0,
  62. 0,
  63. 0x0C, /* casBit (2,2.5) */
  64. 0,
  65. 0,
  66. 0x00, /* not registered: 0 registered : 0x02*/
  67. 0,
  68. 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
  69. 0,
  70. 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
  71. 0,
  72. 0x50, /* tRpNs = 20 ns */
  73. 0,
  74. 0x50, /* tRcdNs = 20 ns */
  75. 45, /* tRasNs */
  76. #ifdef CONFIG_DDR_ECC
  77. 0x08, /* bankSizeID: 32MB */
  78. #else
  79. 0x10, /* bankSizeID: 64MB */
  80. #endif
  81. 0,
  82. 0,
  83. 0,
  84. 0,
  85. 0,
  86. 0,
  87. 0,
  88. 0,
  89. 0,
  90. 0,
  91. 0,
  92. 0,
  93. 0,
  94. 0,
  95. 0,
  96. 0,
  97. 0,
  98. 0,
  99. 0,
  100. 0,
  101. 0,
  102. 0,
  103. 0,
  104. 0,
  105. 0,
  106. 0,
  107. 0,
  108. 0,
  109. 0,
  110. 0,
  111. 0,
  112. 0,
  113. 0,
  114. 0,
  115. 0,
  116. 0,
  117. 0,
  118. 0,
  119. 0,
  120. 0,
  121. 0,
  122. 0,
  123. 0,
  124. 0,
  125. 0,
  126. 0,
  127. 0,
  128. 0,
  129. 0,
  130. 0,
  131. 0,
  132. 0,
  133. 0,
  134. 0,
  135. 0,
  136. 0,
  137. 0,
  138. 0,
  139. 0,
  140. 0,
  141. 0,
  142. 0,
  143. 0,
  144. 0,
  145. 0,
  146. 0,
  147. 0,
  148. 0,
  149. 0,
  150. 0,
  151. 0,
  152. 0,
  153. 0,
  154. 0,
  155. 0,
  156. 0,
  157. 0,
  158. 0,
  159. 0,
  160. 0,
  161. 0,
  162. 0,
  163. 0,
  164. 0,
  165. 0,
  166. 0,
  167. 0,
  168. 0,
  169. 0,
  170. 0,
  171. 0,
  172. 0,
  173. 0,
  174. 0,
  175. 0,
  176. 0
  177. };
  178. #if 0
  179. { /* GPIO Alternate1 Alternate2 Alternate3 */
  180. {
  181. /* GPIO Core 0 */
  182. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
  183. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
  184. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
  185. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
  186. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
  187. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
  188. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
  189. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
  190. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
  191. { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
  192. { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
  193. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
  194. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
  195. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
  196. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
  197. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
  198. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
  199. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
  200. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
  201. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
  202. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
  203. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
  204. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
  205. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
  206. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
  207. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
  208. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
  209. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
  210. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
  211. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
  212. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
  213. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
  214. },
  215. {
  216. /* GPIO Core 1 */
  217. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
  218. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
  219. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
  220. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
  221. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
  222. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
  223. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
  224. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
  225. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
  226. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
  227. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
  228. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
  229. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
  230. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
  231. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
  232. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
  233. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
  234. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
  235. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
  236. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
  237. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
  238. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
  239. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
  240. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
  241. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
  242. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
  243. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
  244. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
  245. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
  246. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
  247. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
  248. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
  249. }
  250. };
  251. #endif
  252. /*----------------------------------------------------------------------------+
  253. | EBC Devices Characteristics
  254. | Peripheral Bank Access Parameters - EBC0_BnAP
  255. | Peripheral Bank Configuration Register - EBC0_BnCR
  256. +----------------------------------------------------------------------------*/
  257. /* Small Flash */
  258. #define EBC0_BNAP_SMALL_FLASH \
  259. EBC0_BNAP_BME_DISABLED | \
  260. EBC0_BNAP_TWT_ENCODE(6) | \
  261. EBC0_BNAP_CSN_ENCODE(0) | \
  262. EBC0_BNAP_OEN_ENCODE(1) | \
  263. EBC0_BNAP_WBN_ENCODE(1) | \
  264. EBC0_BNAP_WBF_ENCODE(3) | \
  265. EBC0_BNAP_TH_ENCODE(1) | \
  266. EBC0_BNAP_RE_ENABLED | \
  267. EBC0_BNAP_SOR_DELAYED | \
  268. EBC0_BNAP_BEM_WRITEONLY | \
  269. EBC0_BNAP_PEN_DISABLED
  270. #define EBC0_BNCR_SMALL_FLASH_CS0 \
  271. EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
  272. EBC0_BNCR_BS_1MB | \
  273. EBC0_BNCR_BU_RW | \
  274. EBC0_BNCR_BW_8BIT
  275. #define EBC0_BNCR_SMALL_FLASH_CS4 \
  276. EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
  277. EBC0_BNCR_BS_1MB | \
  278. EBC0_BNCR_BU_RW | \
  279. EBC0_BNCR_BW_8BIT
  280. /* Large Flash or SRAM */
  281. #define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
  282. EBC0_BNAP_BME_DISABLED | \
  283. EBC0_BNAP_TWT_ENCODE(8) | \
  284. EBC0_BNAP_CSN_ENCODE(0) | \
  285. EBC0_BNAP_OEN_ENCODE(1) | \
  286. EBC0_BNAP_WBN_ENCODE(1) | \
  287. EBC0_BNAP_WBF_ENCODE(1) | \
  288. EBC0_BNAP_TH_ENCODE(2) | \
  289. EBC0_BNAP_SOR_DELAYED | \
  290. EBC0_BNAP_BEM_RW | \
  291. EBC0_BNAP_PEN_DISABLED
  292. #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
  293. EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
  294. EBC0_BNCR_BS_8MB | \
  295. EBC0_BNCR_BU_RW | \
  296. EBC0_BNCR_BW_16BIT
  297. #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
  298. EBC0_BNCR_BAS_ENCODE(0x87800000) | \
  299. EBC0_BNCR_BS_8MB | \
  300. EBC0_BNCR_BU_RW | \
  301. EBC0_BNCR_BW_16BIT
  302. /* NVRAM - FPGA */
  303. #define EBC0_BNAP_NVRAM_FPGA \
  304. EBC0_BNAP_BME_DISABLED | \
  305. EBC0_BNAP_TWT_ENCODE(9) | \
  306. EBC0_BNAP_CSN_ENCODE(0) | \
  307. EBC0_BNAP_OEN_ENCODE(1) | \
  308. EBC0_BNAP_WBN_ENCODE(1) | \
  309. EBC0_BNAP_WBF_ENCODE(0) | \
  310. EBC0_BNAP_TH_ENCODE(2) | \
  311. EBC0_BNAP_RE_ENABLED | \
  312. EBC0_BNAP_SOR_DELAYED | \
  313. EBC0_BNAP_BEM_WRITEONLY | \
  314. EBC0_BNAP_PEN_DISABLED
  315. #define EBC0_BNCR_NVRAM_FPGA_CS5 \
  316. EBC0_BNCR_BAS_ENCODE(0x80000000) | \
  317. EBC0_BNCR_BS_1MB | \
  318. EBC0_BNCR_BU_RW | \
  319. EBC0_BNCR_BW_8BIT
  320. /* Nand Flash */
  321. #define EBC0_BNAP_NAND_FLASH \
  322. EBC0_BNAP_BME_DISABLED | \
  323. EBC0_BNAP_TWT_ENCODE(3) | \
  324. EBC0_BNAP_CSN_ENCODE(0) | \
  325. EBC0_BNAP_OEN_ENCODE(0) | \
  326. EBC0_BNAP_WBN_ENCODE(0) | \
  327. EBC0_BNAP_WBF_ENCODE(0) | \
  328. EBC0_BNAP_TH_ENCODE(1) | \
  329. EBC0_BNAP_RE_ENABLED | \
  330. EBC0_BNAP_SOR_NOT_DELAYED | \
  331. EBC0_BNAP_BEM_RW | \
  332. EBC0_BNAP_PEN_DISABLED
  333. #define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
  334. /* NAND0 */
  335. #define EBC0_BNCR_NAND_FLASH_CS1 \
  336. EBC0_BNCR_BAS_ENCODE(0x90000000) | \
  337. EBC0_BNCR_BS_1MB | \
  338. EBC0_BNCR_BU_RW | \
  339. EBC0_BNCR_BW_32BIT
  340. /* NAND1 - Bank2 */
  341. #define EBC0_BNCR_NAND_FLASH_CS2 \
  342. EBC0_BNCR_BAS_ENCODE(0x94000000) | \
  343. EBC0_BNCR_BS_1MB | \
  344. EBC0_BNCR_BU_RW | \
  345. EBC0_BNCR_BW_32BIT
  346. /* NAND1 - Bank3 */
  347. #define EBC0_BNCR_NAND_FLASH_CS3 \
  348. EBC0_BNCR_BAS_ENCODE(0x94000000) | \
  349. EBC0_BNCR_BS_1MB | \
  350. EBC0_BNCR_BU_RW | \
  351. EBC0_BNCR_BW_32BIT
  352. int board_early_init_f(void)
  353. {
  354. ext_bus_cntlr_init();
  355. /*--------------------------------------------------------------------
  356. * Setup the interrupt controller polarities, triggers, etc.
  357. *-------------------------------------------------------------------*/
  358. mtdcr(UIC0SR, 0xffffffff); /* clear all */
  359. mtdcr(UIC0ER, 0x00000000); /* disable all */
  360. mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
  361. mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
  362. mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
  363. mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
  364. mtdcr(UIC0SR, 0xffffffff); /* clear all */
  365. mtdcr(UIC1SR, 0xffffffff); /* clear all */
  366. mtdcr(UIC1ER, 0x00000000); /* disable all */
  367. mtdcr(UIC1CR, 0x00000000); /* all non-critical */
  368. mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
  369. mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
  370. mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
  371. mtdcr(UIC1SR, 0xffffffff); /* clear all */
  372. /*--------------------------------------------------------------------
  373. * Setup the GPIO pins
  374. *-------------------------------------------------------------------*/
  375. out32(GPIO0_OSRL, 0x00000400);
  376. out32(GPIO0_OSRH, 0x00000000);
  377. out32(GPIO0_TSRL, 0x00000400);
  378. out32(GPIO0_TSRH, 0x00000000);
  379. out32(GPIO0_ISR1L, 0x00000000);
  380. out32(GPIO0_ISR1H, 0x00000000);
  381. out32(GPIO0_ISR2L, 0x00000000);
  382. out32(GPIO0_ISR2H, 0x00000000);
  383. out32(GPIO0_ISR3L, 0x00000000);
  384. out32(GPIO0_ISR3H, 0x00000000);
  385. out32(GPIO1_OSRL, 0x0C380000);
  386. out32(GPIO1_OSRH, 0x00000000);
  387. out32(GPIO1_TSRL, 0x0C380000);
  388. out32(GPIO1_TSRH, 0x00000000);
  389. out32(GPIO1_ISR1L, 0x0FC30000);
  390. out32(GPIO1_ISR1H, 0x00000000);
  391. out32(GPIO1_ISR2L, 0x0C010000);
  392. out32(GPIO1_ISR2H, 0x00000000);
  393. out32(GPIO1_ISR3L, 0x01400000);
  394. out32(GPIO1_ISR3H, 0x00000000);
  395. configure_ppc440ep_pins();
  396. return 0;
  397. }
  398. int checkboard(void)
  399. {
  400. char buf[64];
  401. int i = getenv_f("serial#", buf, sizeof(buf));
  402. printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
  403. if (i > 0) {
  404. puts(", serial# ");
  405. puts(buf);
  406. }
  407. putc('\n');
  408. return (0);
  409. }
  410. int dram_init(void)
  411. {
  412. gd->ram_size = spd_sdram();
  413. return 0;
  414. }
  415. /*----------------------------------------------------------------------------+
  416. | is_powerpc440ep_pass1.
  417. +----------------------------------------------------------------------------*/
  418. int is_powerpc440ep_pass1(void)
  419. {
  420. unsigned long pvr;
  421. pvr = get_pvr();
  422. if (pvr == PVR_POWERPC_440EP_PASS1)
  423. return true;
  424. else if (pvr == PVR_POWERPC_440EP_PASS2)
  425. return false;
  426. else {
  427. printf("brdutil error 3\n");
  428. for (;;)
  429. ;
  430. }
  431. return false;
  432. }
  433. /*----------------------------------------------------------------------------+
  434. | is_nand_selected.
  435. +----------------------------------------------------------------------------*/
  436. int is_nand_selected(void)
  437. {
  438. #ifdef CONFIG_BAMBOO_NAND
  439. return true;
  440. #else
  441. return false;
  442. #endif
  443. }
  444. /*----------------------------------------------------------------------------+
  445. | config_on_ebc_cs4_is_small_flash => from EPLD
  446. +----------------------------------------------------------------------------*/
  447. unsigned char config_on_ebc_cs4_is_small_flash(void)
  448. {
  449. /* Not implemented yet => returns constant value */
  450. return true;
  451. }
  452. /*----------------------------------------------------------------------------+
  453. | Ext_bus_cntlr_init.
  454. | Initialize the external bus controller
  455. +----------------------------------------------------------------------------*/
  456. void ext_bus_cntlr_init(void)
  457. {
  458. unsigned long sdr0_pstrp0, sdr0_sdstp1;
  459. unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
  460. int computed_boot_device = BOOT_DEVICE_UNKNOWN;
  461. unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
  462. unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
  463. unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
  464. unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
  465. unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
  466. /*-------------------------------------------------------------------------+
  467. |
  468. | PART 1 : Initialize EBC Bank 5
  469. | ==============================
  470. | Bank5 is always associated to the NVRAM/EPLD.
  471. | It has to be initialized prior to other banks settings computation since
  472. | some board registers values may be needed
  473. |
  474. +-------------------------------------------------------------------------*/
  475. /* NVRAM - FPGA */
  476. mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
  477. mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
  478. /*-------------------------------------------------------------------------+
  479. |
  480. | PART 2 : Determine which boot device was selected
  481. | =========================================
  482. |
  483. | Read Pin Strap Register in PPC440EP
  484. | In case of boot from IIC, read Serial Device Strap Register1
  485. |
  486. | Result can either be :
  487. | - Boot from EBC 8bits => SMALL FLASH
  488. | - Boot from EBC 16bits => Large Flash or SRAM
  489. | - Boot from NAND Flash
  490. | - Boot from PCI
  491. |
  492. +-------------------------------------------------------------------------*/
  493. /* Read Pin Strap Register in PPC440EP */
  494. mfsdr(SDR0_PINSTP, sdr0_pstrp0);
  495. bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
  496. /*-------------------------------------------------------------------------+
  497. | PPC440EP Pass1
  498. +-------------------------------------------------------------------------*/
  499. if (is_powerpc440ep_pass1() == true) {
  500. switch(bootstrap_settings) {
  501. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
  502. /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
  503. /* Boot from Small Flash */
  504. computed_boot_device = BOOT_FROM_SMALL_FLASH;
  505. break;
  506. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
  507. /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
  508. /* Boot from PCI */
  509. computed_boot_device = BOOT_FROM_PCI;
  510. break;
  511. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
  512. /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
  513. /* Boot from Nand Flash */
  514. computed_boot_device = BOOT_FROM_NAND_FLASH0;
  515. break;
  516. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
  517. /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
  518. /* Boot from Small Flash */
  519. computed_boot_device = BOOT_FROM_SMALL_FLASH;
  520. break;
  521. case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
  522. case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
  523. /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
  524. /* Read Serial Device Strap Register1 in PPC440EP */
  525. mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
  526. boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
  527. ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
  528. switch(boot_selection) {
  529. case SDR0_SDSTP1_BOOT_SEL_EBC:
  530. switch(ebc_boot_size) {
  531. case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
  532. computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
  533. break;
  534. case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
  535. computed_boot_device = BOOT_FROM_SMALL_FLASH;
  536. break;
  537. }
  538. break;
  539. case SDR0_SDSTP1_BOOT_SEL_PCI:
  540. computed_boot_device = BOOT_FROM_PCI;
  541. break;
  542. case SDR0_SDSTP1_BOOT_SEL_NDFC:
  543. computed_boot_device = BOOT_FROM_NAND_FLASH0;
  544. break;
  545. }
  546. break;
  547. }
  548. }
  549. /*-------------------------------------------------------------------------+
  550. | PPC440EP Pass2
  551. +-------------------------------------------------------------------------*/
  552. else {
  553. switch(bootstrap_settings) {
  554. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
  555. /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
  556. /* Boot from Small Flash */
  557. computed_boot_device = BOOT_FROM_SMALL_FLASH;
  558. break;
  559. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
  560. /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
  561. /* Boot from PCI */
  562. computed_boot_device = BOOT_FROM_PCI;
  563. break;
  564. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
  565. /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
  566. /* Boot from Nand Flash */
  567. computed_boot_device = BOOT_FROM_NAND_FLASH0;
  568. break;
  569. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
  570. /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
  571. /* Boot from Large Flash or SRAM */
  572. computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
  573. break;
  574. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
  575. /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
  576. /* Boot from Large Flash or SRAM */
  577. computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
  578. break;
  579. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
  580. /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
  581. /* Boot from PCI */
  582. computed_boot_device = BOOT_FROM_PCI;
  583. break;
  584. case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
  585. case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
  586. /* Default Strap Settings 5-7 */
  587. /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
  588. /* Read Serial Device Strap Register1 in PPC440EP */
  589. mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
  590. boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
  591. ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
  592. switch(boot_selection) {
  593. case SDR0_SDSTP1_BOOT_SEL_EBC:
  594. switch(ebc_boot_size) {
  595. case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
  596. computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
  597. break;
  598. case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
  599. computed_boot_device = BOOT_FROM_SMALL_FLASH;
  600. break;
  601. }
  602. break;
  603. case SDR0_SDSTP1_BOOT_SEL_PCI:
  604. computed_boot_device = BOOT_FROM_PCI;
  605. break;
  606. case SDR0_SDSTP1_BOOT_SEL_NDFC:
  607. computed_boot_device = BOOT_FROM_NAND_FLASH0;
  608. break;
  609. }
  610. break;
  611. }
  612. }
  613. /*-------------------------------------------------------------------------+
  614. |
  615. | PART 3 : Compute EBC settings depending on selected boot device
  616. | ====== ======================================================
  617. |
  618. | Resulting EBC init will be among following configurations :
  619. |
  620. | - Boot from EBC 8bits => boot from SMALL FLASH selected
  621. | EBC-CS0 = Small Flash
  622. | EBC-CS1,2,3 = NAND Flash or
  623. | Exp.Slot depending on Soft Config
  624. | EBC-CS4 = SRAM/Large Flash or
  625. | Large Flash/SRAM depending on jumpers
  626. | EBC-CS5 = NVRAM / EPLD
  627. |
  628. | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
  629. | EBC-CS0 = SRAM/Large Flash or
  630. | Large Flash/SRAM depending on jumpers
  631. | EBC-CS1,2,3 = NAND Flash or
  632. | Exp.Slot depending on Software Configuration
  633. | EBC-CS4 = Small Flash
  634. | EBC-CS5 = NVRAM / EPLD
  635. |
  636. | - Boot from NAND Flash
  637. | EBC-CS0 = NAND Flash0
  638. | EBC-CS1,2,3 = NAND Flash1
  639. | EBC-CS4 = SRAM/Large Flash or
  640. | Large Flash/SRAM depending on jumpers
  641. | EBC-CS5 = NVRAM / EPLD
  642. |
  643. | - Boot from PCI
  644. | EBC-CS0 = ...
  645. | EBC-CS1,2,3 = NAND Flash or
  646. | Exp.Slot depending on Software Configuration
  647. | EBC-CS4 = SRAM/Large Flash or
  648. | Large Flash/SRAM or
  649. | Small Flash depending on jumpers
  650. | EBC-CS5 = NVRAM / EPLD
  651. |
  652. +-------------------------------------------------------------------------*/
  653. switch(computed_boot_device) {
  654. /*------------------------------------------------------------------------- */
  655. case BOOT_FROM_SMALL_FLASH:
  656. /*------------------------------------------------------------------------- */
  657. ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
  658. ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
  659. if ((is_nand_selected()) == true) {
  660. /* NAND Flash */
  661. ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
  662. ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
  663. ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
  664. ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
  665. ebc0_cs3_bnap_value = 0;
  666. ebc0_cs3_bncr_value = 0;
  667. } else {
  668. /* Expansion Slot */
  669. ebc0_cs1_bnap_value = 0;
  670. ebc0_cs1_bncr_value = 0;
  671. ebc0_cs2_bnap_value = 0;
  672. ebc0_cs2_bncr_value = 0;
  673. ebc0_cs3_bnap_value = 0;
  674. ebc0_cs3_bncr_value = 0;
  675. }
  676. ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
  677. ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
  678. break;
  679. /*------------------------------------------------------------------------- */
  680. case BOOT_FROM_LARGE_FLASH_OR_SRAM:
  681. /*------------------------------------------------------------------------- */
  682. ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
  683. ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
  684. if ((is_nand_selected()) == true) {
  685. /* NAND Flash */
  686. ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
  687. ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
  688. ebc0_cs2_bnap_value = 0;
  689. ebc0_cs2_bncr_value = 0;
  690. ebc0_cs3_bnap_value = 0;
  691. ebc0_cs3_bncr_value = 0;
  692. } else {
  693. /* Expansion Slot */
  694. ebc0_cs1_bnap_value = 0;
  695. ebc0_cs1_bncr_value = 0;
  696. ebc0_cs2_bnap_value = 0;
  697. ebc0_cs2_bncr_value = 0;
  698. ebc0_cs3_bnap_value = 0;
  699. ebc0_cs3_bncr_value = 0;
  700. }
  701. ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
  702. ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
  703. break;
  704. /*------------------------------------------------------------------------- */
  705. case BOOT_FROM_NAND_FLASH0:
  706. /*------------------------------------------------------------------------- */
  707. ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
  708. ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
  709. ebc0_cs1_bnap_value = 0;
  710. ebc0_cs1_bncr_value = 0;
  711. ebc0_cs2_bnap_value = 0;
  712. ebc0_cs2_bncr_value = 0;
  713. ebc0_cs3_bnap_value = 0;
  714. ebc0_cs3_bncr_value = 0;
  715. /* Large Flash or SRAM */
  716. ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
  717. ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
  718. break;
  719. /*------------------------------------------------------------------------- */
  720. case BOOT_FROM_PCI:
  721. /*------------------------------------------------------------------------- */
  722. ebc0_cs0_bnap_value = 0;
  723. ebc0_cs0_bncr_value = 0;
  724. if ((is_nand_selected()) == true) {
  725. /* NAND Flash */
  726. ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
  727. ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
  728. ebc0_cs2_bnap_value = 0;
  729. ebc0_cs2_bncr_value = 0;
  730. ebc0_cs3_bnap_value = 0;
  731. ebc0_cs3_bncr_value = 0;
  732. } else {
  733. /* Expansion Slot */
  734. ebc0_cs1_bnap_value = 0;
  735. ebc0_cs1_bncr_value = 0;
  736. ebc0_cs2_bnap_value = 0;
  737. ebc0_cs2_bncr_value = 0;
  738. ebc0_cs3_bnap_value = 0;
  739. ebc0_cs3_bncr_value = 0;
  740. }
  741. if ((config_on_ebc_cs4_is_small_flash()) == true) {
  742. /* Small Flash */
  743. ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
  744. ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
  745. } else {
  746. /* Large Flash or SRAM */
  747. ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
  748. ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
  749. }
  750. break;
  751. /*------------------------------------------------------------------------- */
  752. case BOOT_DEVICE_UNKNOWN:
  753. /*------------------------------------------------------------------------- */
  754. /* Error */
  755. break;
  756. }
  757. /*-------------------------------------------------------------------------+
  758. | Initialize EBC CONFIG
  759. +-------------------------------------------------------------------------*/
  760. mtdcr(EBC0_CFGADDR, EBC0_CFG);
  761. mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN |
  762. EBC0_CFG_PTD_ENABLED |
  763. EBC0_CFG_RTC_2048PERCLK |
  764. EBC0_CFG_EMPL_LOW |
  765. EBC0_CFG_EMPH_LOW |
  766. EBC0_CFG_CSTC_DRIVEN |
  767. EBC0_CFG_BPF_ONEDW |
  768. EBC0_CFG_EMS_8BIT |
  769. EBC0_CFG_PME_DISABLED |
  770. EBC0_CFG_PMT_ENCODE(0) );
  771. /*-------------------------------------------------------------------------+
  772. | Initialize EBC Bank 0-4
  773. +-------------------------------------------------------------------------*/
  774. /* EBC Bank0 */
  775. mtebc(PB0AP, ebc0_cs0_bnap_value);
  776. mtebc(PB0CR, ebc0_cs0_bncr_value);
  777. /* EBC Bank1 */
  778. mtebc(PB1AP, ebc0_cs1_bnap_value);
  779. mtebc(PB1CR, ebc0_cs1_bncr_value);
  780. /* EBC Bank2 */
  781. mtebc(PB2AP, ebc0_cs2_bnap_value);
  782. mtebc(PB2CR, ebc0_cs2_bncr_value);
  783. /* EBC Bank3 */
  784. mtebc(PB3AP, ebc0_cs3_bnap_value);
  785. mtebc(PB3CR, ebc0_cs3_bncr_value);
  786. /* EBC Bank4 */
  787. mtebc(PB4AP, ebc0_cs4_bnap_value);
  788. mtebc(PB4CR, ebc0_cs4_bncr_value);
  789. return;
  790. }
  791. /*----------------------------------------------------------------------------+
  792. | get_uart_configuration.
  793. +----------------------------------------------------------------------------*/
  794. uart_config_nb_t get_uart_configuration(void)
  795. {
  796. return (L4);
  797. }
  798. /*----------------------------------------------------------------------------+
  799. | set_phy_configuration_through_fpga => to EPLD
  800. +----------------------------------------------------------------------------*/
  801. void set_phy_configuration_through_fpga(zmii_config_t config)
  802. {
  803. unsigned long fpga_selection_reg;
  804. fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
  805. switch(config)
  806. {
  807. case ZMII_CONFIGURATION_IS_MII:
  808. fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
  809. break;
  810. case ZMII_CONFIGURATION_IS_RMII:
  811. fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
  812. break;
  813. case ZMII_CONFIGURATION_IS_SMII:
  814. fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
  815. break;
  816. case ZMII_CONFIGURATION_UNKNOWN:
  817. default:
  818. break;
  819. }
  820. out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
  821. }
  822. /*----------------------------------------------------------------------------+
  823. | scp_selection_in_fpga.
  824. +----------------------------------------------------------------------------*/
  825. void scp_selection_in_fpga(void)
  826. {
  827. unsigned long fpga_selection_2_reg;
  828. fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
  829. fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
  830. out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  831. }
  832. /*----------------------------------------------------------------------------+
  833. | iic1_selection_in_fpga.
  834. +----------------------------------------------------------------------------*/
  835. void iic1_selection_in_fpga(void)
  836. {
  837. unsigned long fpga_selection_2_reg;
  838. fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
  839. fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
  840. out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  841. }
  842. /*----------------------------------------------------------------------------+
  843. | dma_a_b_selection_in_fpga.
  844. +----------------------------------------------------------------------------*/
  845. void dma_a_b_selection_in_fpga(void)
  846. {
  847. unsigned long fpga_selection_2_reg;
  848. fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
  849. out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  850. }
  851. /*----------------------------------------------------------------------------+
  852. | dma_a_b_unselect_in_fpga.
  853. +----------------------------------------------------------------------------*/
  854. void dma_a_b_unselect_in_fpga(void)
  855. {
  856. unsigned long fpga_selection_2_reg;
  857. fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
  858. out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  859. }
  860. /*----------------------------------------------------------------------------+
  861. | dma_c_d_selection_in_fpga.
  862. +----------------------------------------------------------------------------*/
  863. void dma_c_d_selection_in_fpga(void)
  864. {
  865. unsigned long fpga_selection_2_reg;
  866. fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
  867. out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  868. }
  869. /*----------------------------------------------------------------------------+
  870. | dma_c_d_unselect_in_fpga.
  871. +----------------------------------------------------------------------------*/
  872. void dma_c_d_unselect_in_fpga(void)
  873. {
  874. unsigned long fpga_selection_2_reg;
  875. fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
  876. out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  877. }
  878. /*----------------------------------------------------------------------------+
  879. | usb2_device_selection_in_fpga.
  880. +----------------------------------------------------------------------------*/
  881. void usb2_device_selection_in_fpga(void)
  882. {
  883. unsigned long fpga_selection_1_reg;
  884. fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
  885. out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
  886. }
  887. /*----------------------------------------------------------------------------+
  888. | usb2_device_reset_through_fpga.
  889. +----------------------------------------------------------------------------*/
  890. void usb2_device_reset_through_fpga(void)
  891. {
  892. /* Perform soft Reset pulse */
  893. unsigned long fpga_reset_reg;
  894. int i;
  895. fpga_reset_reg = in8(FPGA_RESET_REG);
  896. out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
  897. for (i=0; i<500; i++)
  898. udelay(1000);
  899. out8(FPGA_RESET_REG,fpga_reset_reg);
  900. }
  901. /*----------------------------------------------------------------------------+
  902. | usb2_host_selection_in_fpga.
  903. +----------------------------------------------------------------------------*/
  904. void usb2_host_selection_in_fpga(void)
  905. {
  906. unsigned long fpga_selection_1_reg;
  907. fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
  908. out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
  909. }
  910. /*----------------------------------------------------------------------------+
  911. | ndfc_selection_in_fpga.
  912. +----------------------------------------------------------------------------*/
  913. void ndfc_selection_in_fpga(void)
  914. {
  915. unsigned long fpga_selection_1_reg;
  916. fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
  917. fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
  918. fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
  919. out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
  920. }
  921. /*----------------------------------------------------------------------------+
  922. | uart_selection_in_fpga.
  923. +----------------------------------------------------------------------------*/
  924. void uart_selection_in_fpga(uart_config_nb_t uart_config)
  925. {
  926. /* FPGA register */
  927. unsigned char fpga_selection_3_reg;
  928. /* Read FPGA Reagister */
  929. fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
  930. switch (uart_config)
  931. {
  932. case L1:
  933. /* ----------------------------------------------------------------------- */
  934. /* L1 configuration: UART0 = 8 pins */
  935. /* ----------------------------------------------------------------------- */
  936. /* Configure FPGA */
  937. fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  938. fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
  939. out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
  940. break;
  941. case L2:
  942. /* ----------------------------------------------------------------------- */
  943. /* L2 configuration: UART0 = 4 pins */
  944. /* UART1 = 4 pins */
  945. /* ----------------------------------------------------------------------- */
  946. /* Configure FPGA */
  947. fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  948. fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
  949. out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
  950. break;
  951. case L3:
  952. /* ----------------------------------------------------------------------- */
  953. /* L3 configuration: UART0 = 4 pins */
  954. /* UART1 = 2 pins */
  955. /* UART2 = 2 pins */
  956. /* ----------------------------------------------------------------------- */
  957. /* Configure FPGA */
  958. fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  959. fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
  960. out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
  961. break;
  962. case L4:
  963. /* Configure FPGA */
  964. fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  965. fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
  966. out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
  967. break;
  968. default:
  969. /* Unsupported UART configuration number */
  970. for (;;)
  971. ;
  972. break;
  973. }
  974. }
  975. /*----------------------------------------------------------------------------+
  976. | init_default_gpio
  977. +----------------------------------------------------------------------------*/
  978. void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
  979. {
  980. int i;
  981. /* Init GPIO0 */
  982. for(i=0; i<GPIO_MAX; i++)
  983. {
  984. gpio_tab[GPIO0][i].add = GPIO0_BASE;
  985. gpio_tab[GPIO0][i].in_out = GPIO_DIS;
  986. gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
  987. }
  988. /* Init GPIO1 */
  989. for(i=0; i<GPIO_MAX; i++)
  990. {
  991. gpio_tab[GPIO1][i].add = GPIO1_BASE;
  992. gpio_tab[GPIO1][i].in_out = GPIO_DIS;
  993. gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
  994. }
  995. /* EBC_CS_N(5) - GPIO0_10 */
  996. gpio_tab[GPIO0][10].in_out = GPIO_OUT;
  997. gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
  998. /* EBC_CS_N(4) - GPIO0_9 */
  999. gpio_tab[GPIO0][9].in_out = GPIO_OUT;
  1000. gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
  1001. }
  1002. /*----------------------------------------------------------------------------+
  1003. | update_uart_ios
  1004. +------------------------------------------------------------------------------
  1005. |
  1006. | Set UART Configuration in PowerPC440EP
  1007. |
  1008. | +---------------------------------------------------------------------+
  1009. | | Configuartion | Connector | Nb of pins | Pins | Associated |
  1010. | | Number | Port Name | available | naming | CORE |
  1011. | +-----------------+---------------+------------+--------+-------------+
  1012. | | L1 | Port_A | 8 | UART | UART core 0 |
  1013. | +-----------------+---------------+------------+--------+-------------+
  1014. | | L2 | Port_A | 4 | UART1 | UART core 0 |
  1015. | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
  1016. | +-----------------+---------------+------------+--------+-------------+
  1017. | | L3 | Port_A | 4 | UART1 | UART core 0 |
  1018. | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
  1019. | | | Port_C | 2 | UART3 | UART core 2 |
  1020. | +-----------------+---------------+------------+--------+-------------+
  1021. | | | Port_A | 2 | UART1 | UART core 0 |
  1022. | | L4 | Port_B | 2 | UART2 | UART core 1 |
  1023. | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
  1024. | | | Port_D | 2 | UART4 | UART core 3 |
  1025. | +-----------------+---------------+------------+--------+-------------+
  1026. |
  1027. | Involved GPIOs
  1028. |
  1029. | +------------------------------------------------------------------------------+
  1030. | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
  1031. | +---------+------------------+-----+-----------------+-----+-------------+-----+
  1032. | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
  1033. | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
  1034. | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
  1035. | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
  1036. | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
  1037. | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
  1038. | +------------------------------------------------------------------------------+
  1039. |
  1040. |
  1041. +----------------------------------------------------------------------------*/
  1042. void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
  1043. {
  1044. switch (uart_config)
  1045. {
  1046. case L1:
  1047. /* ----------------------------------------------------------------------- */
  1048. /* L1 configuration: UART0 = 8 pins */
  1049. /* ----------------------------------------------------------------------- */
  1050. /* Update GPIO Configuration Table */
  1051. gpio_tab[GPIO1][2].in_out = GPIO_IN;
  1052. gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
  1053. gpio_tab[GPIO1][3].in_out = GPIO_IN;
  1054. gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
  1055. gpio_tab[GPIO1][4].in_out = GPIO_IN;
  1056. gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
  1057. gpio_tab[GPIO1][5].in_out = GPIO_OUT;
  1058. gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
  1059. gpio_tab[GPIO1][6].in_out = GPIO_OUT;
  1060. gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
  1061. gpio_tab[GPIO1][7].in_out = GPIO_IN;
  1062. gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
  1063. break;
  1064. case L2:
  1065. /* ----------------------------------------------------------------------- */
  1066. /* L2 configuration: UART0 = 4 pins */
  1067. /* UART1 = 4 pins */
  1068. /* ----------------------------------------------------------------------- */
  1069. /* Update GPIO Configuration Table */
  1070. gpio_tab[GPIO1][2].in_out = GPIO_IN;
  1071. gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
  1072. gpio_tab[GPIO1][3].in_out = GPIO_OUT;
  1073. gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
  1074. gpio_tab[GPIO1][4].in_out = GPIO_IN;
  1075. gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
  1076. gpio_tab[GPIO1][5].in_out = GPIO_OUT;
  1077. gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
  1078. gpio_tab[GPIO1][6].in_out = GPIO_OUT;
  1079. gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
  1080. gpio_tab[GPIO1][7].in_out = GPIO_IN;
  1081. gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
  1082. break;
  1083. case L3:
  1084. /* ----------------------------------------------------------------------- */
  1085. /* L3 configuration: UART0 = 4 pins */
  1086. /* UART1 = 2 pins */
  1087. /* UART2 = 2 pins */
  1088. /* ----------------------------------------------------------------------- */
  1089. /* Update GPIO Configuration Table */
  1090. gpio_tab[GPIO1][2].in_out = GPIO_OUT;
  1091. gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
  1092. gpio_tab[GPIO1][3].in_out = GPIO_IN;
  1093. gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
  1094. gpio_tab[GPIO1][4].in_out = GPIO_IN;
  1095. gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
  1096. gpio_tab[GPIO1][5].in_out = GPIO_OUT;
  1097. gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
  1098. gpio_tab[GPIO1][6].in_out = GPIO_OUT;
  1099. gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
  1100. gpio_tab[GPIO1][7].in_out = GPIO_IN;
  1101. gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
  1102. break;
  1103. case L4:
  1104. /* ----------------------------------------------------------------------- */
  1105. /* L4 configuration: UART0 = 2 pins */
  1106. /* UART1 = 2 pins */
  1107. /* UART2 = 2 pins */
  1108. /* UART3 = 2 pins */
  1109. /* ----------------------------------------------------------------------- */
  1110. /* Update GPIO Configuration Table */
  1111. gpio_tab[GPIO1][2].in_out = GPIO_OUT;
  1112. gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
  1113. gpio_tab[GPIO1][3].in_out = GPIO_IN;
  1114. gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
  1115. gpio_tab[GPIO1][4].in_out = GPIO_IN;
  1116. gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
  1117. gpio_tab[GPIO1][5].in_out = GPIO_OUT;
  1118. gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
  1119. gpio_tab[GPIO1][6].in_out = GPIO_OUT;
  1120. gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
  1121. gpio_tab[GPIO1][7].in_out = GPIO_IN;
  1122. gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
  1123. break;
  1124. default:
  1125. /* Unsupported UART configuration number */
  1126. printf("ERROR - Unsupported UART configuration number.\n\n");
  1127. for (;;)
  1128. ;
  1129. break;
  1130. }
  1131. /* Set input Selection Register on Alt_Receive for UART Input Core */
  1132. out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
  1133. out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
  1134. out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
  1135. }
  1136. /*----------------------------------------------------------------------------+
  1137. | update_ndfc_ios(void).
  1138. +----------------------------------------------------------------------------*/
  1139. void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1140. {
  1141. /* Update GPIO Configuration Table */
  1142. gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
  1143. gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
  1144. gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
  1145. gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
  1146. #if 0
  1147. gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
  1148. gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
  1149. #endif
  1150. }
  1151. /*----------------------------------------------------------------------------+
  1152. | update_zii_ios(void).
  1153. +----------------------------------------------------------------------------*/
  1154. void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1155. {
  1156. /* Update GPIO Configuration Table */
  1157. gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
  1158. gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
  1159. gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
  1160. gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
  1161. gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
  1162. gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
  1163. gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
  1164. gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
  1165. gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
  1166. gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
  1167. gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
  1168. gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
  1169. gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
  1170. gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
  1171. gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
  1172. gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
  1173. gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
  1174. gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
  1175. gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
  1176. gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
  1177. gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
  1178. gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
  1179. gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
  1180. gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
  1181. gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
  1182. gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
  1183. gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
  1184. gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
  1185. }
  1186. /*----------------------------------------------------------------------------+
  1187. | update_uic_0_3_irq_ios().
  1188. +----------------------------------------------------------------------------*/
  1189. void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1190. {
  1191. gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
  1192. gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
  1193. gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
  1194. gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
  1195. gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
  1196. gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
  1197. gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
  1198. gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
  1199. }
  1200. /*----------------------------------------------------------------------------+
  1201. | update_uic_4_9_irq_ios().
  1202. +----------------------------------------------------------------------------*/
  1203. void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1204. {
  1205. gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
  1206. gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
  1207. gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
  1208. gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
  1209. gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
  1210. gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
  1211. gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
  1212. gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
  1213. gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
  1214. gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
  1215. }
  1216. /*----------------------------------------------------------------------------+
  1217. | update_dma_a_b_ios().
  1218. +----------------------------------------------------------------------------*/
  1219. void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1220. {
  1221. gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
  1222. gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
  1223. gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
  1224. gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
  1225. gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
  1226. gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
  1227. gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
  1228. gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
  1229. gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
  1230. gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
  1231. }
  1232. /*----------------------------------------------------------------------------+
  1233. | update_dma_c_d_ios().
  1234. +----------------------------------------------------------------------------*/
  1235. void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1236. {
  1237. gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
  1238. gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
  1239. gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
  1240. gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
  1241. gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
  1242. gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
  1243. gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
  1244. gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
  1245. gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
  1246. gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
  1247. gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
  1248. gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
  1249. }
  1250. /*----------------------------------------------------------------------------+
  1251. | update_ebc_master_ios().
  1252. +----------------------------------------------------------------------------*/
  1253. void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1254. {
  1255. gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
  1256. gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
  1257. gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
  1258. gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
  1259. gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
  1260. gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
  1261. gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
  1262. gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
  1263. }
  1264. /*----------------------------------------------------------------------------+
  1265. | update_usb2_device_ios().
  1266. +----------------------------------------------------------------------------*/
  1267. void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1268. {
  1269. gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
  1270. gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
  1271. gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
  1272. gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
  1273. gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
  1274. gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
  1275. gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
  1276. gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
  1277. gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
  1278. gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
  1279. gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
  1280. gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
  1281. gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
  1282. gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
  1283. gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
  1284. gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
  1285. }
  1286. /*----------------------------------------------------------------------------+
  1287. | update_pci_patch_ios().
  1288. +----------------------------------------------------------------------------*/
  1289. void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1290. {
  1291. gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
  1292. gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
  1293. }
  1294. /*----------------------------------------------------------------------------+
  1295. | set_chip_gpio_configuration(unsigned char gpio_core,
  1296. | gpio_param_s (*gpio_tab)[GPIO_MAX])
  1297. | Put the core impacted by clock modification and sharing in reset.
  1298. | Config the select registers to resolve the sharing depending of the config.
  1299. | Configure the GPIO registers.
  1300. |
  1301. +----------------------------------------------------------------------------*/
  1302. void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
  1303. {
  1304. unsigned char i=0, j=0, reg_offset = 0;
  1305. unsigned long gpio_reg, gpio_core_add;
  1306. /* GPIO config of the GPIOs 0 to 31 */
  1307. for (i=0; i<GPIO_MAX; i++, j++)
  1308. {
  1309. if (i == GPIO_MAX/2)
  1310. {
  1311. reg_offset = 4;
  1312. j = i-16;
  1313. }
  1314. gpio_core_add = gpio_tab[gpio_core][i].add;
  1315. if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
  1316. (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
  1317. {
  1318. switch (gpio_tab[gpio_core][i].alt_nb)
  1319. {
  1320. case GPIO_SEL:
  1321. break;
  1322. case GPIO_ALT1:
  1323. gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1324. gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
  1325. out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
  1326. break;
  1327. case GPIO_ALT2:
  1328. gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1329. gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
  1330. out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
  1331. break;
  1332. case GPIO_ALT3:
  1333. gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1334. gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
  1335. out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
  1336. break;
  1337. }
  1338. }
  1339. if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
  1340. (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
  1341. {
  1342. switch (gpio_tab[gpio_core][i].alt_nb)
  1343. {
  1344. case GPIO_SEL:
  1345. break;
  1346. case GPIO_ALT1:
  1347. gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1348. gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
  1349. out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
  1350. gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1351. gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
  1352. out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
  1353. break;
  1354. case GPIO_ALT2:
  1355. gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1356. gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
  1357. out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
  1358. gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1359. gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
  1360. out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
  1361. break;
  1362. case GPIO_ALT3:
  1363. gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1364. gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
  1365. out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
  1366. gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1367. gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
  1368. out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
  1369. break;
  1370. }
  1371. }
  1372. }
  1373. }
  1374. /*----------------------------------------------------------------------------+
  1375. | force_bup_core_selection.
  1376. +----------------------------------------------------------------------------*/
  1377. void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
  1378. {
  1379. /* Pointer invalid */
  1380. if (core_select_P == NULL)
  1381. {
  1382. printf("Configuration invalid pointer 1\n");
  1383. for (;;)
  1384. ;
  1385. }
  1386. /* L4 Selection */
  1387. *(core_select_P+UART_CORE0) = CORE_SELECTED;
  1388. *(core_select_P+UART_CORE1) = CORE_SELECTED;
  1389. *(core_select_P+UART_CORE2) = CORE_SELECTED;
  1390. *(core_select_P+UART_CORE3) = CORE_SELECTED;
  1391. /* RMII Selection */
  1392. *(core_select_P+RMII_SEL) = CORE_SELECTED;
  1393. /* External Interrupt 0-9 selection */
  1394. *(core_select_P+UIC_0_3) = CORE_SELECTED;
  1395. *(core_select_P+UIC_4_9) = CORE_SELECTED;
  1396. *(core_select_P+SCP_CORE) = CORE_SELECTED;
  1397. *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
  1398. *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
  1399. *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
  1400. if (is_nand_selected()) {
  1401. *(core_select_P+NAND_FLASH) = CORE_SELECTED;
  1402. }
  1403. *config_val_P = CONFIG_IS_VALID;
  1404. }
  1405. /*----------------------------------------------------------------------------+
  1406. | configure_ppc440ep_pins.
  1407. +----------------------------------------------------------------------------*/
  1408. void configure_ppc440ep_pins(void)
  1409. {
  1410. uart_config_nb_t uart_configuration;
  1411. config_validity_t config_val = CONFIG_IS_INVALID;
  1412. /* Create Core Selection Table */
  1413. core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
  1414. {
  1415. CORE_NOT_SELECTED, /* IIC_CORE, */
  1416. CORE_NOT_SELECTED, /* SPC_CORE, */
  1417. CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
  1418. CORE_NOT_SELECTED, /* UIC_4_9, */
  1419. CORE_NOT_SELECTED, /* USB2_HOST, */
  1420. CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
  1421. CORE_NOT_SELECTED, /* USB2_DEVICE, */
  1422. CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
  1423. CORE_NOT_SELECTED, /* USB1_DEVICE, */
  1424. CORE_NOT_SELECTED, /* EBC_MASTER, */
  1425. CORE_NOT_SELECTED, /* NAND_FLASH, */
  1426. CORE_NOT_SELECTED, /* UART_CORE0, */
  1427. CORE_NOT_SELECTED, /* UART_CORE1, */
  1428. CORE_NOT_SELECTED, /* UART_CORE2, */
  1429. CORE_NOT_SELECTED, /* UART_CORE3, */
  1430. CORE_NOT_SELECTED, /* MII_SEL, */
  1431. CORE_NOT_SELECTED, /* RMII_SEL, */
  1432. CORE_NOT_SELECTED, /* SMII_SEL, */
  1433. CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
  1434. CORE_NOT_SELECTED, /* UIC_0_3 */
  1435. CORE_NOT_SELECTED, /* USB1_HOST */
  1436. CORE_NOT_SELECTED /* PCI_PATCH */
  1437. };
  1438. gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
  1439. /* Table Default Initialisation + FPGA Access */
  1440. init_default_gpio(gpio_tab);
  1441. set_chip_gpio_configuration(GPIO0, gpio_tab);
  1442. set_chip_gpio_configuration(GPIO1, gpio_tab);
  1443. /* Update Table */
  1444. force_bup_core_selection(ppc440ep_core_selection, &config_val);
  1445. #if 0 /* test-only */
  1446. /* If we are running PIBS 1, force known configuration */
  1447. update_core_selection_table(ppc440ep_core_selection, &config_val);
  1448. #endif
  1449. /*----------------------------------------------------------------------------+
  1450. | SDR + ios table update + fpga initialization
  1451. +----------------------------------------------------------------------------*/
  1452. unsigned long sdr0_pfc1 = 0;
  1453. unsigned long sdr0_usb0 = 0;
  1454. unsigned long sdr0_mfr = 0;
  1455. /* PCI Always selected */
  1456. /* I2C Selection */
  1457. if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
  1458. {
  1459. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
  1460. iic1_selection_in_fpga();
  1461. }
  1462. /* SCP Selection */
  1463. if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
  1464. {
  1465. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
  1466. scp_selection_in_fpga();
  1467. }
  1468. /* UIC 0:3 Selection */
  1469. if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
  1470. {
  1471. update_uic_0_3_irq_ios(gpio_tab);
  1472. dma_a_b_unselect_in_fpga();
  1473. }
  1474. /* UIC 4:9 Selection */
  1475. if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
  1476. {
  1477. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
  1478. update_uic_4_9_irq_ios(gpio_tab);
  1479. }
  1480. /* DMA AB Selection */
  1481. if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
  1482. {
  1483. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
  1484. update_dma_a_b_ios(gpio_tab);
  1485. dma_a_b_selection_in_fpga();
  1486. }
  1487. /* DMA CD Selection */
  1488. if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
  1489. {
  1490. update_dma_c_d_ios(gpio_tab);
  1491. dma_c_d_selection_in_fpga();
  1492. }
  1493. /* EBC Master Selection */
  1494. if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
  1495. {
  1496. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
  1497. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
  1498. update_ebc_master_ios(gpio_tab);
  1499. }
  1500. /* PCI Patch Enable */
  1501. if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
  1502. {
  1503. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
  1504. update_pci_patch_ios(gpio_tab);
  1505. }
  1506. /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
  1507. if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
  1508. {
  1509. /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
  1510. printf("Invalid configuration => USB2 Host selected\n");
  1511. for (;;)
  1512. ;
  1513. /*usb2_host_selection_in_fpga(); */
  1514. }
  1515. /* USB2.0 Device Selection */
  1516. if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
  1517. {
  1518. update_usb2_device_ios(gpio_tab);
  1519. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
  1520. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
  1521. mfsdr(SDR0_USB0, sdr0_usb0);
  1522. sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
  1523. sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
  1524. mtsdr(SDR0_USB0, sdr0_usb0);
  1525. usb2_device_selection_in_fpga();
  1526. }
  1527. /* USB1.1 Device Selection */
  1528. if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
  1529. {
  1530. mfsdr(SDR0_USB0, sdr0_usb0);
  1531. sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
  1532. sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
  1533. mtsdr(SDR0_USB0, sdr0_usb0);
  1534. }
  1535. /* USB1.1 Host Selection */
  1536. if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
  1537. {
  1538. mfsdr(SDR0_USB0, sdr0_usb0);
  1539. sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
  1540. sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
  1541. mtsdr(SDR0_USB0, sdr0_usb0);
  1542. }
  1543. /* NAND Flash Selection */
  1544. if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
  1545. {
  1546. update_ndfc_ios(gpio_tab);
  1547. mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
  1548. SDR0_CUST0_NDFC_ENABLE |
  1549. SDR0_CUST0_NDFC_BW_8_BIT |
  1550. SDR0_CUST0_NDFC_ARE_MASK |
  1551. SDR0_CUST0_CHIPSELGAT_EN1 |
  1552. SDR0_CUST0_CHIPSELGAT_EN2);
  1553. ndfc_selection_in_fpga();
  1554. }
  1555. else
  1556. {
  1557. /* Set Mux on EMAC */
  1558. mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
  1559. }
  1560. /* MII Selection */
  1561. if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
  1562. {
  1563. update_zii_ios(gpio_tab);
  1564. mfsdr(SDR0_MFR, sdr0_mfr);
  1565. sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
  1566. mtsdr(SDR0_MFR, sdr0_mfr);
  1567. set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
  1568. }
  1569. /* RMII Selection */
  1570. if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
  1571. {
  1572. update_zii_ios(gpio_tab);
  1573. mfsdr(SDR0_MFR, sdr0_mfr);
  1574. sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
  1575. mtsdr(SDR0_MFR, sdr0_mfr);
  1576. set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
  1577. }
  1578. /* SMII Selection */
  1579. if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
  1580. {
  1581. update_zii_ios(gpio_tab);
  1582. mfsdr(SDR0_MFR, sdr0_mfr);
  1583. sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
  1584. mtsdr(SDR0_MFR, sdr0_mfr);
  1585. set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
  1586. }
  1587. /* UART Selection */
  1588. uart_configuration = get_uart_configuration();
  1589. switch (uart_configuration)
  1590. {
  1591. case L1: /* L1 Selection */
  1592. /* UART0 8 pins Only */
  1593. /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
  1594. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
  1595. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
  1596. break;
  1597. case L2: /* L2 Selection */
  1598. /* UART0 and UART1 4 pins */
  1599. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1600. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
  1601. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1602. break;
  1603. case L3: /* L3 Selection */
  1604. /* UART0 4 pins, UART1 and UART2 2 pins */
  1605. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1606. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
  1607. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1608. break;
  1609. case L4: /* L4 Selection */
  1610. /* UART0, UART1, UART2 and UART3 2 pins */
  1611. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
  1612. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
  1613. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1614. break;
  1615. }
  1616. update_uart_ios(uart_configuration, gpio_tab);
  1617. /* UART Selection in all cases */
  1618. uart_selection_in_fpga(uart_configuration);
  1619. /* Packet Reject Function Available */
  1620. if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
  1621. {
  1622. /* Set UPR Bit in SDR0_PFC1 Register */
  1623. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
  1624. }
  1625. /* Packet Reject Function Enable */
  1626. if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
  1627. {
  1628. mfsdr(SDR0_MFR, sdr0_mfr);
  1629. sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;
  1630. mtsdr(SDR0_MFR, sdr0_mfr);
  1631. }
  1632. /* Perform effective access to hardware */
  1633. mtsdr(SDR0_PFC1, sdr0_pfc1);
  1634. set_chip_gpio_configuration(GPIO0, gpio_tab);
  1635. set_chip_gpio_configuration(GPIO1, gpio_tab);
  1636. /* USB2.0 Device Reset must be done after GPIO setting */
  1637. if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
  1638. usb2_device_reset_through_fpga();
  1639. }