bx50v3.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Timesys Corporation
  4. * Copyright 2015 General Electric Company
  5. * Copyright 2012 Freescale Semiconductor, Inc.
  6. */
  7. #include <image.h>
  8. #include <init.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <env.h>
  14. #include <asm/global_data.h>
  15. #include <linux/delay.h>
  16. #include <linux/errno.h>
  17. #include <linux/libfdt.h>
  18. #include <asm/gpio.h>
  19. #include <asm/mach-imx/iomux-v3.h>
  20. #include <asm/mach-imx/boot_mode.h>
  21. #include <asm/mach-imx/video.h>
  22. #include <mmc.h>
  23. #include <fsl_esdhc_imx.h>
  24. #include <miiphy.h>
  25. #include <net.h>
  26. #include <netdev.h>
  27. #include <asm/arch/mxc_hdmi.h>
  28. #include <asm/arch/crm_regs.h>
  29. #include <asm/io.h>
  30. #include <asm/arch/sys_proto.h>
  31. #include <power/regulator.h>
  32. #include <power/da9063_pmic.h>
  33. #include <power/pmic.h>
  34. #include <input.h>
  35. #include <pwm.h>
  36. #include <version.h>
  37. #include <stdlib.h>
  38. #include <dm/root.h>
  39. #include "../common/ge_rtc.h"
  40. #include "../common/vpd_reader.h"
  41. #include "../../../drivers/net/e1000.h"
  42. #include <pci.h>
  43. #include <panel.h>
  44. DECLARE_GLOBAL_DATA_PTR;
  45. #define VPD_PRODUCT_B850 1
  46. #define VPD_PRODUCT_B650 2
  47. #define VPD_PRODUCT_B450 3
  48. #define AR8033_DBG_REG_ADDR 0x1d
  49. #define AR8033_DBG_REG_DATA 0x1e
  50. #define AR8033_SERDES_REG 0x5
  51. static int productid; /* Default to generic. */
  52. static struct vpd_cache vpd;
  53. #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  54. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  55. PAD_CTL_HYS)
  56. int dram_init(void)
  57. {
  58. gd->ram_size = imx_ddr_size();
  59. return 0;
  60. }
  61. int board_phy_config(struct phy_device *phydev)
  62. {
  63. /*
  64. * Set reserved bits to avoid board specific voltage peak issue. The
  65. * value is a magic number provided directly by Qualcomm. Note, that
  66. * PHY driver will take control of BIT(8) in this register to control
  67. * TX clock delay, so we do not initialize that bit here.
  68. */
  69. phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_ADDR, AR8033_SERDES_REG);
  70. phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_DATA, 0x3c47);
  71. if (phydev->drv->config)
  72. phydev->drv->config(phydev);
  73. return 0;
  74. }
  75. #if defined(CONFIG_VIDEO_IPUV3)
  76. static void do_enable_backlight(struct display_info_t const *dev)
  77. {
  78. struct udevice *panel;
  79. int ret;
  80. ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
  81. if (ret) {
  82. printf("Could not find panel: %d\n", ret);
  83. return;
  84. }
  85. panel_set_backlight(panel, 100);
  86. panel_enable_backlight(panel);
  87. }
  88. static void do_enable_hdmi(struct display_info_t const *dev)
  89. {
  90. imx_enable_hdmi_phy();
  91. }
  92. static int is_b850v3(void)
  93. {
  94. return productid == VPD_PRODUCT_B850;
  95. }
  96. static int detect_lcd(struct display_info_t const *dev)
  97. {
  98. return !is_b850v3();
  99. }
  100. struct display_info_t const displays[] = {{
  101. .bus = -1,
  102. .addr = -1,
  103. .pixfmt = IPU_PIX_FMT_RGB24,
  104. .detect = detect_lcd,
  105. .enable = do_enable_backlight,
  106. .mode = {
  107. .name = "G121X1-L03",
  108. .refresh = 60,
  109. .xres = 1024,
  110. .yres = 768,
  111. .pixclock = 15385,
  112. .left_margin = 20,
  113. .right_margin = 300,
  114. .upper_margin = 30,
  115. .lower_margin = 8,
  116. .hsync_len = 1,
  117. .vsync_len = 1,
  118. .sync = FB_SYNC_EXT,
  119. .vmode = FB_VMODE_NONINTERLACED
  120. } }, {
  121. .bus = -1,
  122. .addr = 3,
  123. .pixfmt = IPU_PIX_FMT_RGB24,
  124. .detect = detect_hdmi,
  125. .enable = do_enable_hdmi,
  126. .mode = {
  127. .name = "HDMI",
  128. .refresh = 60,
  129. .xres = 1024,
  130. .yres = 768,
  131. .pixclock = 15385,
  132. .left_margin = 220,
  133. .right_margin = 40,
  134. .upper_margin = 21,
  135. .lower_margin = 7,
  136. .hsync_len = 60,
  137. .vsync_len = 10,
  138. .sync = FB_SYNC_EXT,
  139. .vmode = FB_VMODE_NONINTERLACED
  140. } } };
  141. size_t display_count = ARRAY_SIZE(displays);
  142. static void enable_videopll(void)
  143. {
  144. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  145. s32 timeout = 100000;
  146. setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
  147. /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2)
  148. * |
  149. * PLL5
  150. * |
  151. * CS2CDR[LDB_DI0_CLK_SEL]
  152. * |
  153. * +----> LDB_DI0_SERIAL_CLK_ROOT
  154. * |
  155. * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz
  156. */
  157. clrsetbits_le32(&ccm->analog_pll_video,
  158. BM_ANADIG_PLL_VIDEO_DIV_SELECT |
  159. BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
  160. BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
  161. BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
  162. writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
  163. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
  164. clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
  165. while (timeout--)
  166. if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
  167. break;
  168. if (timeout < 0)
  169. printf("Warning: video pll lock timeout!\n");
  170. clrsetbits_le32(&ccm->analog_pll_video,
  171. BM_ANADIG_PLL_VIDEO_BYPASS,
  172. BM_ANADIG_PLL_VIDEO_ENABLE);
  173. }
  174. static void setup_display_b850v3(void)
  175. {
  176. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  177. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  178. enable_videopll();
  179. /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
  180. setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  181. imx_setup_hdmi();
  182. /* Set LDB_DI0 as clock source for IPU_DI0 */
  183. clrsetbits_le32(&mxc_ccm->chsccdr,
  184. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
  185. (CHSCCDR_CLK_SEL_LDB_DI0 <<
  186. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
  187. /* Turn on IPU LDB DI0 clocks */
  188. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  189. enable_ipu_clock();
  190. writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
  191. IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
  192. IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  193. IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
  194. IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
  195. IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  196. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
  197. IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
  198. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
  199. IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
  200. &iomux->gpr[2]);
  201. clrbits_le32(&iomux->gpr[3],
  202. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  203. IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
  204. IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
  205. }
  206. static void setup_display_bx50v3(void)
  207. {
  208. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  209. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  210. enable_videopll();
  211. /* When a reset/reboot is performed the display power needs to be turned
  212. * off for atleast 500ms. The boot time is ~300ms, we need to wait for
  213. * an additional 200ms here. Unfortunately we use external PMIC for
  214. * doing the reset, so can not differentiate between POR vs soft reset
  215. */
  216. mdelay(200);
  217. /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
  218. setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  219. /* Set LDB_DI0 as clock source for IPU_DI0 */
  220. clrsetbits_le32(&mxc_ccm->chsccdr,
  221. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
  222. (CHSCCDR_CLK_SEL_LDB_DI0 <<
  223. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
  224. /* Turn on IPU LDB DI0 clocks */
  225. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  226. enable_ipu_clock();
  227. writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
  228. IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  229. IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  230. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
  231. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
  232. &iomux->gpr[2]);
  233. clrsetbits_le32(&iomux->gpr[3],
  234. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
  235. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  236. IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
  237. }
  238. #endif /* CONFIG_VIDEO_IPUV3 */
  239. /*
  240. * Do not overwrite the console
  241. * Use always serial for U-Boot console
  242. */
  243. int overwrite_console(void)
  244. {
  245. return 1;
  246. }
  247. #define VPD_TYPE_INVALID 0x00
  248. #define VPD_BLOCK_NETWORK 0x20
  249. #define VPD_BLOCK_HWID 0x44
  250. #define VPD_HAS_MAC1 0x1
  251. #define VPD_HAS_MAC2 0x2
  252. #define VPD_MAC_ADDRESS_LENGTH 6
  253. struct vpd_cache {
  254. bool is_read;
  255. u8 product_id;
  256. u8 has;
  257. unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
  258. unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
  259. };
  260. /*
  261. * Extracts MAC and product information from the VPD.
  262. */
  263. static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
  264. size_t size, u8 const *data)
  265. {
  266. if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
  267. size >= 1) {
  268. vpd->product_id = data[0];
  269. } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
  270. type != VPD_TYPE_INVALID) {
  271. if (size >= 6) {
  272. vpd->has |= VPD_HAS_MAC1;
  273. memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
  274. }
  275. if (size >= 12) {
  276. vpd->has |= VPD_HAS_MAC2;
  277. memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
  278. }
  279. }
  280. return 0;
  281. }
  282. static void process_vpd(struct vpd_cache *vpd)
  283. {
  284. int fec_index = 0;
  285. int i210_index = -1;
  286. if (!vpd->is_read) {
  287. printf("VPD wasn't read");
  288. return;
  289. }
  290. if (vpd->has & VPD_HAS_MAC1)
  291. eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
  292. env_set("ethact", "eth0");
  293. switch (vpd->product_id) {
  294. case VPD_PRODUCT_B450:
  295. i210_index = 1;
  296. break;
  297. case VPD_PRODUCT_B650:
  298. i210_index = 1;
  299. break;
  300. case VPD_PRODUCT_B850:
  301. i210_index = 2;
  302. break;
  303. }
  304. if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
  305. eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
  306. }
  307. static iomux_v3_cfg_t const misc_pads[] = {
  308. MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  309. MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
  310. MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
  311. MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
  312. MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
  313. MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
  314. MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
  315. MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
  316. };
  317. #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
  318. #define PWGIN_IN IMX_GPIO_NR(4, 14)
  319. #define WIFI_EN IMX_GPIO_NR(6, 14)
  320. int board_early_init_f(void)
  321. {
  322. imx_iomux_v3_setup_multiple_pads(misc_pads,
  323. ARRAY_SIZE(misc_pads));
  324. #if defined(CONFIG_VIDEO_IPUV3)
  325. /* Set LDB clock to Video PLL */
  326. select_ldb_di_clock_source(MXC_PLL5_CLK);
  327. #endif
  328. return 0;
  329. }
  330. int board_init(void)
  331. {
  332. if (!read_i2c_vpd(&vpd, vpd_callback)) {
  333. int ret, rescan;
  334. vpd.is_read = true;
  335. productid = vpd.product_id;
  336. ret = fdtdec_resetup(&rescan);
  337. if (!ret && rescan) {
  338. dm_uninit();
  339. dm_init_and_scan(false);
  340. }
  341. }
  342. gpio_request(SUS_S3_OUT, "sus_s3_out");
  343. gpio_direction_output(SUS_S3_OUT, 1);
  344. gpio_request(PWGIN_IN, "pwgin_in");
  345. gpio_direction_input(PWGIN_IN);
  346. gpio_request(WIFI_EN, "wifi_en");
  347. gpio_direction_output(WIFI_EN, 1);
  348. #if defined(CONFIG_VIDEO_IPUV3)
  349. if (is_b850v3())
  350. setup_display_b850v3();
  351. else
  352. setup_display_bx50v3();
  353. #endif
  354. /* address of boot parameters */
  355. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  356. return 0;
  357. }
  358. #ifdef CONFIG_CMD_BMODE
  359. static const struct boot_mode board_boot_modes[] = {
  360. /* 4 bit bus width */
  361. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  362. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  363. {NULL, 0},
  364. };
  365. #endif
  366. /*
  367. * The SoM used by these boards has XTAL not connected despite datasheet
  368. * suggesting connecting unused XTAL pins to ground. Without explicitly
  369. * clearing the CRYSTAL bit the system runs unstable and sometimes reboots
  370. * unexpectedly.
  371. */
  372. static void pmic_crystal_fix(void)
  373. {
  374. struct udevice *pmic;
  375. static const uint EN_32K_CRYSTAL = (1 << 3);
  376. if (pmic_get("pmic@58", &pmic)) {
  377. puts("failed to get device for PMIC\n");
  378. return;
  379. }
  380. if (pmic_clrsetbits(pmic, DA9063_REG_EN_32K, EN_32K_CRYSTAL, 0) < 0) {
  381. puts("failed to clear CRYSTAL bit\n");
  382. return;
  383. }
  384. }
  385. void pmic_init(void)
  386. {
  387. struct udevice *reg;
  388. int ret, i;
  389. static const char * const bucks[] = {
  390. "bcore1",
  391. "bcore2",
  392. "bpro",
  393. "bmem",
  394. "bio",
  395. "bperi",
  396. };
  397. pmic_crystal_fix();
  398. for (i = 0; i < ARRAY_SIZE(bucks); i++) {
  399. ret = regulator_get_by_devname(bucks[i], &reg);
  400. if (reg < 0) {
  401. printf("%s(): Unable to get regulator %s: %d\n",
  402. __func__, bucks[i], ret);
  403. continue;
  404. }
  405. regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
  406. }
  407. }
  408. static void detect_boot_cause(void)
  409. {
  410. const char *cause = "POR";
  411. if (is_b850v3())
  412. if (!gpio_get_value(PWGIN_IN))
  413. cause = "PM_WDOG";
  414. env_set("bootcause", cause);
  415. }
  416. int board_late_init(void)
  417. {
  418. process_vpd(&vpd);
  419. #ifdef CONFIG_CMD_BMODE
  420. add_board_boot_modes(board_boot_modes);
  421. #endif
  422. if (is_b850v3())
  423. env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
  424. else
  425. env_set("videoargs", "video=LVDS-1:1024x768@65");
  426. detect_boot_cause();
  427. /* board specific pmic init */
  428. pmic_init();
  429. check_time();
  430. pci_init();
  431. return 0;
  432. }
  433. /*
  434. * Removes the 'eth[0-9]*addr' environment variable with the given index
  435. *
  436. * @param index [in] the index of the eth_device whose variable is to be removed
  437. */
  438. static void remove_ethaddr_env_var(int index)
  439. {
  440. char env_var_name[9];
  441. sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
  442. env_set(env_var_name, NULL);
  443. }
  444. int last_stage_init(void)
  445. {
  446. int i;
  447. /*
  448. * Remove first three ethaddr which may have been created by
  449. * function process_vpd().
  450. */
  451. for (i = 0; i < 3; ++i)
  452. remove_ethaddr_env_var(i);
  453. return 0;
  454. }
  455. int checkboard(void)
  456. {
  457. printf("BOARD: %s\n", CONFIG_BOARD_NAME);
  458. return 0;
  459. }
  460. #ifdef CONFIG_OF_BOARD_SETUP
  461. int ft_board_setup(void *blob, struct bd_info *bd)
  462. {
  463. char *rtc_status = env_get("rtc_status");
  464. fdt_setprop(blob, 0, "ge,boot-ver", version_string,
  465. strlen(version_string) + 1);
  466. fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
  467. strlen(rtc_status) + 1);
  468. return 0;
  469. }
  470. #endif
  471. int board_fit_config_name_match(const char *name)
  472. {
  473. const char *machine = name;
  474. if (!vpd.is_read)
  475. return strcmp(name, "imx6q-bx50v3");
  476. if (!strncmp(machine, "Boot ", 5))
  477. machine += 5;
  478. if (!strncmp(machine, "imx6q-", 6))
  479. machine += 6;
  480. switch (vpd.product_id) {
  481. case VPD_PRODUCT_B450:
  482. return strcasecmp(machine, "b450v3");
  483. case VPD_PRODUCT_B650:
  484. return strcasecmp(machine, "b650v3");
  485. case VPD_PRODUCT_B850:
  486. return strcasecmp(machine, "b850v3");
  487. default:
  488. return -1;
  489. }
  490. }
  491. int embedded_dtb_select(void)
  492. {
  493. vpd.is_read = false;
  494. return fdtdec_setup();
  495. }