Kconfig 10 KB

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  1. menu "RISC-V architecture"
  2. depends on RISCV
  3. config SYS_ARCH
  4. default "riscv"
  5. choice
  6. prompt "Target select"
  7. optional
  8. config TARGET_AX25_AE350
  9. bool "Support ax25-ae350"
  10. config TARGET_MICROCHIP_ICICLE
  11. bool "Support Microchip PolarFire-SoC Icicle Board"
  12. config TARGET_QEMU_VIRT
  13. bool "Support QEMU Virt Board"
  14. config TARGET_SIFIVE_UNLEASHED
  15. bool "Support SiFive Unleashed Board"
  16. config TARGET_SIFIVE_UNMATCHED
  17. bool "Support SiFive Unmatched Board"
  18. config TARGET_STARFIVE_VISIONFIVE2
  19. bool "Support StarFive VisionFive2 Board"
  20. config TARGET_STARFIVE_EVB
  21. bool "Support StarFive Evb Board"
  22. config TARGET_SIPEED_MAIX
  23. bool "Support Sipeed Maix Board"
  24. config TARGET_OPENPITON_RISCV64
  25. bool "Support RISC-V cores on OpenPiton SoC"
  26. endchoice
  27. config SYS_ICACHE_OFF
  28. bool "Do not enable icache"
  29. default n
  30. help
  31. Do not enable instruction cache in U-Boot.
  32. config SPL_SYS_ICACHE_OFF
  33. bool "Do not enable icache in SPL"
  34. depends on SPL
  35. default SYS_ICACHE_OFF
  36. help
  37. Do not enable instruction cache in SPL.
  38. config SYS_DCACHE_OFF
  39. bool "Do not enable dcache"
  40. default n
  41. help
  42. Do not enable data cache in U-Boot.
  43. config SPL_SYS_DCACHE_OFF
  44. bool "Do not enable dcache in SPL"
  45. depends on SPL
  46. default SYS_DCACHE_OFF
  47. help
  48. Do not enable data cache in SPL.
  49. # board-specific options below
  50. source "board/AndesTech/ax25-ae350/Kconfig"
  51. source "board/emulation/qemu-riscv/Kconfig"
  52. source "board/microchip/mpfs_icicle/Kconfig"
  53. source "board/sifive/unleashed/Kconfig"
  54. source "board/sifive/unmatched/Kconfig"
  55. source "board/openpiton/riscv64/Kconfig"
  56. source "board/sipeed/maix/Kconfig"
  57. source "board/starfive/visionfive2/Kconfig"
  58. source "board/starfive/evb/Kconfig"
  59. # platform-specific options below
  60. source "arch/riscv/cpu/ax25/Kconfig"
  61. source "arch/riscv/cpu/fu540/Kconfig"
  62. source "arch/riscv/cpu/fu740/Kconfig"
  63. source "arch/riscv/cpu/generic/Kconfig"
  64. source "arch/riscv/cpu/jh7110/Kconfig"
  65. # architecture-specific options below
  66. choice
  67. prompt "Base ISA"
  68. default ARCH_RV32I
  69. config ARCH_RV32I
  70. bool "RV32I"
  71. select 32BIT
  72. help
  73. Choose this option to target the RV32I base integer instruction set.
  74. config ARCH_RV64I
  75. bool "RV64I"
  76. select 64BIT
  77. select PHYS_64BIT
  78. help
  79. Choose this option to target the RV64I base integer instruction set.
  80. endchoice
  81. choice
  82. prompt "Code Model"
  83. default CMODEL_MEDLOW
  84. config CMODEL_MEDLOW
  85. bool "medium low code model"
  86. help
  87. U-Boot and its statically defined symbols must lie within a single 2 GiB
  88. address range and must lie between absolute addresses -2 GiB and +2 GiB.
  89. config CMODEL_MEDANY
  90. bool "medium any code model"
  91. help
  92. U-Boot and its statically defined symbols must be within any single 2 GiB
  93. address range.
  94. endchoice
  95. choice
  96. prompt "Run Mode"
  97. default RISCV_MMODE
  98. config RISCV_MMODE
  99. bool "Machine"
  100. help
  101. Choose this option to build U-Boot for RISC-V M-Mode.
  102. config RISCV_SMODE
  103. bool "Supervisor"
  104. help
  105. Choose this option to build U-Boot for RISC-V S-Mode.
  106. endchoice
  107. choice
  108. prompt "SPL Run Mode"
  109. default SPL_RISCV_MMODE
  110. depends on SPL
  111. config SPL_RISCV_MMODE
  112. bool "Machine"
  113. help
  114. Choose this option to build U-Boot SPL for RISC-V M-Mode.
  115. config SPL_RISCV_SMODE
  116. bool "Supervisor"
  117. help
  118. Choose this option to build U-Boot SPL for RISC-V S-Mode.
  119. endchoice
  120. config RISCV_ISA_C
  121. bool "Emit compressed instructions"
  122. default y
  123. help
  124. Adds "C" to the ISA subsets that the toolchain is allowed to emit
  125. when building U-Boot, which results in compressed instructions in the
  126. U-Boot binary.
  127. config RISCV_ISA_F
  128. bool "Standard extension for Single-Precision Floating Point"
  129. default y
  130. help
  131. Adds "F" to the ISA string passed to the compiler.
  132. config RISCV_ISA_D
  133. bool "Standard extension for Double-Precision Floating Point"
  134. depends on RISCV_ISA_F
  135. default y
  136. help
  137. Adds "D" to the ISA string passed to the compiler and changes the
  138. riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
  139. lp64d.
  140. config RISCV_ISA_A
  141. def_bool y
  142. config 32BIT
  143. bool
  144. config 64BIT
  145. bool
  146. config DMA_ADDR_T_64BIT
  147. bool
  148. default y if 64BIT
  149. config SIFIVE_CLINT
  150. bool
  151. depends on RISCV_MMODE
  152. help
  153. The SiFive CLINT block holds memory-mapped control and status registers
  154. associated with software and timer interrupts.
  155. config SPL_SIFIVE_CLINT
  156. bool
  157. depends on SPL_RISCV_MMODE
  158. help
  159. The SiFive CLINT block holds memory-mapped control and status registers
  160. associated with software and timer interrupts.
  161. config SIFIVE_CACHE
  162. bool
  163. help
  164. This enables the operations to configure SiFive cache
  165. config ANDES_PLIC
  166. bool
  167. depends on RISCV_MMODE || SPL_RISCV_MMODE
  168. select REGMAP
  169. select SYSCON
  170. select SPL_REGMAP if SPL
  171. select SPL_SYSCON if SPL
  172. help
  173. The Andes PLIC block holds memory-mapped claim and pending registers
  174. associated with software interrupt.
  175. config SYS_MALLOC_F_LEN
  176. default 0x1000
  177. config SMP
  178. bool "Symmetric Multi-Processing"
  179. depends on SBI_V01 || !RISCV_SMODE
  180. help
  181. This enables support for systems with more than one CPU. If
  182. you say N here, U-Boot will run on single and multiprocessor
  183. machines, but will use only one CPU of a multiprocessor
  184. machine. If you say Y here, U-Boot will run on many, but not
  185. all, single processor machines.
  186. config SPL_SMP
  187. bool "Symmetric Multi-Processing in SPL"
  188. depends on SPL && SPL_RISCV_MMODE
  189. default y
  190. help
  191. This enables support for systems with more than one CPU in SPL.
  192. If you say N here, U-Boot SPL will run on single and multiprocessor
  193. machines, but will use only one CPU of a multiprocessor
  194. machine. If you say Y here, U-Boot SPL will run on many, but not
  195. all, single processor machines.
  196. config NR_CPUS
  197. int "Maximum number of CPUs (2-32)"
  198. range 2 32
  199. depends on SMP || SPL_SMP
  200. default 8
  201. help
  202. On multiprocessor machines, U-Boot sets up a stack for each CPU.
  203. Stack memory is pre-allocated. U-Boot must therefore know the
  204. maximum number of CPUs that may be present.
  205. config SBI
  206. bool
  207. default y if RISCV_SMODE || SPL_RISCV_SMODE
  208. choice
  209. prompt "SBI support"
  210. default SBI_V02
  211. config SBI_V01
  212. bool "SBI v0.1 support"
  213. depends on SBI
  214. help
  215. This config allows kernel to use SBI v0.1 APIs. This will be
  216. deprecated in future once legacy M-mode software are no longer in use.
  217. config SBI_V02
  218. bool "SBI v0.2 support"
  219. depends on SBI
  220. help
  221. This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
  222. scalable and extendable to handle future needs for RISC-V supervisor
  223. interfaces. For example, with SBI v0.2 HSM extension, only a single
  224. hart need to boot and enter operating system. The booting hart can
  225. bring up secondary harts one by one afterwards.
  226. Choose this option if OpenSBI v0.7 or above release is used together
  227. with U-Boot.
  228. endchoice
  229. config SBI_IPI
  230. bool
  231. depends on SBI
  232. default y if RISCV_SMODE || SPL_RISCV_SMODE
  233. depends on SMP
  234. config XIP
  235. bool "XIP mode"
  236. help
  237. XIP (eXecute In Place) is a method for executing code directly
  238. from a NOR flash memory without copying the code to ram.
  239. Say yes here if U-Boot boots from flash directly.
  240. config SHOW_REGS
  241. bool "Show registers on unhandled exception"
  242. config RISCV_PRIV_1_9
  243. bool "Use version 1.9 of the RISC-V priviledged specification"
  244. help
  245. Older versions of the RISC-V priviledged specification had
  246. separate counter enable CSRs for each privilege mode. Writing
  247. to the unified mcounteren CSR on a processor implementing the
  248. old specification will result in an illegal instruction
  249. exception. In addition to counter CSR changes, the way virtual
  250. memory is configured was also changed.
  251. config STACK_SIZE_SHIFT
  252. int
  253. default 14
  254. config OF_BOARD_FIXUP
  255. default y if OF_SEPARATE && RISCV_SMODE
  256. menu "Use assembly optimized implementation of memory routines"
  257. config USE_ARCH_MEMCPY
  258. bool "Use an assembly optimized implementation of memcpy"
  259. default y
  260. help
  261. Enable the generation of an optimized version of memcpy.
  262. Such an implementation may be faster under some conditions
  263. but may increase the binary size.
  264. config SPL_USE_ARCH_MEMCPY
  265. bool "Use an assembly optimized implementation of memcpy for SPL"
  266. default y if USE_ARCH_MEMCPY
  267. depends on SPL
  268. help
  269. Enable the generation of an optimized version of memcpy.
  270. Such an implementation may be faster under some conditions
  271. but may increase the binary size.
  272. config TPL_USE_ARCH_MEMCPY
  273. bool "Use an assembly optimized implementation of memcpy for TPL"
  274. default y if USE_ARCH_MEMCPY
  275. depends on TPL
  276. help
  277. Enable the generation of an optimized version of memcpy.
  278. Such an implementation may be faster under some conditions
  279. but may increase the binary size.
  280. config USE_ARCH_MEMMOVE
  281. bool "Use an assembly optimized implementation of memmove"
  282. default y
  283. help
  284. Enable the generation of an optimized version of memmove.
  285. Such an implementation may be faster under some conditions
  286. but may increase the binary size.
  287. config SPL_USE_ARCH_MEMMOVE
  288. bool "Use an assembly optimized implementation of memmove for SPL"
  289. default y if USE_ARCH_MEMCPY
  290. depends on SPL
  291. help
  292. Enable the generation of an optimized version of memmove.
  293. Such an implementation may be faster under some conditions
  294. but may increase the binary size.
  295. config TPL_USE_ARCH_MEMMOVE
  296. bool "Use an assembly optimized implementation of memmove for TPL"
  297. default y if USE_ARCH_MEMCPY
  298. depends on TPL
  299. help
  300. Enable the generation of an optimized version of memmove.
  301. Such an implementation may be faster under some conditions
  302. but may increase the binary size.
  303. config USE_ARCH_MEMSET
  304. bool "Use an assembly optimized implementation of memset"
  305. default y
  306. help
  307. Enable the generation of an optimized version of memset.
  308. Such an implementation may be faster under some conditions
  309. but may increase the binary size.
  310. config SPL_USE_ARCH_MEMSET
  311. bool "Use an assembly optimized implementation of memset for SPL"
  312. default y if USE_ARCH_MEMSET
  313. depends on SPL
  314. help
  315. Enable the generation of an optimized version of memset.
  316. Such an implementation may be faster under some conditions
  317. but may increase the binary size.
  318. config TPL_USE_ARCH_MEMSET
  319. bool "Use an assembly optimized implementation of memset for TPL"
  320. default y if USE_ARCH_MEMSET
  321. depends on TPL
  322. help
  323. Enable the generation of an optimized version of memset.
  324. Such an implementation may be faster under some conditions
  325. but may increase the binary size.
  326. endmenu
  327. endmenu