cam_enc_4xx.h 14 KB

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  1. /*
  2. * Copyright (C) 2009 Texas Instruments Incorporated
  3. *
  4. * Copyright (C) 2011
  5. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #ifndef __CONFIG_H
  23. #define __CONFIG_H
  24. #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
  25. #define CONFIG_SYS_CONSOLE_INFO_QUIET
  26. /* SoC Configuration */
  27. #define CONFIG_ARM926EJS /* arm926ejs CPU */
  28. #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
  29. #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
  30. #define CONFIG_SYS_HZ 1000
  31. #define CONFIG_SOC_DM365
  32. #define CONFIG_MACH_TYPE MACH_TYPE_DAVINCI_DM365_EVM
  33. #define CONFIG_HOSTNAME cam_enc_4xx
  34. #define BOARD_LATE_INIT
  35. #define CONFIG_CAM_ENC_LED_MASK 0x0fc00000
  36. /* Memory Info */
  37. #define CONFIG_NR_DRAM_BANKS 1
  38. #define PHYS_SDRAM_1 0x80000000
  39. #define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MiB */
  40. #define DDR_4BANKS /* 4-bank DDR2 (256MB) */
  41. #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
  42. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  43. /* Serial Driver info: UART0 for console */
  44. #define CONFIG_SYS_NS16550
  45. #define CONFIG_SYS_NS16550_SERIAL
  46. #define CONFIG_SYS_NS16550_REG_SIZE -4
  47. #define CONFIG_SYS_NS16550_COM1 0x01c20000
  48. #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
  49. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  50. #define CONFIG_CONS_INDEX 1
  51. #define CONFIG_BAUDRATE 115200
  52. /* Network Configuration */
  53. #define CONFIG_DRIVER_TI_EMAC
  54. #define CONFIG_EMAC_MDIO_PHY_NUM 0
  55. #define CONFIG_SYS_EMAC_TI_CLKDIV 0xa9 /* 1MHz */
  56. #define CONFIG_MII
  57. #define CONFIG_BOOTP_DEFAULT
  58. #define CONFIG_BOOTP_DNS
  59. #define CONFIG_BOOTP_DNS2
  60. #define CONFIG_BOOTP_SEND_HOSTNAME
  61. #define CONFIG_NET_RETRY_COUNT 10
  62. #define CONFIG_NET_MULTI
  63. #define CONFIG_CMD_MII
  64. #define CONFIG_SYS_DCACHE_OFF
  65. #define CONFIG_RESET_PHY_R
  66. /* I2C */
  67. #define CONFIG_HARD_I2C
  68. #define CONFIG_DRIVER_DAVINCI_I2C
  69. #define CONFIG_SYS_I2C_SPEED 400000
  70. #define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
  71. /* NAND: socketed, two chipselects, normally 2 GBytes */
  72. #define CONFIG_NAND_DAVINCI
  73. #define CONFIG_SYS_NAND_CS 2
  74. #define CONFIG_SYS_NAND_USE_FLASH_BBT
  75. #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  76. #define CONFIG_SYS_NAND_PAGE_2K
  77. #define CONFIG_SYS_NAND_LARGEPAGE
  78. #define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
  79. /* socket has two chipselects, nCE0 gated by address BIT(14) */
  80. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  81. #define CONFIG_SYS_NAND_MAX_CHIPS 1
  82. /* SPI support */
  83. #define CONFIG_SPI
  84. #define CONFIG_SPI_FLASH
  85. #define CONFIG_SPI_FLASH_STMICRO
  86. #define CONFIG_DAVINCI_SPI
  87. #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
  88. #define CONFIG_SYS_SPI_CLK davinci_clk_get(SPI_PLLDIV)
  89. #define CONFIG_SF_DEFAULT_SPEED 3000000
  90. #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  91. #define CONFIG_CMD_SF
  92. /* SD/MMC */
  93. #define CONFIG_MMC
  94. #define CONFIG_GENERIC_MMC
  95. #define CONFIG_DAVINCI_MMC
  96. #define CONFIG_MMC_MBLOCK
  97. /* U-Boot command configuration */
  98. #include <config_cmd_default.h>
  99. #define CONFIG_CMD_BDI
  100. #undef CONFIG_CMD_FLASH
  101. #undef CONFIG_CMD_FPGA
  102. #undef CONFIG_CMD_SETGETDCR
  103. #define CONFIG_CMD_ASKENV
  104. #define CONFIG_CMD_CACHE
  105. #define CONFIG_CMD_DHCP
  106. #define CONFIG_CMD_I2C
  107. #define CONFIG_CMD_PING
  108. #define CONFIG_CMD_SAVES
  109. #ifdef CONFIG_MMC
  110. #define CONFIG_DOS_PARTITION
  111. #define CONFIG_CMD_EXT2
  112. #define CONFIG_CMD_FAT
  113. #define CONFIG_CMD_MMC
  114. #endif
  115. #ifdef CONFIG_NAND_DAVINCI
  116. #define CONFIG_CMD_MTDPARTS
  117. #define CONFIG_MTD_PARTITIONS
  118. #define CONFIG_MTD_DEVICE
  119. #define CONFIG_CMD_NAND
  120. #define CONFIG_CMD_UBI
  121. #define CONFIG_RBTREE
  122. #endif
  123. #define CONFIG_CRC32_VERIFY
  124. #define CONFIG_MX_CYCLIC
  125. /* U-Boot general configuration */
  126. #undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
  127. #define CONFIG_BOOTFILE "uImage" /* Boot file name */
  128. #define CONFIG_SYS_PROMPT "cam_enc_4xx> " /* Monitor Command Prompt */
  129. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  130. #define CONFIG_SYS_PBSIZE /* Print buffer size */ \
  131. (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  132. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  133. #define CONFIG_SYS_HUSH_PARSER
  134. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  135. #define CONFIG_SYS_LONGHELP
  136. #ifdef CONFIG_NAND_DAVINCI
  137. #define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
  138. #define CONFIG_ENV_IS_IN_NAND
  139. #define CONFIG_ENV_OFFSET 0x0
  140. #undef CONFIG_ENV_IS_IN_FLASH
  141. #endif
  142. #if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
  143. #define CONFIG_CMD_ENV
  144. #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
  145. #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
  146. #define CONFIG_ENV_IS_IN_MMC
  147. #undef CONFIG_ENV_IS_IN_FLASH
  148. #endif
  149. #define CONFIG_BOOTDELAY 3
  150. #define CONFIG_CMDLINE_EDITING
  151. #define CONFIG_VERSION_VARIABLE
  152. #define CONFIG_TIMESTAMP
  153. /* U-Boot memory configuration */
  154. #define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
  155. #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
  156. #define CONFIG_SYS_MEMTEST_START 0x80000000 /* physical address */
  157. #define CONFIG_SYS_MEMTEST_END 0x81000000 /* test 16MB RAM */
  158. /* Linux interfacing */
  159. #define CONFIG_CMDLINE_TAG
  160. #define CONFIG_SETUP_MEMORY_TAGS
  161. #define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
  162. #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
  163. #define MTDIDS_DEFAULT "nand0=davinci_nand.0"
  164. #ifdef CONFIG_SYS_NAND_LARGEPAGE
  165. /* Use same layout for 128K/256K blocks; allow some bad blocks */
  166. #define PART_BOOT "2m(bootloader)ro,"
  167. #endif
  168. #define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
  169. #define PART_REST "-(filesystem)"
  170. #define MTDPARTS_DEFAULT \
  171. "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
  172. #define CONFIG_SYS_NAND_PAGE_SIZE (0x800)
  173. #define CONFIG_SYS_NAND_BLOCK_SIZE (0x20000)
  174. /* Defines for SPL */
  175. #define CONFIG_SPL
  176. #define CONFIG_SPL_NAND_SUPPORT
  177. #define CONFIG_SPL_NAND_SIMPLE
  178. #define CONFIG_SPL_NAND_LOAD
  179. #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
  180. #define CONFIG_SPL_SERIAL_SUPPORT
  181. #define CONFIG_SPL_POST_MEM_SUPPORT
  182. #define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds"
  183. #define CONFIG_SPL_STACK (0x00010000 + 0x7f00)
  184. #define CONFIG_SPL_TEXT_BASE 0x0000020 /*CONFIG_SYS_SRAM_START*/
  185. #define CONFIG_SPL_MAX_SIZE 12320
  186. #ifndef CONFIG_SPL_BUILD
  187. #define CONFIG_SYS_TEXT_BASE 0x81080000
  188. #endif
  189. #define CONFIG_SYS_NAND_BASE 0x02000000
  190. #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
  191. CONFIG_SYS_NAND_PAGE_SIZE)
  192. #define CONFIG_SYS_NAND_ECCPOS { \
  193. 24, 25, 26, 27, 28, \
  194. 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
  195. 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
  196. 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
  197. 59, 60, 61, 62, 63 }
  198. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  199. #define CONFIG_SYS_NAND_ECCSIZE 0x200
  200. #define CONFIG_SYS_NAND_ECCBYTES 10
  201. #define CONFIG_SYS_NAND_OOBSIZE 64
  202. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  203. #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
  204. CONFIG_SYS_NAND_ECCSIZE)
  205. #define CONFIG_SYS_NAND_ECCTOTAL (40)
  206. /*
  207. * RBL searches from Block n (n = 1..24)
  208. * so we can define, how many UBL Headers
  209. * we can write before the real spl code
  210. */
  211. #define CONFIG_SYS_NROF_UBL_HEADER 5
  212. #define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
  213. #define CONFIG_SYS_NAND_U_BOOT_DST 0x81080000 /* u-boot TEXT_BASE */
  214. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
  215. /*
  216. * Post tests for memory testing
  217. */
  218. #define CONFIG_POST CONFIG_SYS_POST_MEMORY
  219. #define _POST_WORD_ADDR 0x0
  220. #define CONFIG_DISPLAY_CPUINFO
  221. #define CONFIG_DISPLAY_BOARDINFO
  222. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
  223. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0xc0000
  224. #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
  225. /*
  226. * U-Boot is a 3rd stage loader and if booting with spl, cpu setup is
  227. * done in board_init_f from c code.
  228. */
  229. #define CONFIG_SKIP_LOWLEVEL_INIT
  230. /* for UBL header */
  231. #define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
  232. #define CONFIG_SYS_DM36x_PLL1_PLLM 0x55
  233. #define CONFIG_SYS_DM36x_PLL1_PREDIV 0x8005
  234. #define CONFIG_SYS_DM36x_PLL2_PLLM 0x09
  235. #define CONFIG_SYS_DM36x_PLL2_PREDIV 0x8000
  236. #define CONFIG_SYS_DM36x_PERI_CLK_CTRL 0x243F04FC
  237. #define CONFIG_SYS_DM36x_PLL1_PLLDIV1 0x801b
  238. #define CONFIG_SYS_DM36x_PLL1_PLLDIV2 0x8001
  239. /* POST DIV 680/2 = 340Mhz -> MJCP and HDVICP bus interface clock */
  240. #define CONFIG_SYS_DM36x_PLL1_PLLDIV3 0x8001
  241. /*
  242. * POST DIV 680/4 = 170Mhz -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
  243. * interface clk)
  244. */
  245. #define CONFIG_SYS_DM36x_PLL1_PLLDIV4 0x8003
  246. /* POST DIV 680/2 = 340Mhz -> VPSS */
  247. #define CONFIG_SYS_DM36x_PLL1_PLLDIV5 0x8001
  248. /* POST DIV 680/9 = 75.6 Mhz -> VENC */
  249. #define CONFIG_SYS_DM36x_PLL1_PLLDIV6 0x8008
  250. /*
  251. * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
  252. * down to 340 Mhz)
  253. */
  254. #define CONFIG_SYS_DM36x_PLL1_PLLDIV7 0x8000
  255. /* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
  256. #define CONFIG_SYS_DM36x_PLL1_PLLDIV8 0x8006
  257. /* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
  258. #define CONFIG_SYS_DM36x_PLL1_PLLDIV9 0x801b
  259. #define CONFIG_SYS_DM36x_PLL2_PLLDIV1 0x8011
  260. /* POST DIV 432/1=432 Mhz -> ARM926/(HDVICP block) clk */
  261. #define CONFIG_SYS_DM36x_PLL2_PLLDIV2 0x8000
  262. #define CONFIG_SYS_DM36x_PLL2_PLLDIV3 0x8001
  263. /* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
  264. #define CONFIG_SYS_DM36x_PLL2_PLLDIV4 0x8014
  265. /* POST DIV 432/16=27 Mhz -> VENC(For SD modes, requires) */
  266. #define CONFIG_SYS_DM36x_PLL2_PLLDIV5 0x800f
  267. /*
  268. * READ LATENCY 7 (CL + 2)
  269. * CONFIG_PWRDNEN = 1
  270. * CONFIG_EXT_STRBEN = 1
  271. */
  272. #define CONFIG_SYS_DM36x_DDR2_DDRPHYCR (0 \
  273. | DV_DDR_PHY_EXT_STRBEN \
  274. | DV_DDR_PHY_PWRDNEN \
  275. | (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  276. /*
  277. * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
  278. * T_RP = (trp/DDR_CLK) - 1 = (12.5 / 2.941) - 1
  279. * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
  280. * T_WR = (twr/DDR_CLK) - 1 = (15 / 2.941) - 1
  281. * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
  282. * T_RC = (trc/DDR_CLK) - 1 = (57.5 / 2.941) - 1
  283. * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
  284. * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
  285. */
  286. #define CONFIG_SYS_DM36x_DDR2_SDTIMR (0 \
  287. | (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
  288. | (4 << DV_DDR_SDTMR1_RP_SHIFT) \
  289. | (4 << DV_DDR_SDTMR1_RCD_SHIFT) \
  290. | (5 << DV_DDR_SDTMR1_WR_SHIFT) \
  291. | (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
  292. | (19 << DV_DDR_SDTMR1_RC_SHIFT) \
  293. | (2 << DV_DDR_SDTMR1_RRD_SHIFT) \
  294. | (2 << DV_DDR_SDTMR1_WTR_SHIFT))
  295. /*
  296. * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
  297. * T_XP = tCKE - 1 = 3 - 2
  298. * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
  299. * T_XSRD = txsrd - 1 = 200 - 1
  300. * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
  301. * T_CKE = tcke - 1 = 3 - 1
  302. */
  303. #define CONFIG_SYS_DM36x_DDR2_SDTIMR2 (0 \
  304. | (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) \
  305. | (2 << DV_DDR_SDTMR2_XP_SHIFT) \
  306. | (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
  307. | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) \
  308. | (2 << DV_DDR_SDTMR2_RTP_SHIFT) \
  309. | (2 << DV_DDR_SDTMR2_CKE_SHIFT))
  310. /* PR_OLD_COUNT = 0xfe */
  311. #define CONFIG_SYS_DM36x_DDR2_PBBPR 0x000000FE
  312. /* refresh rate = 0x768 */
  313. #define CONFIG_SYS_DM36x_DDR2_SDRCR 0x00000768
  314. #define CONFIG_SYS_DM36x_DDR2_SDBCR (0 \
  315. | (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
  316. | (3 << DV_DDR_SDCR_IBANK_SHIFT) \
  317. | (5 << DV_DDR_SDCR_CL_SHIFT) \
  318. | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \
  319. | (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
  320. | (1 << DV_DDR_SDCR_DDREN_SHIFT) \
  321. | (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) \
  322. | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
  323. | (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
  324. | (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
  325. #define CONFIG_SYS_DM36x_AWCCR 0xff
  326. #define CONFIG_SYS_DM36x_AB1CR 0x40400204
  327. #define CONFIG_SYS_DM36x_AB2CR 0x04ca2650
  328. /* All Video Inputs */
  329. #define CONFIG_SYS_DM36x_PINMUX0 0x00000000
  330. /*
  331. * All Video Outputs,
  332. * GPIO 86, 87 + 90 0x0000f030
  333. */
  334. #define CONFIG_SYS_DM36x_PINMUX1 0x00530002
  335. #define CONFIG_SYS_DM36x_PINMUX2 0x00001815
  336. /*
  337. * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
  338. * GPIO 25 0x60000000
  339. */
  340. #define CONFIG_SYS_DM36x_PINMUX3 0x9b5affff
  341. /*
  342. * MMC/SD0 instead of MS, SPI0
  343. * GPIO 34 0x0000c000
  344. */
  345. #define CONFIG_SYS_DM36x_PINMUX4 0x00002655
  346. /*
  347. * Default environment settings
  348. */
  349. #define xstr(s) str(s)
  350. #define str(s) #s
  351. #define DVN4XX_UBOOT_ADDR_R_RAM 0x80000000
  352. /* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
  353. #define DVN4XX_UBOOT_ADDR_R_NAND_SPL 0x80000800
  354. /*
  355. * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
  356. * CONFIG_SYS_NAND_PAGE_SIZE))
  357. */
  358. #define DVN4XX_UBOOT_ADDR_R_UBOOT 0x80003800
  359. #define CONFIG_EXTRA_ENV_SETTINGS \
  360. "u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
  361. "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
  362. "load=tftp ${u_boot_addr_r} ${uboot}\0" \
  363. "pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
  364. "writeheader=nandrbl rbl;nand erase 80000 ${pagesz};" \
  365. "nand write ${u_boot_addr_r} 80000 ${pagesz};" \
  366. "nandrbl uboot\0" \
  367. "writenand_spl=nandrbl rbl;nand erase a0000 3000;" \
  368. "nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
  369. " a0000 3000;nandrbl uboot\0" \
  370. "writeuboot=nandrbl uboot;" \
  371. "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
  372. xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \
  373. ";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT) \
  374. " " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
  375. xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
  376. "update=run load writenand_spl writeuboot\0" \
  377. "bootcmd=run bootcmd\0" \
  378. "rootpath=/opt/eldk-arm/arm\0" \
  379. "\0"
  380. /* USB Configuration */
  381. #define CONFIG_USB_DAVINCI
  382. #define CONFIG_MUSB_HCD
  383. #define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
  384. USBPHY_PHY24MHZ)
  385. #define CONFIG_CMD_USB /* include support for usb cmd */
  386. #define CONFIG_USB_STORAGE /* MSC class support */
  387. #define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
  388. #define CONFIG_CMD_FAT /* inclue support for FAT/storage */
  389. #define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
  390. #undef DAVINCI_DM365EVM
  391. #define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
  392. #define PINMUX4_USBDRVBUS_BITSET 0x2000
  393. #endif /* __CONFIG_H */