starfive_evb.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022 Starfive, Inc.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/jh7110-regs.h>
  10. #include <cpu_func.h>
  11. #include <dm/uclass.h>
  12. #include <dm/device.h>
  13. #include <env.h>
  14. #include <inttypes.h>
  15. #include <misc.h>
  16. #include <linux/bitops.h>
  17. #include <asm/arch/gpio.h>
  18. enum chip_type_t {
  19. CHIP_A = 0,
  20. CHIP_B,
  21. CHIP_MAX,
  22. };
  23. #define SYS_CLOCK_ENABLE(clk) \
  24. setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK)
  25. static void sys_reset_clear(ulong assert, ulong status, u32 rst)
  26. {
  27. u32 value;
  28. clrbits_le32(SYS_CRG_BASE + assert, BIT(rst));
  29. do {
  30. value = in_le32(SYS_CRG_BASE + status);
  31. } while ((value & BIT(rst)) != BIT(rst));
  32. }
  33. static void jh7110_timer_init(void)
  34. {
  35. SYS_CLOCK_ENABLE(TIMER_CLK_APB_SHIFT);
  36. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER0_SHIFT);
  37. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER1_SHIFT);
  38. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER2_SHIFT);
  39. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER3_SHIFT);
  40. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  41. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_APB_SHIFT);
  42. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  43. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER0_SHIFT);
  44. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  45. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER1_SHIFT);
  46. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  47. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER2_SHIFT);
  48. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  49. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER3_SHIFT);
  50. }
  51. static void jh7110_gmac_sel_tx_to_rgmii(int id)
  52. {
  53. switch (id) {
  54. case 0:
  55. clrsetbits_le32(AON_CRG_BASE + GMAC5_0_CLK_TX_SHIFT,
  56. GMAC5_0_CLK_TX_MASK,
  57. BIT(GMAC5_0_CLK_TX_BIT) & GMAC5_0_CLK_TX_MASK);
  58. break;
  59. case 1:
  60. clrsetbits_le32(SYS_CRG_BASE + GMAC5_1_CLK_TX_SHIFT,
  61. GMAC5_1_CLK_TX_MASK,
  62. BIT(GMAC5_1_CLK_TX_BIT) & GMAC5_1_CLK_TX_MASK);
  63. break;
  64. default:
  65. break;
  66. }
  67. }
  68. static void jh7110_gmac_io_pad(int id)
  69. {
  70. u32 cap = BIT(0); /* 2.5V */
  71. switch (id) {
  72. case 0:
  73. /* Improved GMAC0 TX I/O PAD capability */
  74. clrsetbits_le32(AON_IOMUX_BASE + 0x78, 0x3, cap & 0x3);
  75. clrsetbits_le32(AON_IOMUX_BASE + 0x7c, 0x3, cap & 0x3);
  76. clrsetbits_le32(AON_IOMUX_BASE + 0x80, 0x3, cap & 0x3);
  77. clrsetbits_le32(AON_IOMUX_BASE + 0x84, 0x3, cap & 0x3);
  78. clrsetbits_le32(AON_IOMUX_BASE + 0x88, 0x3, cap & 0x3);
  79. break;
  80. case 1:
  81. /* Improved GMAC1 TX I/O PAD capability */
  82. clrsetbits_le32(SYS_IOMUX_BASE + 0x26c, 0x3, cap & 0x3);
  83. clrsetbits_le32(SYS_IOMUX_BASE + 0x270, 0x3, cap & 0x3);
  84. clrsetbits_le32(SYS_IOMUX_BASE + 0x274, 0x3, cap & 0x3);
  85. clrsetbits_le32(SYS_IOMUX_BASE + 0x278, 0x3, cap & 0x3);
  86. clrsetbits_le32(SYS_IOMUX_BASE + 0x27c, 0x3, cap & 0x3);
  87. break;
  88. }
  89. }
  90. static void jh7110_gmac_init(int id, u32 chip)
  91. {
  92. switch (chip) {
  93. case CHIP_B:
  94. jh7110_gmac_sel_tx_to_rgmii(id);
  95. jh7110_gmac_io_pad(id);
  96. break;
  97. case CHIP_A:
  98. default:
  99. break;
  100. }
  101. }
  102. static void jh7110_usb_init(bool usb2_enable)
  103. {
  104. if (usb2_enable) {
  105. /*usb 2.0 utmi phy init*/
  106. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  107. USB_MODE_STRAP_MASK,
  108. (2<<USB_MODE_STRAP_SHIFT) &
  109. USB_MODE_STRAP_MASK);/*2:host mode, 4:device mode*/
  110. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  111. USB_OTG_SUSPENDM_BYPS_MASK,
  112. BIT(USB_OTG_SUSPENDM_BYPS_SHIFT)
  113. & USB_OTG_SUSPENDM_BYPS_MASK);
  114. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  115. USB_OTG_SUSPENDM_MASK,
  116. BIT(USB_OTG_SUSPENDM_SHIFT) &
  117. USB_OTG_SUSPENDM_MASK);/*HOST = 1. DEVICE = 0;*/
  118. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  119. USB_PLL_EN_MASK,
  120. BIT(USB_PLL_EN_SHIFT) & USB_PLL_EN_MASK);
  121. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  122. USB_REFCLK_MODE_MASK,
  123. BIT(USB_REFCLK_MODE_SHIFT) & USB_REFCLK_MODE_MASK);
  124. /* usb 2.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
  125. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  126. PDRSTN_SPLIT_MASK,
  127. BIT(PDRSTN_SPLIT_SHIFT) &
  128. PDRSTN_SPLIT_MASK);
  129. } else {
  130. /*usb 3.0 pipe phy config*/
  131. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_196,
  132. PCIE_CKREF_SRC_MASK,
  133. (0<<PCIE_CKREF_SRC_SHIFT) & PCIE_CKREF_SRC_MASK);
  134. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_196,
  135. PCIE_CLK_SEL_MASK,
  136. (0<<PCIE_CLK_SEL_SHIFT) & PCIE_CLK_SEL_MASK);
  137. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_328,
  138. PCIE_PHY_MODE_MASK,
  139. BIT(PCIE_PHY_MODE_SHIFT) & PCIE_PHY_MODE_MASK);
  140. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  141. PCIE_USB3_BUS_WIDTH_MASK,
  142. (0 << PCIE_USB3_BUS_WIDTH_SHIFT) &
  143. PCIE_USB3_BUS_WIDTH_MASK);
  144. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  145. PCIE_USB3_RATE_MASK,
  146. (0 << PCIE_USB3_RATE_SHIFT) & PCIE_USB3_RATE_MASK);
  147. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  148. PCIE_USB3_RX_STANDBY_MASK,
  149. (0 << PCIE_USB3_RX_STANDBY_SHIFT)
  150. & PCIE_USB3_RX_STANDBY_MASK);
  151. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  152. PCIE_USB3_PHY_ENABLE_MASK,
  153. BIT(PCIE_USB3_PHY_ENABLE_SHIFT)
  154. & PCIE_USB3_PHY_ENABLE_MASK);
  155. /* usb 3.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
  156. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  157. PDRSTN_SPLIT_MASK,
  158. (0 << PDRSTN_SPLIT_SHIFT) & PDRSTN_SPLIT_MASK);
  159. }
  160. }
  161. static u32 get_chip_type(void)
  162. {
  163. u32 value;
  164. value = in_le32(AON_IOMUX_BASE + AON_GPIO_DIN_REG);
  165. value = (value & BIT(3)) >> 3;
  166. switch (value) {
  167. case CHIP_B:
  168. env_set("chip_vision", "B");
  169. break;
  170. case CHIP_A:
  171. default:
  172. env_set("chip_vision", "A");
  173. break;
  174. }
  175. return value;
  176. }
  177. /*enable U74-mc hart1~hart4 prefetcher*/
  178. static void enable_prefetcher(void)
  179. {
  180. u32 hart;
  181. u32 *reg;
  182. #define L2_PREFETCHER_BASE_ADDR 0x2030000
  183. #define L2_PREFETCHER_OFFSET 0x2000
  184. /*hart1~hart4*/
  185. for (hart = 1; hart < 5; hart++) {
  186. reg = (u32 *)((u64)(L2_PREFETCHER_BASE_ADDR
  187. + hart*L2_PREFETCHER_OFFSET));
  188. mb(); /* memory barrier */
  189. setbits_le32(reg, 0x1);
  190. mb(); /* memory barrier */
  191. }
  192. }
  193. int board_init(void)
  194. {
  195. enable_caches();
  196. /*enable hart1-hart4 prefetcher*/
  197. enable_prefetcher();
  198. jh7110_timer_init();
  199. jh7110_usb_init(true);
  200. return 0;
  201. }
  202. #ifdef CONFIG_MISC_INIT_R
  203. int misc_init_r(void)
  204. {
  205. char mac0[6] = {0x66, 0x34, 0xb0, 0x6c, 0xde, 0xad};
  206. char mac1[6] = {0x66, 0x34, 0xb0, 0x7c, 0xae, 0x5d};
  207. u32 chip;
  208. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  209. struct udevice *dev;
  210. char buf[16];
  211. int ret;
  212. #define MACADDR_OFFSET 0x8
  213. ret = uclass_get_device_by_driver(UCLASS_MISC,
  214. DM_DRIVER_GET(starfive_otp), &dev);
  215. if (ret) {
  216. debug("%s: could not find otp device\n", __func__);
  217. goto err;
  218. }
  219. ret = misc_read(dev, MACADDR_OFFSET, buf, sizeof(buf));
  220. if (ret != sizeof(buf))
  221. printf("%s: error reading mac from OTP\n", __func__);
  222. else
  223. if (buf[0] != 0xff) {
  224. memcpy(mac0, buf, 6);
  225. memcpy(mac1, &buf[8], 6);
  226. }
  227. err:
  228. #endif
  229. eth_env_set_enetaddr("eth0addr", mac0);
  230. eth_env_set_enetaddr("eth1addr", mac1);
  231. chip = get_chip_type();
  232. jh7110_gmac_init(0, chip);
  233. jh7110_gmac_init(1, chip);
  234. return 0;
  235. }
  236. #endif