sl28.rst 4.9 KB

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  1. .. SPDX-License-Identifier: GPL-2.0+
  2. Summary
  3. =======
  4. The Kontron SMARC-sAL28 board is a TSN-enabled dual-core ARM A72
  5. processor module with an on-chip 6-port TSN switch and a 3D GPU.
  6. Quickstart
  7. ==========
  8. Compile U-Boot
  9. --------------
  10. Configure and compile the binary::
  11. $ make kontron_sl28_defconfig
  12. $ CROSS_COMPILE=aarch64-linux-gnu make
  13. Copy u-boot.rom to a TFTP server.
  14. Install the bootloader on the board
  15. -----------------------------------
  16. Please note, this bootloader doesn't support the builtin watchdog (yet),
  17. therefore you have to disable it, see below. Otherwise you'll end up in
  18. the failsafe bootloader on every reset::
  19. > tftp path/to/u-boot.rom
  20. > sf probe 0
  21. > sf update $fileaddr 0x210000 $filesize
  22. The board is fully failsafe, you can't break anything. But because you've
  23. disabled the builtin watchdog you might have to manually enter failsafe
  24. mode by asserting the ``FORCE_RECOV#`` line during board reset.
  25. Disable the builtin watchdog
  26. ----------------------------
  27. - boot into the failsafe bootloader, either by asserting the
  28. ``FORCE_RECOV#`` line or if you still have the original bootloader
  29. installed you can use the command::
  30. > wdt dev cpld_watchdog@4a; wdt expire 1
  31. - in the failsafe bootloader use the "sl28 nvm" command to disable
  32. the automatic start of the builtin watchdog::
  33. > sl28 nvm 0008
  34. - power-cycle the board
  35. Useful I2C tricks
  36. =================
  37. The board has a board management controller which is not supported in
  38. u-boot (yet). But you can use the i2c command to access it.
  39. - reset into failsafe bootloader::
  40. > i2c mw 4a 5.1 0; i2c mw 4a 6.1 6b; i2c mw 4a 4.1 42
  41. - read board management controller version::
  42. > i2c md 4a 3.1 1
  43. Non-volatile Board Configuration Bits
  44. =====================================
  45. The board has 16 configuration bits which are stored in the CPLD and are
  46. non-volatile. These can be changed by the `sl28 nvm` command.
  47. === ===============================================================
  48. Bit Description
  49. === ===============================================================
  50. 0 Power-on inhibit
  51. 1 Enable eMMC boot
  52. 2 Enable watchdog by default
  53. 3 Disable failsafe watchdog by default
  54. 4 Clock generator selection bit 0
  55. 5 Clock generator selection bit 1
  56. 6 Disable CPU SerDes clock #2 and PCIe-A clock output
  57. 7 Disable PCIe-B and PCIe-C clock output
  58. 8 Keep onboard PHYs in reset
  59. 9 Keep USB hub in reset
  60. 10 Keep eDP-to-LVDS converter in reset
  61. 11 Enable I2C stuck recovery on I2C PM and I2C GP busses
  62. 12 Enable automatic onboard PHY H/W reset
  63. 13 reserved
  64. 14 Used by the RCW to determine boot source
  65. 15 Used by the RCW to determine boot source
  66. === ===============================================================
  67. Please note, that if the board is in failsafe mode, the bits will have the
  68. factory defaults, ie. all bits are off.
  69. Power-On Inhibit
  70. ----------------
  71. If this is set, the board doesn't automatically turn on when power is
  72. applied. Instead, the user has to either toggle the ``PWR_BTN#`` line or
  73. use any other wake-up source such as RTC alarm or Wake-on-LAN.
  74. eMMC Boot
  75. ---------
  76. If this is set, the RCW will be fetched from the on-board eMMC at offset
  77. 1MiB. For further details, have a look at the `Reset Configuration Word
  78. Documentation`_.
  79. Watchdog
  80. --------
  81. By default, the CPLD watchdog is enabled in failsafe mode. Using bits 2 and
  82. 3, the user can change its mode or disable it altogether.
  83. ===== ===== ===============================
  84. Bit 2 Bit 3 Description
  85. ===== ===== ===============================
  86. 0 0 Watchdog enabled, failsafe mode
  87. 0 1 Watchdog disabled
  88. 1 0 Watchdog enabled, failsafe mode
  89. 1 1 Watchdog enabled, normal mode
  90. ===== ===== ===============================
  91. Clock Generator Select
  92. ----------------------
  93. The board is prepared to supply different SerDes clock speeds. But for now,
  94. only setting 0 is supported, otherwise the CPU will hang because the PLL
  95. will not lock.
  96. Clock Output Disable And Keep Devices In Reset
  97. ----------------------------------------------
  98. To safe power, the user might disable different devices and clock output of
  99. the board. It is not supported to disable the "CPU SerDes clock #2" for
  100. now, otherwise the CPU will hang because the PLL will not lock.
  101. Automatic reset of the onboard PHYs
  102. -----------------------------------
  103. By default, there is no hardware reset of the onboard PHY. This is because
  104. for Wake-on-LAN, some registers have to retain their values. If you don't
  105. use the WOL feature and a soft reset of the PHY is not enough you can
  106. enable the hardware reset. The onboard PHY hardware reset follows the
  107. power-on reset.
  108. Further documentation
  109. =====================
  110. - `Vendor Documentation`_
  111. - `Reset Configuration Word Documentation`_
  112. .. _Reset Configuration Word Documentation: https://raw.githubusercontent.com/kontron/rcw-smarc-sal28/master/README.md
  113. .. _Vendor Documentation: https://raw.githubusercontent.com/kontron/u-boot-smarc-sal28/master/board/kontron/sl28/README.md