sl28.c 1.2 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768
  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <common.h>
  3. #include <malloc.h>
  4. #include <errno.h>
  5. #include <fsl_ddr.h>
  6. #include <fdt_support.h>
  7. #include <linux/libfdt.h>
  8. #include <env_internal.h>
  9. #include <asm/arch-fsl-layerscape/soc.h>
  10. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  11. #include <i2c.h>
  12. #include <asm/arch/soc.h>
  13. #include <fsl_immap.h>
  14. #include <netdev.h>
  15. #include <fdtdec.h>
  16. #include <miiphy.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. int board_init(void)
  19. {
  20. if (CONFIG_IS_ENABLED(FSL_CAAM))
  21. sec_init();
  22. return 0;
  23. }
  24. int board_eth_init(struct bd_info *bis)
  25. {
  26. return pci_eth_init(bis);
  27. }
  28. int checkboard(void)
  29. {
  30. printf("EL: %d\n", current_el());
  31. return 0;
  32. }
  33. void detail_board_ddr_info(void)
  34. {
  35. puts("\nDDR ");
  36. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  37. print_ddr_info(0);
  38. }
  39. int ft_board_setup(void *blob, struct bd_info *bd)
  40. {
  41. u64 base[CONFIG_NR_DRAM_BANKS];
  42. u64 size[CONFIG_NR_DRAM_BANKS];
  43. int nbanks = CONFIG_NR_DRAM_BANKS;
  44. int i;
  45. ft_cpu_setup(blob, bd);
  46. /* fixup DT for the two GPP DDR banks */
  47. for (i = 0; i < nbanks; i++) {
  48. base[i] = gd->bd->bi_dram[i].start;
  49. size[i] = gd->bd->bi_dram[i].size;
  50. }
  51. fdt_fixup_memory_banks(blob, base, size, nbanks);
  52. fdt_fixup_icid(blob);
  53. return 0;
  54. }