ddr.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <common.h>
  3. #include <asm/io.h>
  4. #include <fsl_ddr_sdram.h>
  5. DECLARE_GLOBAL_DATA_PTR;
  6. #define DCFG_GPPORCR1 0x20
  7. #define GPPORCR1_MEM_MASK (0x7 << 5)
  8. #define GPPORCR1_MEM_512MB_CS0 (0x0 << 5)
  9. #define GPPORCR1_MEM_1GB_CS0 (0x1 << 5)
  10. #define GPPORCR1_MEM_2GB_CS0 (0x2 << 5)
  11. #define GPPORCR1_MEM_4GB_CS0_1 (0x3 << 5)
  12. #define GPPORCR1_MEM_4GB_CS0_2 (0x4 << 5)
  13. #define GPPORCR1_MEM_8GB_CS0_1_2_3 (0x5 << 5)
  14. #define GPPORCR1_MEM_8GB_CS0_1 (0x6 << 5)
  15. static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = {
  16. .cs[0].bnds = 0x0000007f,
  17. .cs[0].config = 0x80044402,
  18. .cs[1].bnds = 0x008000ff,
  19. .cs[1].config = 0x80004402,
  20. .timing_cfg_0 = 0x9011010c,
  21. .timing_cfg_3 = 0x010c1000,
  22. .timing_cfg_1 = 0xbcb48c66,
  23. .timing_cfg_2 = 0x0fc0d118,
  24. .ddr_sdram_cfg = 0xe70c000c,
  25. .ddr_sdram_cfg_2 = 0x24401111,
  26. .ddr_sdram_mode = 0x00441c70,
  27. .ddr_sdram_mode_3 = 0x00001c70,
  28. .ddr_sdram_mode_5 = 0x00001c70,
  29. .ddr_sdram_mode_7 = 0x00001c70,
  30. .ddr_sdram_mode_2 = 0x00180000,
  31. .ddr_sdram_mode_4 = 0x00180000,
  32. .ddr_sdram_mode_6 = 0x00180000,
  33. .ddr_sdram_mode_8 = 0x00180000,
  34. .ddr_sdram_interval = 0x0c30030c,
  35. .ddr_data_init = 0xdeadbeef,
  36. .ddr_sdram_clk_cntl = 0x02400000,
  37. .timing_cfg_4 = 0x00000001,
  38. .timing_cfg_5 = 0x04401400,
  39. .ddr_zq_cntl = 0x89080600,
  40. .ddr_wrlvl_cntl = 0x8675f606,
  41. .ddr_wrlvl_cntl_2 = 0x04080700,
  42. .ddr_wrlvl_cntl_3 = 0x00000009,
  43. .ddr_cdr1 = 0x80040000,
  44. .ddr_cdr2 = 0x0000bc01,
  45. };
  46. int fsl_initdram(void)
  47. {
  48. u32 gpporcr1 = in_le32(DCFG_BASE + DCFG_GPPORCR1);
  49. phys_size_t dram_size;
  50. switch (gpporcr1 & GPPORCR1_MEM_MASK) {
  51. case GPPORCR1_MEM_2GB_CS0:
  52. dram_size = 0x80000000;
  53. ddr_cfg_regs.cs[1].bnds = 0;
  54. ddr_cfg_regs.cs[1].config = 0;
  55. ddr_cfg_regs.cs[1].config_2 = 0;
  56. break;
  57. case GPPORCR1_MEM_4GB_CS0_1:
  58. dram_size = 0x100000000ULL;
  59. break;
  60. case GPPORCR1_MEM_512MB_CS0:
  61. dram_size = 0x20000000;
  62. fallthrough; /* for now */
  63. case GPPORCR1_MEM_1GB_CS0:
  64. dram_size = 0x40000000;
  65. fallthrough; /* for now */
  66. case GPPORCR1_MEM_4GB_CS0_2:
  67. dram_size = 0x100000000ULL;
  68. fallthrough; /* for now */
  69. case GPPORCR1_MEM_8GB_CS0_1:
  70. case GPPORCR1_MEM_8GB_CS0_1_2_3:
  71. dram_size = 0x200000000ULL;
  72. fallthrough; /* for now */
  73. default:
  74. panic("Unsupported memory configuration (%08x)\n",
  75. gpporcr1 & GPPORCR1_MEM_MASK);
  76. break;
  77. }
  78. if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD))
  79. fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
  80. gd->ram_size = dram_size;
  81. return 0;
  82. }