am33xx.dtsi 17 KB

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  1. /*
  2. * Device Tree Source for AM33XX SoC
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. #include <dt-bindings/bus/ti-sysc.h>
  11. #include <dt-bindings/gpio/gpio.h>
  12. #include <dt-bindings/pinctrl/am33xx.h>
  13. #include <dt-bindings/clock/am3.h>
  14. / {
  15. compatible = "ti,am33xx";
  16. interrupt-parent = <&intc>;
  17. #address-cells = <1>;
  18. #size-cells = <1>;
  19. chosen { };
  20. aliases {
  21. i2c0 = &i2c0;
  22. i2c1 = &i2c1;
  23. i2c2 = &i2c2;
  24. serial0 = &uart0;
  25. serial1 = &uart1;
  26. serial2 = &uart2;
  27. serial3 = &uart3;
  28. serial4 = &uart4;
  29. serial5 = &uart5;
  30. d-can0 = &dcan0;
  31. d-can1 = &dcan1;
  32. usb0 = &usb0;
  33. usb1 = &usb1;
  34. phy0 = &usb0_phy;
  35. phy1 = &usb1_phy;
  36. ethernet0 = &cpsw_emac0;
  37. ethernet1 = &cpsw_emac1;
  38. spi0 = &spi0;
  39. spi1 = &spi1;
  40. };
  41. cpus {
  42. #address-cells = <1>;
  43. #size-cells = <0>;
  44. cpu@0 {
  45. compatible = "arm,cortex-a8";
  46. enable-method = "ti,am3352";
  47. device_type = "cpu";
  48. reg = <0>;
  49. operating-points-v2 = <&cpu0_opp_table>;
  50. clocks = <&dpll_mpu_ck>;
  51. clock-names = "cpu";
  52. clock-latency = <300000>; /* From omap-cpufreq driver */
  53. cpu-idle-states = <&mpu_gate>;
  54. };
  55. idle-states {
  56. mpu_gate: mpu_gate {
  57. compatible = "arm,idle-state";
  58. entry-latency-us = <40>;
  59. exit-latency-us = <90>;
  60. min-residency-us = <300>;
  61. ti,idle-wkup-m3;
  62. };
  63. };
  64. };
  65. cpu0_opp_table: opp-table {
  66. compatible = "operating-points-v2-ti-cpu";
  67. syscon = <&scm_conf>;
  68. /*
  69. * The three following nodes are marked with opp-suspend
  70. * because the can not be enabled simultaneously on a
  71. * single SoC.
  72. */
  73. opp50-300000000 {
  74. opp-hz = /bits/ 64 <300000000>;
  75. opp-microvolt = <950000 931000 969000>;
  76. opp-supported-hw = <0x06 0x0010>;
  77. opp-suspend;
  78. };
  79. opp100-275000000 {
  80. opp-hz = /bits/ 64 <275000000>;
  81. opp-microvolt = <1100000 1078000 1122000>;
  82. opp-supported-hw = <0x01 0x00FF>;
  83. opp-suspend;
  84. };
  85. opp100-300000000 {
  86. opp-hz = /bits/ 64 <300000000>;
  87. opp-microvolt = <1100000 1078000 1122000>;
  88. opp-supported-hw = <0x06 0x0020>;
  89. opp-suspend;
  90. };
  91. opp100-500000000 {
  92. opp-hz = /bits/ 64 <500000000>;
  93. opp-microvolt = <1100000 1078000 1122000>;
  94. opp-supported-hw = <0x01 0xFFFF>;
  95. };
  96. opp100-600000000 {
  97. opp-hz = /bits/ 64 <600000000>;
  98. opp-microvolt = <1100000 1078000 1122000>;
  99. opp-supported-hw = <0x06 0x0040>;
  100. };
  101. opp120-600000000 {
  102. opp-hz = /bits/ 64 <600000000>;
  103. opp-microvolt = <1200000 1176000 1224000>;
  104. opp-supported-hw = <0x01 0xFFFF>;
  105. };
  106. opp120-720000000 {
  107. opp-hz = /bits/ 64 <720000000>;
  108. opp-microvolt = <1200000 1176000 1224000>;
  109. opp-supported-hw = <0x06 0x0080>;
  110. };
  111. oppturbo-720000000 {
  112. opp-hz = /bits/ 64 <720000000>;
  113. opp-microvolt = <1260000 1234800 1285200>;
  114. opp-supported-hw = <0x01 0xFFFF>;
  115. };
  116. oppturbo-800000000 {
  117. opp-hz = /bits/ 64 <800000000>;
  118. opp-microvolt = <1260000 1234800 1285200>;
  119. opp-supported-hw = <0x06 0x0100>;
  120. };
  121. oppnitro-1000000000 {
  122. opp-hz = /bits/ 64 <1000000000>;
  123. opp-microvolt = <1325000 1298500 1351500>;
  124. opp-supported-hw = <0x04 0x0200>;
  125. };
  126. };
  127. pmu@4b000000 {
  128. compatible = "arm,cortex-a8-pmu";
  129. interrupts = <3>;
  130. reg = <0x4b000000 0x1000000>;
  131. ti,hwmods = "debugss";
  132. };
  133. /*
  134. * The soc node represents the soc top level view. It is used for IPs
  135. * that are not memory mapped in the MPU view or for the MPU itself.
  136. */
  137. soc {
  138. compatible = "ti,omap-infra";
  139. mpu {
  140. compatible = "ti,omap3-mpu";
  141. ti,hwmods = "mpu";
  142. pm-sram = <&pm_sram_code
  143. &pm_sram_data>;
  144. };
  145. };
  146. /*
  147. * XXX: Use a flat representation of the AM33XX interconnect.
  148. * The real AM33XX interconnect network is quite complex. Since
  149. * it will not bring real advantage to represent that in DT
  150. * for the moment, just use a fake OCP bus entry to represent
  151. * the whole bus hierarchy.
  152. */
  153. ocp {
  154. compatible = "simple-bus";
  155. #address-cells = <1>;
  156. #size-cells = <1>;
  157. ranges;
  158. ti,hwmods = "l3_main";
  159. l4_wkup: l4_wkup@44c00000 {
  160. wkup_m3: wkup_m3@100000 {
  161. compatible = "ti,am3352-wkup-m3";
  162. reg = <0x100000 0x4000>,
  163. <0x180000 0x2000>;
  164. reg-names = "umem", "dmem";
  165. ti,hwmods = "wkup_m3";
  166. ti,pm-firmware = "am335x-pm-firmware.elf";
  167. };
  168. };
  169. l4_per: interconnect@48000000 {
  170. };
  171. l4_fw: interconnect@47c00000 {
  172. };
  173. l4_fast: interconnect@4a000000 {
  174. };
  175. l4_mpuss: interconnect@4b140000 {
  176. };
  177. intc: interrupt-controller@48200000 {
  178. compatible = "ti,am33xx-intc";
  179. interrupt-controller;
  180. #interrupt-cells = <1>;
  181. reg = <0x48200000 0x1000>;
  182. };
  183. target-module@49000000 {
  184. compatible = "ti,sysc-omap4", "ti,sysc";
  185. reg = <0x49000000 0x4>;
  186. reg-names = "rev";
  187. clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
  188. clock-names = "fck";
  189. #address-cells = <1>;
  190. #size-cells = <1>;
  191. ranges = <0x0 0x49000000 0x10000>;
  192. edma: dma@0 {
  193. compatible = "ti,edma3-tpcc";
  194. reg = <0 0x10000>;
  195. reg-names = "edma3_cc";
  196. interrupts = <12 13 14>;
  197. interrupt-names = "edma3_ccint", "edma3_mperr",
  198. "edma3_ccerrint";
  199. dma-requests = <64>;
  200. #dma-cells = <2>;
  201. ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
  202. <&edma_tptc2 0>;
  203. ti,edma-memcpy-channels = <20 21>;
  204. };
  205. };
  206. target-module@49800000 {
  207. compatible = "ti,sysc-omap4", "ti,sysc";
  208. reg = <0x49800000 0x4>,
  209. <0x49800010 0x4>;
  210. reg-names = "rev", "sysc";
  211. ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
  212. ti,sysc-midle = <SYSC_IDLE_FORCE>;
  213. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  214. <SYSC_IDLE_SMART>;
  215. clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
  216. clock-names = "fck";
  217. #address-cells = <1>;
  218. #size-cells = <1>;
  219. ranges = <0x0 0x49800000 0x100000>;
  220. edma_tptc0: dma@0 {
  221. compatible = "ti,edma3-tptc";
  222. reg = <0 0x100000>;
  223. interrupts = <112>;
  224. interrupt-names = "edma3_tcerrint";
  225. };
  226. };
  227. target-module@49900000 {
  228. compatible = "ti,sysc-omap4", "ti,sysc";
  229. reg = <0x49900000 0x4>,
  230. <0x49900010 0x4>;
  231. reg-names = "rev", "sysc";
  232. ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
  233. ti,sysc-midle = <SYSC_IDLE_FORCE>;
  234. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  235. <SYSC_IDLE_SMART>;
  236. clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
  237. clock-names = "fck";
  238. #address-cells = <1>;
  239. #size-cells = <1>;
  240. ranges = <0x0 0x49900000 0x100000>;
  241. edma_tptc1: dma@0 {
  242. compatible = "ti,edma3-tptc";
  243. reg = <0 0x100000>;
  244. interrupts = <113>;
  245. interrupt-names = "edma3_tcerrint";
  246. };
  247. };
  248. target-module@49a00000 {
  249. compatible = "ti,sysc-omap4", "ti,sysc";
  250. reg = <0x49a00000 0x4>,
  251. <0x49a00010 0x4>;
  252. reg-names = "rev", "sysc";
  253. ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
  254. ti,sysc-midle = <SYSC_IDLE_FORCE>;
  255. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  256. <SYSC_IDLE_SMART>;
  257. clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
  258. clock-names = "fck";
  259. #address-cells = <1>;
  260. #size-cells = <1>;
  261. ranges = <0x0 0x49a00000 0x100000>;
  262. edma_tptc2: dma@0 {
  263. compatible = "ti,edma3-tptc";
  264. reg = <0 0x100000>;
  265. interrupts = <114>;
  266. interrupt-names = "edma3_tcerrint";
  267. };
  268. };
  269. i2c0: i2c@44e0b000 {
  270. compatible = "ti,omap4-i2c";
  271. #address-cells = <1>;
  272. #size-cells = <0>;
  273. ti,hwmods = "i2c1";
  274. reg = <0x44e0b000 0x1000>;
  275. interrupts = <70>;
  276. status = "disabled";
  277. };
  278. i2c1: i2c@4802a000 {
  279. compatible = "ti,omap4-i2c";
  280. #address-cells = <1>;
  281. #size-cells = <0>;
  282. ti,hwmods = "i2c2";
  283. reg = <0x4802a000 0x1000>;
  284. interrupts = <71>;
  285. status = "disabled";
  286. };
  287. i2c2: i2c@4819c000 {
  288. compatible = "ti,omap4-i2c";
  289. #address-cells = <1>;
  290. #size-cells = <0>;
  291. ti,hwmods = "i2c3";
  292. reg = <0x4819c000 0x1000>;
  293. interrupts = <30>;
  294. status = "disabled";
  295. };
  296. mmc1: mmc@48060000 {
  297. compatible = "ti,omap4-hsmmc";
  298. ti,hwmods = "mmc1";
  299. ti,dual-volt;
  300. ti,needs-special-reset;
  301. ti,needs-special-hs-handling;
  302. dmas = <&edma_xbar 24 0 0
  303. &edma_xbar 25 0 0>;
  304. dma-names = "tx", "rx";
  305. interrupts = <64>;
  306. reg = <0x48060000 0x1000>;
  307. status = "disabled";
  308. };
  309. mmc2: mmc@481d8000 {
  310. compatible = "ti,omap4-hsmmc";
  311. ti,hwmods = "mmc2";
  312. ti,needs-special-reset;
  313. dmas = <&edma 2 0
  314. &edma 3 0>;
  315. dma-names = "tx", "rx";
  316. interrupts = <28>;
  317. reg = <0x481d8000 0x1000>;
  318. status = "disabled";
  319. };
  320. mmc3: mmc@47810000 {
  321. compatible = "ti,omap4-hsmmc";
  322. ti,hwmods = "mmc3";
  323. ti,needs-special-reset;
  324. interrupts = <29>;
  325. reg = <0x47810000 0x1000>;
  326. status = "disabled";
  327. };
  328. wdt2: wdt@44e35000 {
  329. compatible = "ti,omap3-wdt";
  330. ti,hwmods = "wd_timer2";
  331. reg = <0x44e35000 0x1000>;
  332. interrupts = <91>;
  333. };
  334. usb: usb@47400000 {
  335. compatible = "ti,am33xx-usb";
  336. reg = <0x47400000 0x1000>;
  337. ranges;
  338. #address-cells = <1>;
  339. #size-cells = <1>;
  340. ti,hwmods = "usb_otg_hs";
  341. usb_ctrl_mod: control@44e10620 {
  342. compatible = "ti,am335x-usb-ctrl-module";
  343. reg = <0x44e10620 0x10
  344. 0x44e10648 0x4>;
  345. reg-names = "phy_ctrl", "wakeup";
  346. };
  347. usb0_phy: usb-phy@47401300 {
  348. compatible = "ti,am335x-usb-phy";
  349. reg = <0x47401300 0x100>;
  350. reg-names = "phy";
  351. ti,ctrl_mod = <&usb_ctrl_mod>;
  352. #phy-cells = <0>;
  353. };
  354. usb0: usb@47401000 {
  355. compatible = "ti,musb-am33xx";
  356. reg = <0x47401400 0x400
  357. 0x47401000 0x200>;
  358. reg-names = "mc", "control";
  359. interrupts = <18>;
  360. interrupt-names = "mc";
  361. dr_mode = "otg";
  362. mentor,multipoint = <1>;
  363. mentor,num-eps = <16>;
  364. mentor,ram-bits = <12>;
  365. mentor,power = <500>;
  366. phys = <&usb0_phy>;
  367. dmas = <&cppi41dma 0 0 &cppi41dma 1 0
  368. &cppi41dma 2 0 &cppi41dma 3 0
  369. &cppi41dma 4 0 &cppi41dma 5 0
  370. &cppi41dma 6 0 &cppi41dma 7 0
  371. &cppi41dma 8 0 &cppi41dma 9 0
  372. &cppi41dma 10 0 &cppi41dma 11 0
  373. &cppi41dma 12 0 &cppi41dma 13 0
  374. &cppi41dma 14 0 &cppi41dma 0 1
  375. &cppi41dma 1 1 &cppi41dma 2 1
  376. &cppi41dma 3 1 &cppi41dma 4 1
  377. &cppi41dma 5 1 &cppi41dma 6 1
  378. &cppi41dma 7 1 &cppi41dma 8 1
  379. &cppi41dma 9 1 &cppi41dma 10 1
  380. &cppi41dma 11 1 &cppi41dma 12 1
  381. &cppi41dma 13 1 &cppi41dma 14 1>;
  382. dma-names =
  383. "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
  384. "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
  385. "rx14", "rx15",
  386. "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
  387. "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
  388. "tx14", "tx15";
  389. };
  390. usb1_phy: usb-phy@47401b00 {
  391. compatible = "ti,am335x-usb-phy";
  392. reg = <0x47401b00 0x100>;
  393. reg-names = "phy";
  394. ti,ctrl_mod = <&usb_ctrl_mod>;
  395. #phy-cells = <0>;
  396. };
  397. usb1: usb@47401800 {
  398. compatible = "ti,musb-am33xx";
  399. reg = <0x47401c00 0x400
  400. 0x47401800 0x200>;
  401. reg-names = "mc", "control";
  402. interrupts = <19>;
  403. interrupt-names = "mc";
  404. dr_mode = "otg";
  405. mentor,multipoint = <1>;
  406. mentor,num-eps = <16>;
  407. mentor,ram-bits = <12>;
  408. mentor,power = <500>;
  409. phys = <&usb1_phy>;
  410. dmas = <&cppi41dma 15 0 &cppi41dma 16 0
  411. &cppi41dma 17 0 &cppi41dma 18 0
  412. &cppi41dma 19 0 &cppi41dma 20 0
  413. &cppi41dma 21 0 &cppi41dma 22 0
  414. &cppi41dma 23 0 &cppi41dma 24 0
  415. &cppi41dma 25 0 &cppi41dma 26 0
  416. &cppi41dma 27 0 &cppi41dma 28 0
  417. &cppi41dma 29 0 &cppi41dma 15 1
  418. &cppi41dma 16 1 &cppi41dma 17 1
  419. &cppi41dma 18 1 &cppi41dma 19 1
  420. &cppi41dma 20 1 &cppi41dma 21 1
  421. &cppi41dma 22 1 &cppi41dma 23 1
  422. &cppi41dma 24 1 &cppi41dma 25 1
  423. &cppi41dma 26 1 &cppi41dma 27 1
  424. &cppi41dma 28 1 &cppi41dma 29 1>;
  425. dma-names =
  426. "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
  427. "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
  428. "rx14", "rx15",
  429. "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
  430. "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
  431. "tx14", "tx15";
  432. };
  433. cppi41dma: dma-controller@2000 {
  434. compatible = "ti,am3359-cppi41";
  435. reg = <0x0000 0x1000>,
  436. <0x2000 0x1000>,
  437. <0x3000 0x1000>,
  438. <0x4000 0x4000>;
  439. reg-names = "glue", "controller", "scheduler", "queuemgr";
  440. interrupts = <17>;
  441. interrupt-names = "glue";
  442. #dma-cells = <2>;
  443. #dma-channels = <30>;
  444. #dma-requests = <256>;
  445. };
  446. };
  447. mac: ethernet@4a100000 {
  448. compatible = "ti,am335x-cpsw","ti,cpsw";
  449. ti,hwmods = "cpgmac0";
  450. clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
  451. clock-names = "fck", "cpts";
  452. cpdma_channels = <8>;
  453. ale_entries = <1024>;
  454. bd_ram_size = <0x2000>;
  455. mac_control = <0x20>;
  456. slaves = <2>;
  457. active_slave = <0>;
  458. cpts_clock_mult = <0x80000000>;
  459. cpts_clock_shift = <29>;
  460. reg = <0x4a100000 0x800
  461. 0x4a101200 0x100>;
  462. #address-cells = <1>;
  463. #size-cells = <1>;
  464. /*
  465. * c0_rx_thresh_pend
  466. * c0_rx_pend
  467. * c0_tx_pend
  468. * c0_misc_pend
  469. */
  470. interrupts = <40 41 42 43>;
  471. ranges;
  472. syscon = <&scm_conf>;
  473. status = "disabled";
  474. davinci_mdio: mdio@4a101000 {
  475. compatible = "ti,cpsw-mdio","ti,davinci_mdio";
  476. #address-cells = <1>;
  477. #size-cells = <0>;
  478. ti,hwmods = "davinci_mdio";
  479. bus_freq = <1000000>;
  480. reg = <0x4a101000 0x100>;
  481. status = "disabled";
  482. };
  483. cpsw_emac0: slave@4a100200 {
  484. /* Filled in by U-Boot */
  485. mac-address = [ 00 00 00 00 00 00 ];
  486. };
  487. cpsw_emac1: slave@4a100300 {
  488. /* Filled in by U-Boot */
  489. mac-address = [ 00 00 00 00 00 00 ];
  490. };
  491. phy_sel: cpsw-phy-sel@44e10650 {
  492. compatible = "ti,am3352-cpsw-phy-sel";
  493. reg= <0x44e10650 0x4>;
  494. reg-names = "gmii-sel";
  495. };
  496. };
  497. ocmcram: sram@40300000 {
  498. compatible = "mmio-sram";
  499. reg = <0x40300000 0x10000>; /* 64k */
  500. ranges = <0x0 0x40300000 0x10000>;
  501. #address-cells = <1>;
  502. #size-cells = <1>;
  503. pm_sram_code: pm-code-sram@0 {
  504. compatible = "ti,sram";
  505. reg = <0x0 0x1000>;
  506. protect-exec;
  507. };
  508. pm_sram_data: pm-data-sram@1000 {
  509. compatible = "ti,sram";
  510. reg = <0x1000 0x1000>;
  511. pool;
  512. };
  513. };
  514. emif: emif@4c000000 {
  515. compatible = "ti,emif-am3352";
  516. reg = <0x4c000000 0x1000000>;
  517. ti,hwmods = "emif";
  518. interrupts = <101>;
  519. sram = <&pm_sram_code
  520. &pm_sram_data>;
  521. ti,no-idle;
  522. };
  523. gpmc: gpmc@50000000 {
  524. compatible = "ti,am3352-gpmc";
  525. ti,hwmods = "gpmc";
  526. ti,no-idle-on-init;
  527. reg = <0x50000000 0x2000>;
  528. interrupts = <100>;
  529. dmas = <&edma 52 0>;
  530. dma-names = "rxtx";
  531. gpmc,num-cs = <7>;
  532. gpmc,num-waitpins = <2>;
  533. #address-cells = <2>;
  534. #size-cells = <1>;
  535. interrupt-controller;
  536. #interrupt-cells = <2>;
  537. gpio-controller;
  538. #gpio-cells = <2>;
  539. status = "disabled";
  540. };
  541. sham_target: target-module@53100000 {
  542. compatible = "ti,sysc-omap3-sham", "ti,sysc";
  543. reg = <0x53100100 0x4>,
  544. <0x53100110 0x4>,
  545. <0x53100114 0x4>;
  546. reg-names = "rev", "sysc", "syss";
  547. ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  548. SYSC_OMAP2_AUTOIDLE)>;
  549. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  550. <SYSC_IDLE_NO>,
  551. <SYSC_IDLE_SMART>;
  552. ti,syss-mask = <1>;
  553. /* Domains (P, C): per_pwrdm, l3_clkdm */
  554. clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
  555. clock-names = "fck";
  556. #address-cells = <1>;
  557. #size-cells = <1>;
  558. ranges = <0x0 0x53100000 0x1000>;
  559. sham: sham@0 {
  560. compatible = "ti,omap4-sham";
  561. reg = <0 0x200>;
  562. interrupts = <109>;
  563. dmas = <&edma 36 0>;
  564. dma-names = "rx";
  565. };
  566. };
  567. aes_target: target-module@53500000 {
  568. compatible = "ti,sysc-omap2", "ti,sysc";
  569. reg = <0x53500080 0x4>,
  570. <0x53500084 0x4>,
  571. <0x53500088 0x4>;
  572. reg-names = "rev", "sysc", "syss";
  573. ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  574. SYSC_OMAP2_AUTOIDLE)>;
  575. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  576. <SYSC_IDLE_NO>,
  577. <SYSC_IDLE_SMART>,
  578. <SYSC_IDLE_SMART_WKUP>;
  579. ti,syss-mask = <1>;
  580. /* Domains (P, C): per_pwrdm, l3_clkdm */
  581. clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
  582. clock-names = "fck";
  583. #address-cells = <1>;
  584. #size-cells = <1>;
  585. ranges = <0x0 0x53500000 0x1000>;
  586. aes: aes@0 {
  587. compatible = "ti,omap4-aes";
  588. reg = <0 0xa0>;
  589. interrupts = <103>;
  590. dmas = <&edma 6 0>,
  591. <&edma 5 0>;
  592. dma-names = "tx", "rx";
  593. };
  594. };
  595. target-module@56000000 {
  596. compatible = "ti,sysc-omap4", "ti,sysc";
  597. reg = <0x5600fe00 0x4>,
  598. <0x5600fe10 0x4>;
  599. reg-names = "rev", "sysc";
  600. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  601. <SYSC_IDLE_NO>,
  602. <SYSC_IDLE_SMART>;
  603. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  604. <SYSC_IDLE_NO>,
  605. <SYSC_IDLE_SMART>;
  606. clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
  607. clock-names = "fck";
  608. resets = <&prm_gfx 0>;
  609. reset-names = "rstctrl";
  610. #address-cells = <1>;
  611. #size-cells = <1>;
  612. ranges = <0 0x56000000 0x1000000>;
  613. /*
  614. * Closed source PowerVR driver, no child device
  615. * binding or driver in mainline
  616. */
  617. };
  618. };
  619. };
  620. #include "am33xx-l4.dtsi"
  621. #include "am33xx-clocks.dtsi"
  622. &prcm {
  623. prm_per: prm@c00 {
  624. compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
  625. reg = <0xc00 0x100>;
  626. #reset-cells = <1>;
  627. };
  628. prm_wkup: prm@d00 {
  629. compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
  630. reg = <0xd00 0x100>;
  631. #reset-cells = <1>;
  632. };
  633. prm_device: prm@f00 {
  634. compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
  635. reg = <0xf00 0x100>;
  636. #reset-cells = <1>;
  637. };
  638. prm_gfx: prm@1100 {
  639. compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
  640. reg = <0x1100 0x100>;
  641. #reset-cells = <1>;
  642. };
  643. };