sf_vop.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
  4. * Copyright (c) 2015 Google, Inc
  5. * Copyright 2014 Rockchip Inc.
  6. */
  7. #include <common.h>
  8. #include <display.h>
  9. #include <dm.h>
  10. #include <dm/uclass.h>
  11. #include <dm/device.h>
  12. #include <dm/uclass-internal.h>
  13. #include <dm/device-internal.h>
  14. #include <dm/lists.h>
  15. #include <regmap.h>
  16. #include <syscon.h>
  17. #include <video.h>
  18. #include <asm/global_data.h>
  19. #include <asm/io.h>
  20. #include <linux/delay.h>
  21. #include <power-domain-uclass.h>
  22. #include <power-domain.h>
  23. #include <clk.h>
  24. #include <video_bridge.h>
  25. #include <power/pmic.h>
  26. #include <panel.h>
  27. #include "sf_vop.h"
  28. #include "sf_mipi.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. static void iotrace_writel(ulong value, void *ptr)
  31. {
  32. //printf("writel( 0x%08x, %p ) -- 0x%08x\n", value, ptr, readl(ptr));
  33. //readl(ptr);
  34. mdelay(10);
  35. writel(value, ptr);
  36. }
  37. static int sf_vop_power_off(struct udevice *dev)
  38. {
  39. struct udevice *dev_power;
  40. struct power_domain_ops *ops;
  41. struct power_domain power_domain;
  42. int ret;
  43. if (!(gd->flags & GD_FLG_RELOC))
  44. return 0;
  45. ret = uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev_power);
  46. if (ret)
  47. return ret;
  48. ret = device_probe(dev_power);
  49. if (ret) {
  50. pr_err("%s: device '%s' display won't probe (ret=%d)\n",
  51. __func__, dev_power->name, ret);
  52. return ret;
  53. }
  54. ops = (struct power_domain_ops *)dev_power->driver->ops;
  55. power_domain.dev = dev_power;
  56. power_domain.id = 4;
  57. ret = ops->off(&power_domain);
  58. if (ret) {
  59. pr_err("ops->0ff() failed: %d\n", ret);
  60. return ret;
  61. }
  62. return 0;
  63. }
  64. static int sf_vop_power(struct udevice *dev)
  65. {
  66. struct udevice *dev_power;
  67. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB)
  68. struct udevice *dev_pmic;
  69. #endif
  70. struct power_domain_ops *ops;
  71. struct power_domain power_domain;
  72. int ret;
  73. if (!(gd->flags & GD_FLG_RELOC))
  74. return 0;
  75. ret = uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev_power);
  76. if (ret)
  77. return ret;
  78. ret = device_probe(dev_power);
  79. if (ret) {
  80. pr_err("%s: device '%s' display won't probe (ret=%d)\n",
  81. __func__, dev_power->name, ret);
  82. return ret;
  83. }
  84. ops = (struct power_domain_ops *)dev_power->driver->ops;
  85. power_domain.dev = dev_power;
  86. power_domain.id = 4;
  87. ret = ops->request(&power_domain);
  88. if (ret) {
  89. pr_err("ops->request() failed: %d\n", ret);
  90. return ret;
  91. }
  92. ret = ops->on(&power_domain);
  93. if (ret) {
  94. pr_err("ops->on() failed: %d\n", ret);
  95. return ret;
  96. }
  97. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB)
  98. ret = uclass_get_device_by_driver(UCLASS_PMIC,
  99. DM_DRIVER_GET(pmic_starfive), &dev_pmic);
  100. if (ret) {
  101. pr_err("failed to find PMIC: %d\n", ret);
  102. return ret;
  103. }
  104. ret = pmic_clrsetbits(dev_pmic, POWER_SW_0_REG, 0x3f, 0x3f);
  105. if (ret) {
  106. pr_err("failed to update SD control register: %d", ret);
  107. return ret;
  108. }
  109. #endif
  110. return 0;
  111. }
  112. static int vout_get_rst_clock_resources(struct udevice *dev)
  113. {
  114. struct sf_vop_priv *priv = dev_get_priv(dev);
  115. int ret;
  116. ret = clk_get_by_name(dev, "disp_axi", &priv->disp_axi);
  117. if (ret) {
  118. pr_err("clk_get_by_name(noc_disp) failed: %d", ret);
  119. return ret;
  120. }
  121. ret = clk_get_by_name(dev, "vout_src", &priv->vout_src);
  122. if (ret) {
  123. pr_err("clk_get_by_name(vout_src) failed: %d\n", ret);
  124. return ret;
  125. }
  126. ret = clk_get_by_name(dev, "top_vout_axi", &priv->top_vout_axi);
  127. if (ret) {
  128. pr_err("clk_get_by_name(top_vout_axi) failed: %d\n", ret);
  129. return ret;
  130. }
  131. ret = clk_get_by_name(dev, "top_vout_ahb", &priv->top_vout_ahb);
  132. if (ret) {
  133. pr_err("clk_get_by_name(top_vout_ahb) failed: %d\n", ret);
  134. return ret;
  135. }
  136. ret = clk_get_by_name(dev, "dc_pix0", &priv->dc_pix0);
  137. if (ret) {
  138. pr_err("clk_get_by_name(dc_pix0) failed: %d\n", ret);
  139. return ret;
  140. }
  141. ret = clk_get_by_name(dev, "dc_pix1", &priv->dc_pix1);
  142. if (ret) {
  143. pr_err("clk_get_by_name(dc_pix1) failed: %d\n", ret);
  144. return ret;
  145. }
  146. ret = clk_get_by_name(dev, "dc_axi", &priv->dc_axi);
  147. if (ret) {
  148. pr_err("clk_get_by_name(dc_axi) failed: %d\n", ret);
  149. return ret;
  150. }
  151. ret = clk_get_by_name(dev, "dc_core", &priv->dc_core);
  152. if (ret) {
  153. pr_err("clk_get_by_name(dc_core) failed: %d\n", ret);
  154. return ret;
  155. }
  156. ret = clk_get_by_name(dev, "dc_ahb", &priv->dc_ahb);
  157. if (ret) {
  158. pr_err("clk_get_by_name(dc_ahb) failed: %d\n", ret);
  159. return ret;
  160. }
  161. ret = clk_get_by_name(dev, "top_vout_lcd", &priv->top_vout_lcd);
  162. if (ret) {
  163. pr_err("clk_get_by_name(top_vout_lcd) failed: %d\n", ret);
  164. return ret;
  165. }
  166. ret = clk_get_by_name(dev, "hdmitx0_pixelclk", &priv->hdmitx0_pixelclk);
  167. if (ret) {
  168. pr_err("clk_get_by_name(hdmitx0_pixelclk) failed: %d\n", ret);
  169. return ret;
  170. }
  171. ret = clk_get_by_name(dev, "dc8200_pix0", &priv->dc_pix_src);
  172. if (ret) {
  173. pr_err("clk_get_by_name(dc_pix_src) failed: %d\n", ret);
  174. return ret;
  175. }
  176. ret = clk_get_by_name(dev, "dc8200_pix0_out", &priv->dc_pix0_out);
  177. if (ret) {
  178. pr_err("clk_get_by_name(dc_pix0_out) failed: %d\n", ret);
  179. return ret;
  180. }
  181. ret = clk_get_by_name(dev, "dc8200_pix1_out", &priv->dc_pix1_out);
  182. if (ret) {
  183. pr_err("clk_get_by_name(dc_ahb) failed: %d\n", ret);
  184. return ret;
  185. }
  186. ret = reset_get_by_name(dev, "rst_vout_src", &priv->rst_vout_src);
  187. if (ret) {
  188. pr_err("failed to get rst_vout_src reset (ret=%d)\n", ret);
  189. return ret;
  190. }
  191. ret = reset_get_by_name(dev, "rst_axi", &priv->dc8200_rst_axi);
  192. if (ret) {
  193. pr_err("failed to get dc8200_rst_axi reset (ret=%d)\n", ret);
  194. return ret;
  195. }
  196. ret = reset_get_by_name(dev, "rst_ahb", &priv->dc8200_rst_ahb);
  197. if (ret) {
  198. pr_err("failed to get ahb reset (ret=%d)\n", ret);
  199. return ret;
  200. }
  201. ret = reset_get_by_name(dev, "rst_core", &priv->dc8200_rst_core);
  202. if (ret) {
  203. pr_err("failed to get dc8200_rst_core reset (ret=%d)\n", ret);
  204. return ret;
  205. }
  206. ret = reset_get_by_name(dev, "rst_noc_disp", &priv->noc_disp);
  207. if (ret) {
  208. pr_err("failed to get noc_disp reset (ret=%d)\n", ret);
  209. return ret;
  210. }
  211. debug("%s: OK\n", __func__);
  212. return 0;
  213. }
  214. int dc_hw_init(struct udevice *dev)
  215. {
  216. struct sf_vop_priv *priv = dev_get_priv(dev);
  217. u32 revision = readl(priv->regs_hi+DC_HW_REVISION);
  218. u32 cid = readl(priv->regs_hi+DC_HW_CHIP_CID);
  219. debug("%s: revision = %08x\n", __func__,revision);
  220. debug("%s: cid = %08x\n", __func__,cid);
  221. return 0;
  222. }
  223. static int vout_probe_resources_jh7110(struct udevice *dev)
  224. {
  225. struct sf_vop_priv *priv = dev_get_priv(dev);
  226. int ret;
  227. ret = vout_get_rst_clock_resources(dev);
  228. ret = clk_enable(&priv->disp_axi);
  229. if (ret < 0) {
  230. pr_err("clk_enable(noc_disp) failed: %d\n", ret);
  231. return ret;
  232. }
  233. ret = reset_deassert(&priv->noc_disp);
  234. if (ret) {
  235. pr_err("failed to deassert noc_disp reset (ret=%d)\n", ret);
  236. goto free_clock_vout_src;
  237. }
  238. ret = clk_enable(&priv->vout_src);
  239. if (ret < 0) {
  240. pr_err("clk_enable(vout_src) failed: %d\n", ret);
  241. goto free_clock_vout_src;
  242. }
  243. ret = clk_enable(&priv->top_vout_axi);
  244. if (ret < 0) {
  245. pr_err("clk_enable(top_vout_axi) failed: %d\n", ret);
  246. goto free_clock_top_vout_axi;
  247. }
  248. ret = clk_enable(&priv->top_vout_ahb);
  249. if (ret < 0) {
  250. pr_err("clk_enable(top_vout_ahb) failed: %d\n", ret);
  251. goto free_clock_top_vout_ahb;
  252. }
  253. ret = reset_deassert(&priv->rst_vout_src);
  254. if (ret) {
  255. pr_err("failed to deassert rst_vout_src reset (ret=%d)\n", ret);
  256. goto free_clock_dc_pix0;
  257. }
  258. ret = clk_enable(&priv->dc_pix0);
  259. if (ret < 0) {
  260. pr_err("clk_enable(dc_pix0) failed: %d\n", ret);
  261. goto free_clock_dc_pix0;
  262. }
  263. ret = clk_enable(&priv->dc_pix1);
  264. if (ret < 0) {
  265. pr_err("clk_enable(dc_pix1) failed: %d\n", ret);
  266. goto free_clock_dc_pix1;
  267. }
  268. ret = clk_enable(&priv->dc_axi);
  269. if (ret < 0) {
  270. pr_err("clk_enable(dc_axi) failed: %d\n", ret);
  271. goto free_clock_dc_axi;
  272. }
  273. ret = clk_enable(&priv->dc_core);
  274. if (ret < 0) {
  275. pr_err("clk_enable(dc_core) failed: %d\n", ret);
  276. goto free_clock_dc_core;
  277. }
  278. ret = clk_enable(&priv->dc_ahb);
  279. if (ret < 0) {
  280. pr_err("clk_enable(dc_ahb) failed: %d\n", ret);
  281. goto free_clock_dc_ahb;
  282. }
  283. ret = clk_enable(&priv->hdmitx0_pixelclk);
  284. if (ret < 0) {
  285. pr_err("clk_enable(hdmitx0_pixelclk) failed: %d\n", ret);
  286. goto free_clock_hdmitx0_pixelclk;
  287. }
  288. ret = reset_deassert(&priv->dc8200_rst_axi);
  289. if (ret) {
  290. pr_err("failed to deassert dc8200_rst_axi reset (ret=%d)\n", ret);
  291. goto free_reset_dc8200;
  292. }
  293. ret = reset_deassert(&priv->dc8200_rst_core);
  294. if (ret) {
  295. pr_err("failed to deassert dc8200_rst_axi reset (ret=%d)\n", ret);
  296. goto free_reset_dc8200;
  297. }
  298. ret = reset_deassert(&priv->dc8200_rst_ahb);
  299. if (ret) {
  300. pr_err("failed to deassert dc8200_rst_ahb reset (ret=%d)\n", ret);
  301. goto free_reset_dc8200;
  302. }
  303. debug("%s: OK\n", __func__);
  304. return 0;
  305. free_reset_dc8200:
  306. clk_disable(&priv->hdmitx0_pixelclk);
  307. free_clock_hdmitx0_pixelclk:
  308. clk_disable(&priv->dc_ahb);
  309. free_clock_dc_ahb:
  310. clk_disable(&priv->dc_core);
  311. free_clock_dc_core:
  312. clk_disable(&priv->dc_axi);
  313. free_clock_dc_axi:
  314. clk_disable(&priv->dc_pix1);
  315. free_clock_dc_pix1:
  316. clk_disable(&priv->dc_pix0);
  317. free_clock_dc_pix0:
  318. clk_disable(&priv->top_vout_ahb);
  319. free_clock_top_vout_ahb:
  320. clk_disable(&priv->top_vout_axi);
  321. free_clock_top_vout_axi:
  322. clk_disable(&priv->vout_src);
  323. free_clock_vout_src:
  324. clk_disable(&priv->disp_axi);
  325. return ret;
  326. }
  327. static int sf_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
  328. {
  329. struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
  330. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  331. struct sf_vop_priv *priv = dev_get_priv(dev);
  332. int vop_id, remote_vop_id;
  333. struct display_timing timing;
  334. struct udevice *disp;
  335. int ret;
  336. u32 remote_phandle;
  337. ofnode remote;
  338. const char *compat;
  339. struct display_plat *disp_uc_plat;
  340. debug("%s(%s, 0x%lx, %s)\n", __func__,
  341. dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
  342. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB) || CONFIG_IS_ENABLED(TARGET_STARFIVE_VISIONFIVE2)
  343. struct udevice *panel = NULL;
  344. #endif
  345. ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
  346. if (ret)
  347. return ret;
  348. remote = ofnode_get_by_phandle(remote_phandle);
  349. if (!ofnode_valid(remote))
  350. return -EINVAL;
  351. remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
  352. uc_priv->bpix = VIDEO_BPP32;
  353. debug("remote_vop_id %d\n", remote_vop_id);
  354. /*
  355. * The remote-endpoint references into a subnode of the encoder
  356. * (i.e. HDMI, MIPI, etc.) with the DTS looking something like
  357. * the following (assume 'hdmi_in_vopl' to be referenced):
  358. *
  359. * hdmi: hdmi@ff940000 {
  360. * ports {
  361. * hdmi_in: port {
  362. * hdmi_in_vopb: endpoint@0 { ... };
  363. * hdmi_in_vopl: endpoint@1 { ... };
  364. * }
  365. * }
  366. * }
  367. *
  368. * The original code had 3 steps of "walking the parent", but
  369. * a much better (as in: less likely to break if the DTS
  370. * changes) way of doing this is to "find the enclosing device
  371. * of UCLASS_DISPLAY".
  372. */
  373. while (ofnode_valid(remote)) {
  374. remote = ofnode_get_parent(remote);
  375. if (!ofnode_valid(remote)) {
  376. debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
  377. __func__, dev_read_name(dev));
  378. return -EINVAL;
  379. }
  380. debug("%s(%s, 0x%lx,remote %s)\n", __func__,
  381. dev_read_name(dev), fbbase, ofnode_get_name(remote));
  382. uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
  383. if (disp)
  384. break;
  385. uclass_find_device_by_ofnode(UCLASS_VIDEO_BRIDGE, remote, &disp);
  386. if (disp)
  387. break;
  388. };
  389. compat = ofnode_get_property(remote, "compatible", NULL);
  390. if (!compat) {
  391. debug("%s(%s): Failed to find compatible property\n",
  392. __func__, dev_read_name(dev));
  393. return -EINVAL;
  394. }
  395. if (strstr(compat, "edp")) {
  396. vop_id = VOP_MODE_EDP;
  397. } else if (strstr(compat, "mipi")) {
  398. vop_id = VOP_MODE_MIPI;
  399. } else if (strstr(compat, "hdmi")) {
  400. vop_id = VOP_MODE_HDMI;
  401. } else if (strstr(compat, "cdn-dp")) {
  402. vop_id = VOP_MODE_DP;
  403. } else if (strstr(compat, "lvds")) {
  404. vop_id = VOP_MODE_LVDS;
  405. } else {
  406. debug("%s(%s): Failed to find vop mode for %s\n",
  407. __func__, dev_read_name(dev), compat);
  408. return -EINVAL;
  409. }
  410. debug("vop_id %d,compat = %s\n", vop_id,compat);
  411. if(vop_id == VOP_MODE_HDMI)
  412. {
  413. disp_uc_plat = dev_get_uclass_plat(disp);
  414. debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
  415. disp_uc_plat->source_id = remote_vop_id;
  416. disp_uc_plat->src_dev = dev;
  417. ret = device_probe(disp);
  418. if (ret) {
  419. debug("%s: device '%s' display won't probe (ret=%d)\n",
  420. __func__, dev->name, ret);
  421. return ret;
  422. }
  423. ret = display_enable(disp, 1 << VIDEO_BPP32, &timing);
  424. if (ret) {
  425. debug("%s: Failed to read timings\n", __func__);
  426. return ret;
  427. }
  428. int err = clk_set_parent(&priv->dc_pix0, &priv->dc_pix_src);
  429. if (err) {
  430. debug("failed to set %s clock as %s's parent\n",
  431. priv->dc_pix_src.dev->name, priv->dc_pix0.dev->name);
  432. return err;
  433. }
  434. ulong new_rate = clk_set_rate(&priv->dc_pix_src, 148500000);
  435. debug("new_rate %ld\n", new_rate);
  436. dc_hw_init(dev);
  437. uc_priv->xsize = 1920;
  438. uc_priv->ysize = 1080;
  439. writel(0xc0001fff, priv->regs_hi+0x00000014);
  440. writel(0x00002000, priv->regs_hi+0x00001cc0);
  441. //writel(uc_plat->base+0x1fa400, priv->regs_hi+0x00001530);
  442. writel(0x00000000, priv->regs_hi+0x00001800);
  443. writel(0x00000000, priv->regs_hi+0x000024d8);
  444. writel(0x021c0780, priv->regs_hi+0x000024e0);
  445. writel(0x021c0780, priv->regs_hi+0x00001810);
  446. writel(uc_plat->base, priv->regs_hi+0x00001400);
  447. writel(0x00001e00, priv->regs_hi+0x00001408);
  448. writel(0x00000f61, priv->regs_hi+0x00001ce8);
  449. writel(0x00002042, priv->regs_hi+0x00002510);
  450. writel(0x808a3156, priv->regs_hi+0x00002508);
  451. writel(0x8008e1b2, priv->regs_hi+0x00002500);
  452. writel(0x18000000, priv->regs_hi+0x00001518);
  453. writel(0x00003000, priv->regs_hi+0x00001cc0);
  454. writel(0x00060000, priv->regs_hi+0x00001540);
  455. writel(0x00000001, priv->regs_hi+0x00002540);
  456. writel(0x80060000, priv->regs_hi+0x00001540);
  457. writel(0x00060000, priv->regs_hi+0x00001544);
  458. writel(0x00000002, priv->regs_hi+0x00002544);
  459. writel(0x80060000, priv->regs_hi+0x00001544);
  460. writel(0x00060000, priv->regs_hi+0x00001548);
  461. writel(0x0000000c, priv->regs_hi+0x00002548);
  462. writel(0x80060000, priv->regs_hi+0x00001548);
  463. writel(0x00060000, priv->regs_hi+0x0000154c);
  464. writel(0x0000000d, priv->regs_hi+0x0000254c);
  465. writel(0x80060000, priv->regs_hi+0x0000154c);
  466. writel(0x00000001, priv->regs_hi+0x00002518);
  467. writel(0x00000000, priv->regs_hi+0x00001a28);
  468. writel(0x08980780, priv->regs_hi+0x00001430);
  469. writel(0x440207d8, priv->regs_hi+0x00001438);
  470. writel(0x04650438, priv->regs_hi+0x00001440);
  471. writel(0x4220843c, priv->regs_hi+0x00001448);
  472. writel(0x00000000, priv->regs_hi+0x000014b0);
  473. writel(0x000000d2, priv->regs_hi+0x00001cd0);
  474. writel(0x00000005, priv->regs_hi+0x000014b8);
  475. writel(0x00000052, priv->regs_hi+0x000014d0);
  476. writel(0xdeadbeef, priv->regs_hi+0x00001528);
  477. writel(0x00001111, priv->regs_hi+0x00001418);
  478. writel(0x00000000, priv->regs_hi+0x00001410);
  479. writel(0x00000000, priv->regs_hi+0x00002518);
  480. writel(0x00200024, priv->regs_hi+0x00001468);
  481. writel(0x00000000, priv->regs_hi+0x00001484);
  482. writel(0x00200024, priv->regs_hi+0x00001468);
  483. writel(0x00000c24, priv->regs_hi+0x000024e8);
  484. writel(0x00000000, priv->regs_hi+0x000024fc);
  485. writel(0x00000c24, priv->regs_hi+0x000024e8);
  486. writel(0x00000001, priv->regs_hi+0x00001ccc);
  487. priv->hdmi_logo = true;
  488. return 0;
  489. }
  490. if(vop_id == VOP_MODE_MIPI)
  491. {
  492. ret = device_probe(disp);
  493. if (ret) {
  494. debug("%s: device '%s' display won't probe (ret=%d)\n",
  495. __func__, dev->name, ret);
  496. return ret;
  497. }
  498. ret = video_bridge_attach(disp);
  499. if (ret) {
  500. debug("fail to attach bridge\n");
  501. return ret;
  502. }
  503. ret = video_bridge_set_backlight(disp, 80);
  504. if (ret) {
  505. debug("dp: failed to set backlight\n");
  506. return ret;
  507. }
  508. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB) || CONFIG_IS_ENABLED(TARGET_STARFIVE_VISIONFIVE2)
  509. ret = uclass_first_device_err(UCLASS_PANEL, &panel);
  510. if (ret) {
  511. if (ret != -ENODEV)
  512. debug("panel device error %d\n", ret);
  513. return ret;
  514. }
  515. ret = panel_get_display_timing(panel, &timing);
  516. if (ret) {
  517. ret = ofnode_decode_display_timing(dev_ofnode(panel),
  518. 0, &timing);
  519. if (ret) {
  520. debug("decode display timing error %d\n", ret);
  521. return ret;
  522. }
  523. }
  524. #endif
  525. int err = clk_set_parent(&priv->dc_pix0, &priv->dc_pix_src);
  526. if (err) {
  527. debug("failed to set %s clock as %s's parent\n",
  528. priv->dc_pix_src.dev->name, priv->dc_pix0.dev->name);
  529. return err;
  530. }
  531. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB) || CONFIG_IS_ENABLED(TARGET_STARFIVE_VISIONFIVE2)
  532. ulong new_rate = clk_set_rate(&priv->dc_pix_src, timing.pixelclock.typ);
  533. debug("new_rate %ld\n", new_rate);
  534. #endif
  535. dc_hw_init(dev);
  536. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB) || CONFIG_IS_ENABLED(TARGET_STARFIVE_VISIONFIVE2)
  537. uc_priv->xsize = timing.hactive.typ;
  538. uc_priv->ysize = timing.vactive.typ;
  539. if (IS_ENABLED(CONFIG_VIDEO_COPY))
  540. uc_plat->copy_base = uc_plat->base - uc_plat->size / 2;
  541. #else
  542. struct dsi_sf_priv *private = dev_get_priv(disp);
  543. uc_priv->xsize = private->timings.hactive.typ;
  544. uc_priv->ysize = private->timings.vactive.typ;
  545. debug("uc_priv->xsize %d\n", uc_priv->xsize);
  546. debug("uc_priv->ysize %d\n", uc_priv->ysize);
  547. if(uc_priv->xsize == 800)
  548. {
  549. ulong new_rate = clk_set_rate(&priv->dc_pix_src, 29700000);
  550. debug("new_rate %ld\n", new_rate);
  551. }
  552. if(uc_priv->xsize == 1920)
  553. {
  554. ulong new_rate = clk_set_rate(&priv->dc_pix_src, 148500000);
  555. debug("new_rate %ld\n", new_rate);
  556. }
  557. #endif
  558. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB) || CONFIG_IS_ENABLED(TARGET_STARFIVE_VISIONFIVE2)
  559. writel(0xc0001fff, priv->regs_hi+0x00000014); //csr_reg
  560. writel(0x000000e8, priv->regs_hi+0x00001a38); //csr_reg
  561. writel(0x00002000, priv->regs_hi+0x00001cc0); //csr_reg
  562. writel(0x00000000, priv->regs_hi+0x000024d8); //csr_reg
  563. writel(0x03c00438, priv->regs_hi+0x000024e0); //csr_reg
  564. writel(0x03c00438, priv->regs_hi+0x00001810); //csr_reg
  565. writel(uc_plat->base, priv->regs_hi+0x00001400);
  566. writel(0x000010e0, priv->regs_hi+0x00001408); //csr_reg
  567. writel(0x000fb00b, priv->regs_hi+0x00001ce8); //csr_reg
  568. writel(0x0000a9a3, priv->regs_hi+0x00002510); //csr_reg
  569. writel(0x2c4e6f06, priv->regs_hi+0x00002508); //csr_reg
  570. writel(0xe6daec4f, priv->regs_hi+0x00002500); //csr_reg
  571. writel(0x18220000, priv->regs_hi+0x00001518); //csr_reg
  572. writel(0x00003000, priv->regs_hi+0x00001cc0); //csr_reg
  573. writel(0x00030000, priv->regs_hi+0x00001cc4); //csr_reg
  574. writel(0x00030000, priv->regs_hi+0x00001cc4); //csr_reg
  575. writel(0x00050c1a, priv->regs_hi+0x00001540); //csr_reg
  576. writel(0x00000001, priv->regs_hi+0x00002540); //csr_reg
  577. writel(0x00050c1a, priv->regs_hi+0x00001540); //csr_reg
  578. writel(0x4016120c, priv->regs_hi+0x00001544); //csr_reg
  579. writel(0x00000002, priv->regs_hi+0x00002544); //csr_reg
  580. writel(0x4016120c, priv->regs_hi+0x00001544); //csr_reg
  581. writel(0x001b1208, priv->regs_hi+0x00001548); //csr_reg
  582. writel(0x00000004, priv->regs_hi+0x00002548); //csr_reg
  583. writel(0x001b1208, priv->regs_hi+0x00001548); //csr_reg
  584. writel(0x0016110e, priv->regs_hi+0x0000154c); //csr_reg
  585. writel(0x00000005, priv->regs_hi+0x0000254c); //csr_reg
  586. writel(0x0016110e, priv->regs_hi+0x0000154c); //csr_reg
  587. writel(0x00000001, priv->regs_hi+0x00002518); //csr_reg
  588. writel(0x00000000, priv->regs_hi+0x00001a28); //csr_reg
  589. writel(0x03840320, priv->regs_hi+0x00001430); //csr_reg, hsize, htotal
  590. writel(0xc1bf837a, priv->regs_hi+0x00001438); //csr_reg, hsize blanking
  591. writel(0x022601e0, priv->regs_hi+0x00001440); //csr_reg, vsize
  592. writel(0xc110021c, priv->regs_hi+0x00001448); //csr_reg, vsize blanking
  593. writel(0x00000000, priv->regs_hi+0x000014b0); //csr_reg
  594. writel(0x000000e2, priv->regs_hi+0x00001cd0); //csr_reg
  595. writel(0x000000af, priv->regs_hi+0x000014d0); //csr_reg
  596. writel(0x00000005, priv->regs_hi+0x000014b8); //csr_reg
  597. writel(0x8dd0b774, priv->regs_hi+0x00001528); //csr_reg
  598. writel(0x00001111, priv->regs_hi+0x00001418); //csr_reg
  599. writel(0x00000000, priv->regs_hi+0x00001410); //csr_reg
  600. writel(0x00000000, priv->regs_hi+0x00002518); //csr_reg
  601. writel(0x00000006, priv->regs_hi+0x00001468); //csr_reg
  602. writel(0x00000000, priv->regs_hi+0x00001484); //csr_reg
  603. writel(0x00000006, priv->regs_hi+0x00001468); //csr_reg
  604. writel(0x00011b25, priv->regs_hi+0x000024e8); //csr_reg
  605. writel(0x00000000, priv->regs_hi+0x000024fc); //csr_reg
  606. writel(0x00011b25, priv->regs_hi+0x000024e8); //csr_reg
  607. writel(0x00000001, priv->regs_hi+0x00001ccc); //csr_reg
  608. #else
  609. if(uc_priv->xsize == 800)
  610. {
  611. writel(0xc0001fff, priv->regs_hi+0x00000014); //csr_reg
  612. writel(0x000000e8, priv->regs_hi+0x00001a38); //csr_reg
  613. writel(0x00002000, priv->regs_hi+0x00001cc0); //csr_reg
  614. writel(0x00000000, priv->regs_hi+0x000024d8); //csr_reg
  615. writel(0x03c00438, priv->regs_hi+0x000024e0); //csr_reg
  616. writel(0x03c00438, priv->regs_hi+0x00001810); //csr_reg
  617. writel(uc_plat->base, priv->regs_hi+0x00001400);
  618. writel(0x000010e0, priv->regs_hi+0x00001408); //csr_reg
  619. writel(0x000fb00b, priv->regs_hi+0x00001ce8); //csr_reg
  620. writel(0x0000a9a3, priv->regs_hi+0x00002510); //csr_reg
  621. writel(0x2c4e6f06, priv->regs_hi+0x00002508); //csr_reg
  622. writel(0xe6daec4f, priv->regs_hi+0x00002500); //csr_reg
  623. writel(0x18220000, priv->regs_hi+0x00001518); //csr_reg
  624. writel(0x00003000, priv->regs_hi+0x00001cc0); //csr_reg
  625. writel(0x00030000, priv->regs_hi+0x00001cc4); //csr_reg
  626. writel(0x00030000, priv->regs_hi+0x00001cc4); //csr_reg
  627. writel(0x00050c1a, priv->regs_hi+0x00001540); //csr_reg
  628. writel(0x00000001, priv->regs_hi+0x00002540); //csr_reg
  629. writel(0x00050c1a, priv->regs_hi+0x00001540); //csr_reg
  630. writel(0x4016120c, priv->regs_hi+0x00001544); //csr_reg
  631. writel(0x00000002, priv->regs_hi+0x00002544); //csr_reg
  632. writel(0x4016120c, priv->regs_hi+0x00001544); //csr_reg
  633. writel(0x001b1208, priv->regs_hi+0x00001548); //csr_reg
  634. writel(0x00000004, priv->regs_hi+0x00002548); //csr_reg
  635. writel(0x001b1208, priv->regs_hi+0x00001548); //csr_reg
  636. writel(0x0016110e, priv->regs_hi+0x0000154c); //csr_reg
  637. writel(0x00000005, priv->regs_hi+0x0000254c); //csr_reg
  638. writel(0x0016110e, priv->regs_hi+0x0000154c); //csr_reg
  639. writel(0x00000001, priv->regs_hi+0x00002518); //csr_reg
  640. writel(0x00000000, priv->regs_hi+0x00001a28); //csr_reg
  641. writel(0x03840320, priv->regs_hi+0x00001430); //csr_reg, hsize, htotal
  642. writel(0xc1bf837a, priv->regs_hi+0x00001438); //csr_reg, hsize blanking
  643. writel(0x022601e0, priv->regs_hi+0x00001440); //csr_reg, vsize
  644. writel(0xc110021c, priv->regs_hi+0x00001448); //csr_reg, vsize blanking
  645. writel(0x00000000, priv->regs_hi+0x000014b0); //csr_reg
  646. writel(0x000000e2, priv->regs_hi+0x00001cd0); //csr_reg
  647. writel(0x000000af, priv->regs_hi+0x000014d0); //csr_reg
  648. writel(0x00000005, priv->regs_hi+0x000014b8); //csr_reg
  649. writel(0x8dd0b774, priv->regs_hi+0x00001528); //csr_reg
  650. writel(0x00001111, priv->regs_hi+0x00001418); //csr_reg
  651. writel(0x00000000, priv->regs_hi+0x00001410); //csr_reg
  652. writel(0x00000000, priv->regs_hi+0x00002518); //csr_reg
  653. writel(0x00000006, priv->regs_hi+0x00001468); //csr_reg
  654. writel(0x00000000, priv->regs_hi+0x00001484); //csr_reg
  655. writel(0x00000006, priv->regs_hi+0x00001468); //csr_reg
  656. writel(0x00011b25, priv->regs_hi+0x000024e8); //csr_reg
  657. writel(0x00000000, priv->regs_hi+0x000024fc); //csr_reg
  658. writel(0x00011b25, priv->regs_hi+0x000024e8); //csr_reg
  659. writel(0x00000001, priv->regs_hi+0x00001ccc); //csr_reg
  660. }
  661. if(uc_priv->xsize == 1920)
  662. {
  663. writel(0xc0001fff, priv->regs_hi+0x00000014);
  664. writel(0x000000e8, priv->regs_hi+0x00001a38);
  665. writel(0x00002000, priv->regs_hi+0x00001cc0);
  666. writel(0x00000000, priv->regs_hi+0x000024d8);
  667. writel(0x04380780, priv->regs_hi+0x000024e0);
  668. writel(0x04380780, priv->regs_hi+0x00001810);
  669. writel(uc_plat->base, priv->regs_hi+0x00001400);
  670. writel(0x00001e00, priv->regs_hi+0x00001408);
  671. writel(0x00000000, priv->regs_hi+0x00001ce8);
  672. writel(0x0000a9a3, priv->regs_hi+0x00002510);
  673. writel(0x2c4e6f06, priv->regs_hi+0x00002508);
  674. writel(0xe6daec4f, priv->regs_hi+0x00002500);
  675. writel(0x18220000, priv->regs_hi+0x00001518);
  676. writel(0x00003000, priv->regs_hi+0x00001cc0);
  677. writel(0x00030000, priv->regs_hi+0x00001cc4);
  678. writel(0x00030000, priv->regs_hi+0x00001cc4);
  679. writel(0x00050c1a, priv->regs_hi+0x00001540);
  680. writel(0x00000001, priv->regs_hi+0x00002540);
  681. writel(0x00050c1a, priv->regs_hi+0x00001540);
  682. writel(0x4016120c, priv->regs_hi+0x00001544);
  683. writel(0x00000002, priv->regs_hi+0x00002544);
  684. writel(0x4016120c, priv->regs_hi+0x00001544);
  685. writel(0x001b1208, priv->regs_hi+0x00001548);
  686. writel(0x00000004, priv->regs_hi+0x00002548);
  687. writel(0x001b1208, priv->regs_hi+0x00001548);
  688. writel(0x0016110e, priv->regs_hi+0x0000154c);
  689. writel(0x00000005, priv->regs_hi+0x0000254c);
  690. writel(0x0016110e, priv->regs_hi+0x0000154c);
  691. writel(0x00000001, priv->regs_hi+0x00002518);
  692. writel(0x00000000, priv->regs_hi+0x00001a28);
  693. writel(0x08980780, priv->regs_hi+0x00001430);
  694. writel(0xc40207d8, priv->regs_hi+0x00001438);
  695. writel(0x04650438, priv->regs_hi+0x00001440);
  696. writel(0xc220843c, priv->regs_hi+0x00001448);
  697. writel(0x00000000, priv->regs_hi+0x000014b0);
  698. writel(0x000000e2, priv->regs_hi+0x00001cd0);
  699. writel(0x000000af, priv->regs_hi+0x000014d0);
  700. writel(0x00000005, priv->regs_hi+0x000014b8);
  701. writel(0x8dd0b774, priv->regs_hi+0x00001528);
  702. writel(0x00001111, priv->regs_hi+0x00001418);
  703. writel(0x00000000, priv->regs_hi+0x00001410);
  704. writel(0x00000000, priv->regs_hi+0x00002518);
  705. writel(0x00000006, priv->regs_hi+0x00001468);
  706. writel(0x00000000, priv->regs_hi+0x00001484);
  707. writel(0x00000006, priv->regs_hi+0x00001468);
  708. writel(0x00011b25, priv->regs_hi+0x000024e8);
  709. writel(0x00000000, priv->regs_hi+0x000024fc);
  710. writel(0x00011b25, priv->regs_hi+0x000024e8);
  711. writel(0x00000001, priv->regs_hi+0x00001ccc);
  712. }
  713. #endif
  714. }
  715. priv->mipi_logo = true;
  716. return 0;
  717. }
  718. static int sf_vop_probe(struct udevice *dev)
  719. {
  720. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  721. struct sf_vop_priv *priv = dev_get_priv(dev);
  722. ofnode port, node;
  723. int ret;
  724. sf_vop_power(dev);
  725. mdelay(50);
  726. priv->regs_hi = dev_remap_addr_name(dev, "hi");
  727. if (!priv->regs_hi)
  728. return -EINVAL;
  729. priv->regs_low = dev_remap_addr_name(dev, "low");
  730. if (!priv->regs_low)
  731. return -EINVAL;
  732. priv->hdmi_logo = false;
  733. priv->mipi_logo = false;
  734. vout_probe_resources_jh7110(dev);
  735. port = dev_read_subnode(dev, "port");
  736. if (!ofnode_valid(port)) {
  737. debug("%s(%s): 'port' subnode not found\n",
  738. __func__, dev_read_name(dev));
  739. return -EINVAL;
  740. }
  741. for (node = ofnode_first_subnode(port);
  742. ofnode_valid(node);
  743. node = dev_read_next_subnode(node)) {
  744. ret = sf_display_init(dev, plat->base, node);
  745. if (ret)
  746. debug("Device failed: ret=%d\n", ret);
  747. if (!ret)
  748. break;
  749. }
  750. video_set_flush_dcache(dev, 1);
  751. return 0;
  752. }
  753. static int sf_vop_remove(struct udevice *dev)
  754. {
  755. struct sf_vop_priv *priv = dev_get_priv(dev);
  756. debug("sf_vop_remove-------\n");
  757. int ret;
  758. if(priv->mipi_logo == true)
  759. return 0;
  760. iotrace_writel( 0x00000000, priv->regs_hi+0x1cc0 );
  761. iotrace_writel( 0x00000000, priv->regs_hi+0x24e0 );
  762. iotrace_writel( 0x00000000, priv->regs_hi+0x1810 );
  763. iotrace_writel( 0x00000000, priv->regs_hi+0x1400 );
  764. iotrace_writel( 0x00000000, priv->regs_hi+0x1408 );
  765. iotrace_writel( 0x00000000, priv->regs_hi+0x1ce8 );
  766. iotrace_writel( 0x00000000, priv->regs_hi+0x2510 );
  767. iotrace_writel( 0x00000000, priv->regs_hi+0x2508 );
  768. iotrace_writel( 0x00000000, priv->regs_hi+0x2500 );
  769. iotrace_writel( 0x00000000, priv->regs_hi+0x1518 );
  770. iotrace_writel( 0x00000000, priv->regs_hi+0x1540 );
  771. iotrace_writel( 0x00000000, priv->regs_hi+0x2540 );
  772. iotrace_writel( 0x00000000, priv->regs_hi+0x1544 );
  773. iotrace_writel( 0x00000000, priv->regs_hi+0x2544 );
  774. iotrace_writel( 0x00000000, priv->regs_hi+0x1548 );
  775. iotrace_writel( 0x00000000, priv->regs_hi+0x2548 );
  776. iotrace_writel( 0x00000000, priv->regs_hi+0x154c );
  777. iotrace_writel( 0x00000000, priv->regs_hi+0x254c );
  778. iotrace_writel( 0x00000000, priv->regs_hi+0x2518 );
  779. iotrace_writel( 0x00000e07, priv->regs_hi+0x1a28 );
  780. iotrace_writel( 0x00000000, priv->regs_hi+0x1430 );
  781. iotrace_writel( 0x00000000, priv->regs_hi+0x1438 );
  782. iotrace_writel( 0x00000000, priv->regs_hi+0x1440 );
  783. iotrace_writel( 0x00000000, priv->regs_hi+0x1448 );
  784. iotrace_writel( 0x00000000, priv->regs_hi+0x14b0 );
  785. iotrace_writel( 0x00000000, priv->regs_hi+0x1cd0 );
  786. iotrace_writel( 0x00000000, priv->regs_hi+0x14b8 );
  787. iotrace_writel( 0x00000000, priv->regs_hi+0x14d0 );
  788. iotrace_writel( 0x00000000, priv->regs_hi+0x1528 );
  789. iotrace_writel( 0x00000100, priv->regs_hi+0x1418 );
  790. iotrace_writel( 0x00000000, priv->regs_hi+0x1410 );
  791. iotrace_writel( 0x00000001, priv->regs_hi+0x2518 );
  792. iotrace_writel( 0x00000000, priv->regs_hi+0x1468 );
  793. iotrace_writel( 0x00000001, priv->regs_hi+0x1484 );
  794. iotrace_writel( 0x00000000, priv->regs_hi+0x24e8 );
  795. iotrace_writel( 0x00000001, priv->regs_hi+0x24fc );
  796. iotrace_writel( 0x00000000, priv->regs_hi+0x1ccc );
  797. ret = reset_assert(&priv->dc8200_rst_axi);
  798. if (ret) {
  799. pr_err("failed to assert dc8200_rst_axi reset (ret=%d)\n", ret);
  800. return ret;
  801. }
  802. ret = reset_assert(&priv->dc8200_rst_core);
  803. if (ret) {
  804. pr_err("failed to assert dc8200_rst_axi reset (ret=%d)\n", ret);
  805. return ret;
  806. }
  807. ret = reset_assert(&priv->dc8200_rst_ahb);
  808. if (ret) {
  809. pr_err("failed to assert dc8200_rst_ahb reset (ret=%d)\n", ret);
  810. return ret;
  811. }
  812. clk_set_rate(&priv->dc_pix_src, 74250000);
  813. clk_disable(&priv->hdmitx0_pixelclk);
  814. clk_disable(&priv->dc_ahb);
  815. clk_disable(&priv->dc_core);
  816. clk_disable(&priv->dc_axi);
  817. clk_disable(&priv->dc_pix1);
  818. clk_disable(&priv->dc_pix0);
  819. ret = reset_assert(&priv->rst_vout_src);
  820. if (ret) {
  821. pr_err("failed to deassert rst_vout_src reset (ret=%d)\n", ret);
  822. return ret;
  823. }
  824. clk_disable(&priv->top_vout_ahb);
  825. clk_disable(&priv->top_vout_axi);
  826. clk_disable(&priv->vout_src);
  827. clk_disable(&priv->disp_axi);
  828. reset_assert(&priv->noc_disp);
  829. sf_vop_power_off(dev);
  830. return 0;
  831. }
  832. struct rkvop_driverdata rk3288_driverdata = {
  833. .features = VOP_FEATURE_OUTPUT_10BIT,
  834. };
  835. static const struct udevice_id sf_dc_ids[] = {
  836. { .compatible = "starfive,sf-dc8200",
  837. .data = (ulong)&rk3288_driverdata },
  838. { }
  839. };
  840. static const struct video_ops sf_vop_ops = {
  841. };
  842. int sf_vop_bind(struct udevice *dev)
  843. {
  844. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  845. plat->size = 4 * (CONFIG_VIDEO_STARFIVE_MAX_XRES *
  846. CONFIG_VIDEO_STARFIVE_MAX_YRES);
  847. debug("%s,%d,plat->size = %d\n",__func__,__LINE__,plat->size);
  848. return 0;
  849. }
  850. U_BOOT_DRIVER(starfive_dc8200) = {
  851. .name = "starfive_dc8200",
  852. .id = UCLASS_VIDEO,
  853. .of_match = sf_dc_ids,
  854. .ops = &sf_vop_ops,
  855. .bind = sf_vop_bind,
  856. .probe = sf_vop_probe,
  857. .remove = sf_vop_remove,
  858. .priv_auto = sizeof(struct sf_vop_priv),
  859. .flags = DM_FLAG_OS_PREPARE,
  860. };