sf_mipi.h 34 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
  4. * Author: Eric Gao <eric.gao@rock-chips.com>
  5. */
  6. #ifndef __RK_MIPI_H
  7. #define __RK_MIPI_H
  8. #include <clk.h>
  9. #include <reset.h>
  10. #include <mipi_dsi.h>
  11. //sysrst registers
  12. #define SRST_ASSERT0 0x00
  13. #define SRST_STATUS0 0x04
  14. #define IP_CONF 0x0
  15. #define SP_HS_FIFO_DEPTH(x) (((x) & GENMASK(30, 26)) >> 26)
  16. #define SP_LP_FIFO_DEPTH(x) (((x) & GENMASK(25, 21)) >> 21)
  17. #define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16)
  18. #define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13)
  19. #define SDI_IFACE_32 BIT(12)
  20. #define INTERNAL_DATAPATH_32 (0 << 10)
  21. #define INTERNAL_DATAPATH_16 (1 << 10)
  22. #define INTERNAL_DATAPATH_8 (3 << 10)
  23. #define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10))
  24. #define NUM_IFACE(x) ((((x) & GENMASK(9, 8)) >> 8) + 1)
  25. #define MAX_LANE_NB(x) (((x) & GENMASK(7, 6)) >> 6)
  26. #define RX_FIFO_DEPTH(x) ((x) & GENMASK(5, 0))
  27. #define MCTL_MAIN_DATA_CTL 0x4
  28. #define TE_MIPI_POLLING_EN BIT(25)
  29. #define TE_HW_POLLING_EN BIT(24)
  30. #define DISP_EOT_GEN BIT(18)
  31. #define HOST_EOT_GEN BIT(17)
  32. #define DISP_GEN_CHECKSUM BIT(16)
  33. #define DISP_GEN_ECC BIT(15)
  34. #define BTA_EN BIT(14)
  35. #define READ_EN BIT(13)
  36. #define REG_TE_EN BIT(12)
  37. #define IF_TE_EN(x) BIT(8 + (x))
  38. #define TVG_SEL BIT(6)
  39. #define VID_EN BIT(5)
  40. #define IF_VID_SELECT(x) ((x) << 2)
  41. #define IF_VID_SELECT_MASK GENMASK(3, 2)
  42. #define IF_VID_MODE BIT(1)
  43. #define LINK_EN BIT(0)
  44. #define MCTL_MAIN_PHY_CTL 0x8
  45. #define HS_INVERT_DAT(x) BIT(19 + ((x) * 2))
  46. #define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2))
  47. #define HS_INVERT_CLK BIT(17)
  48. #define SWAP_PINS_CLK BIT(16)
  49. #define HS_SKEWCAL_EN BIT(15)
  50. #define WAIT_BURST_TIME(x) ((x) << 10)
  51. #define DATA_ULPM_EN(x) BIT(6 + (x))
  52. #define CLK_ULPM_EN BIT(5)
  53. #define CLK_CONTINUOUS BIT(4)
  54. #define DATA_LANE_EN(x) BIT((x) - 1)
  55. #define MCTL_MAIN_EN 0xc
  56. #define DATA_FORCE_STOP BIT(17)
  57. #define CLK_FORCE_STOP BIT(16)
  58. #define IF_EN(x) BIT(13 + (x))
  59. #define DATA_LANE_ULPM_REQ(l) BIT(9 + (l))
  60. #define CLK_LANE_ULPM_REQ BIT(8)
  61. #define DATA_LANE_START(x) BIT(4 + (x))
  62. #define CLK_LANE_EN BIT(3)
  63. #define PLL_START BIT(0)
  64. #define MCTL_DPHY_CFG0 0x10
  65. #define DPHY_C_RSTB BIT(20)
  66. #define DPHY_D_RSTB(x) GENMASK(15 + (x), 16)
  67. #define DPHY_PLL_PDN BIT(10)
  68. #define DPHY_CMN_PDN BIT(9)
  69. #define DPHY_C_PDN BIT(8)
  70. #define DPHY_D_PDN(x) GENMASK(3 + (x), 4)
  71. #define DPHY_ALL_D_PDN GENMASK(7, 4)
  72. #define DPHY_PLL_PSO BIT(1)
  73. #define DPHY_CMN_PSO BIT(0)
  74. #define MCTL_DPHY_TIMEOUT1 0x14
  75. #define HSTX_TIMEOUT(x) ((x) << 4)
  76. #define HSTX_TIMEOUT_MAX GENMASK(17, 0)
  77. #define CLK_DIV(x) (x)
  78. #define CLK_DIV_MAX GENMASK(3, 0)
  79. #define MCTL_DPHY_TIMEOUT2 0x18
  80. #define LPRX_TIMEOUT(x) (x)
  81. #define MCTL_ULPOUT_TIME 0x1c
  82. #define DATA_LANE_ULPOUT_TIME(x) ((x) << 9)
  83. #define CLK_LANE_ULPOUT_TIME(x) (x)
  84. #define MCTL_3DVIDEO_CTL 0x20
  85. #define VID_VSYNC_3D_EN BIT(7)
  86. #define VID_VSYNC_3D_LR BIT(5)
  87. #define VID_VSYNC_3D_SECOND_EN BIT(4)
  88. #define VID_VSYNC_3DFORMAT_LINE (0 << 2)
  89. #define VID_VSYNC_3DFORMAT_FRAME (1 << 2)
  90. #define VID_VSYNC_3DFORMAT_PIXEL (2 << 2)
  91. #define VID_VSYNC_3DMODE_OFF 0
  92. #define VID_VSYNC_3DMODE_PORTRAIT 1
  93. #define VID_VSYNC_3DMODE_LANDSCAPE 2
  94. #define MCTL_MAIN_STS 0x24
  95. #define MCTL_MAIN_STS_CTL 0x130
  96. #define MCTL_MAIN_STS_CLR 0x150
  97. #define MCTL_MAIN_STS_FLAG 0x170
  98. #define HS_SKEWCAL_DONE BIT(11)
  99. #define IF_UNTERM_PKT_ERR(x) BIT(8 + (x))
  100. #define LPRX_TIMEOUT_ERR BIT(7)
  101. #define HSTX_TIMEOUT_ERR BIT(6)
  102. #define DATA_LANE_RDY(l) BIT(2 + (l))
  103. #define CLK_LANE_RDY BIT(1)
  104. #define PLL_LOCKED BIT(0)
  105. #define MCTL_DPHY_ERR 0x28
  106. #define MCTL_DPHY_ERR_CTL1 0x148
  107. #define MCTL_DPHY_ERR_CLR 0x168
  108. #define MCTL_DPHY_ERR_FLAG 0x188
  109. #define ERR_CONT_LP(x, l) BIT(18 + ((x) * 4) + (l))
  110. #define ERR_CONTROL(l) BIT(14 + (l))
  111. #define ERR_SYNESC(l) BIT(10 + (l))
  112. #define ERR_ESC(l) BIT(6 + (l))
  113. #define MCTL_DPHY_ERR_CTL2 0x14c
  114. #define ERR_CONT_LP_EDGE(x, l) BIT(12 + ((x) * 4) + (l))
  115. #define ERR_CONTROL_EDGE(l) BIT(8 + (l))
  116. #define ERR_SYN_ESC_EDGE(l) BIT(4 + (l))
  117. #define ERR_ESC_EDGE(l) BIT(0 + (l))
  118. #define MCTL_LANE_STS 0x2c
  119. #define PPI_C_TX_READY_HS BIT(18)
  120. #define DPHY_PLL_LOCK BIT(17)
  121. #define PPI_D_RX_ULPS_ESC(x) (((x) & GENMASK(15, 12)) >> 12)
  122. #define LANE_STATE_START 0
  123. #define LANE_STATE_IDLE 1
  124. #define LANE_STATE_WRITE 2
  125. #define LANE_STATE_ULPM 3
  126. #define LANE_STATE_READ 4
  127. #define DATA_LANE_STATE(l, val) \
  128. (((val) >> (2 + 2 * (l) + ((l) ? 1 : 0))) & GENMASK((l) ? 1 : 2, 0))
  129. #define CLK_LANE_STATE_HS 2
  130. #define CLK_LANE_STATE(val) ((val) & GENMASK(1, 0))
  131. #define DSC_MODE_CTL 0x30
  132. #define DSC_MODE_EN BIT(0)
  133. #define DSC_CMD_SEND 0x34
  134. #define DSC_SEND_PPS BIT(0)
  135. #define DSC_EXECUTE_QUEUE BIT(1)
  136. #define DSC_PPS_WRDAT 0x38
  137. #define DSC_MODE_STS 0x3c
  138. #define DSC_PPS_DONE BIT(1)
  139. #define DSC_EXEC_DONE BIT(2)
  140. #define CMD_MODE_CTL 0x70
  141. #define IF_LP_EN(x) BIT(9 + (x))
  142. #define IF_VCHAN_ID(x, c) ((c) << ((x) * 2))
  143. #define CMD_MODE_CTL2 0x74
  144. #define TE_TIMEOUT(x) ((x) << 11)
  145. #define FILL_VALUE(x) ((x) << 3)
  146. #define ARB_IF_WITH_HIGHEST_PRIORITY(x) ((x) << 1)
  147. #define ARB_ROUND_ROBIN_MODE BIT(0)
  148. #define CMD_MODE_STS 0x78
  149. #define CMD_MODE_STS_CTL 0x134
  150. #define CMD_MODE_STS_CLR 0x154
  151. #define CMD_MODE_STS_FLAG 0x174
  152. #define ERR_IF_UNDERRUN(x) BIT(4 + (x))
  153. #define ERR_UNWANTED_READ BIT(3)
  154. #define ERR_TE_MISS BIT(2)
  155. #define ERR_NO_TE BIT(1)
  156. #define CSM_RUNNING BIT(0)
  157. #define DIRECT_CMD_SEND 0x80
  158. #define DIRECT_CMD_MAIN_SETTINGS 0x84
  159. #define TRIGGER_VAL(x) ((x) << 25)
  160. #define CMD_LP_EN BIT(24)
  161. #define CMD_SIZE(x) ((x) << 16)
  162. #define CMD_VCHAN_ID(x) ((x) << 14)
  163. #define CMD_DATATYPE(x) ((x) << 8)
  164. #define CMD_LONG BIT(3)
  165. #define WRITE_CMD 0
  166. #define READ_CMD 1
  167. #define TE_REQ 4
  168. #define TRIGGER_REQ 5
  169. #define BTA_REQ 6
  170. #define DIRECT_CMD_STS 0x88
  171. #define DIRECT_CMD_STS_CTL 0x138
  172. #define DIRECT_CMD_STS_CLR 0x158
  173. #define DIRECT_CMD_STS_FLAG 0x178
  174. #define RCVD_ACK_VAL(val) ((val) >> 16)
  175. #define RCVD_TRIGGER_VAL(val) (((val) & GENMASK(14, 11)) >> 11)
  176. #define READ_COMPLETED_WITH_ERR BIT(10)
  177. #define BTA_FINISHED BIT(9)
  178. #define BTA_COMPLETED BIT(8)
  179. #define TE_RCVD BIT(7)
  180. #define TRIGGER_RCVD BIT(6)
  181. #define ACK_WITH_ERR_RCVD BIT(5)
  182. #define ACK_RCVD BIT(4)
  183. #define READ_COMPLETED BIT(3)
  184. #define TRIGGER_COMPLETED BIT(2)
  185. #define WRITE_COMPLETED BIT(1)
  186. #define SENDING_CMD BIT(0)
  187. #define DIRECT_CMD_STOP_READ 0x8c
  188. #define DIRECT_CMD_WRDATA 0x90
  189. #define DIRECT_CMD_FIFO_RST 0x94
  190. #define DIRECT_CMD_RDDATA 0xa0
  191. #define DIRECT_CMD_RD_PROPS 0xa4
  192. #define RD_DCS BIT(18)
  193. #define RD_VCHAN_ID(val) (((val) >> 16) & GENMASK(1, 0))
  194. #define RD_SIZE(val) ((val) & GENMASK(15, 0))
  195. #define DIRECT_CMD_RD_STS 0xa8
  196. #define DIRECT_CMD_RD_STS_CTL 0x13c
  197. #define DIRECT_CMD_RD_STS_CLR 0x15c
  198. #define DIRECT_CMD_RD_STS_FLAG 0x17c
  199. #define ERR_EOT_WITH_ERR BIT(8)
  200. #define ERR_MISSING_EOT BIT(7)
  201. #define ERR_WRONG_LENGTH BIT(6)
  202. #define ERR_OVERSIZE BIT(5)
  203. #define ERR_RECEIVE BIT(4)
  204. #define ERR_UNDECODABLE BIT(3)
  205. #define ERR_CHECKSUM BIT(2)
  206. #define ERR_UNCORRECTABLE BIT(1)
  207. #define ERR_FIXED BIT(0)
  208. #define VID_MAIN_CTL 0xb0
  209. #define VID_IGNORE_MISS_VSYNC BIT(31)
  210. #define VID_FIELD_SW BIT(28)
  211. #define VID_INTERLACED_EN BIT(27)
  212. #define RECOVERY_MODE(x) ((x) << 25)
  213. #define RECOVERY_MODE_NEXT_HSYNC 0
  214. #define RECOVERY_MODE_NEXT_STOP_POINT 2
  215. #define RECOVERY_MODE_NEXT_VSYNC 3
  216. #define REG_BLKEOL_MODE(x) ((x) << 23)
  217. #define REG_BLKLINE_MODE(x) ((x) << 21)
  218. #define REG_BLK_MODE_NULL_PKT 0
  219. #define REG_BLK_MODE_BLANKING_PKT 1
  220. #define REG_BLK_MODE_LP 2
  221. #define SYNC_PULSE_HORIZONTAL BIT(20)
  222. #define SYNC_PULSE_ACTIVE BIT(19)
  223. #define BURST_MODE BIT(18)
  224. #define VID_PIXEL_MODE_MASK GENMASK(17, 14)
  225. #define VID_PIXEL_MODE_RGB565 (0 << 14)
  226. #define VID_PIXEL_MODE_RGB666_PACKED (1 << 14)
  227. #define VID_PIXEL_MODE_RGB666 (2 << 14)
  228. #define VID_PIXEL_MODE_RGB888 (3 << 14)
  229. #define VID_PIXEL_MODE_RGB101010 (4 << 14)
  230. #define VID_PIXEL_MODE_RGB121212 (5 << 14)
  231. #define VID_PIXEL_MODE_YUV420 (8 << 14)
  232. #define VID_PIXEL_MODE_YUV422_PACKED (9 << 14)
  233. #define VID_PIXEL_MODE_YUV422 (10 << 14)
  234. #define VID_PIXEL_MODE_YUV422_24B (11 << 14)
  235. #define VID_PIXEL_MODE_DSC_COMP (12 << 14)
  236. #define VID_DATATYPE(x) ((x) << 8)
  237. #define VID_VIRTCHAN_ID(iface, x) ((x) << (4 + (iface) * 2))
  238. #define STOP_MODE(x) ((x) << 2)
  239. #define START_MODE(x) (x)
  240. #define VID_VSIZE1 0xb4
  241. #define VFP_LEN(x) ((x) << 12)
  242. #define VBP_LEN(x) ((x) << 6)
  243. #define VSA_LEN(x) (x)
  244. #define VID_VSIZE2 0xb8
  245. #define VACT_LEN(x) (x)
  246. #define VID_HSIZE1 0xc0
  247. #define HBP_LEN(x) ((x) << 16)
  248. #define HSA_LEN(x) (x)
  249. #define VID_HSIZE2 0xc4
  250. #define HFP_LEN(x) ((x) << 16)
  251. #define HACT_LEN(x) (x)
  252. #define VID_BLKSIZE1 0xcc
  253. #define BLK_EOL_PKT_LEN(x) ((x) << 15)
  254. #define BLK_LINE_EVENT_PKT_LEN(x) (x)
  255. #define VID_BLKSIZE2 0xd0
  256. #define BLK_LINE_PULSE_PKT_LEN(x) (x)
  257. #define VID_PKT_TIME 0xd8
  258. #define BLK_EOL_DURATION(x) (x)
  259. #define VID_DPHY_TIME 0xdc
  260. #define REG_WAKEUP_TIME(x) ((x) << 17)
  261. #define REG_LINE_DURATION(x) (x)
  262. #define VID_ERR_COLOR1 0xe0
  263. #define COL_GREEN(x) ((x) << 12)
  264. #define COL_RED(x) (x)
  265. #define VID_ERR_COLOR2 0xe4
  266. #define PAD_VAL(x) ((x) << 12)
  267. #define COL_BLUE(x) (x)
  268. #define VID_VPOS 0xe8
  269. #define LINE_VAL(val) (((val) & GENMASK(14, 2)) >> 2)
  270. #define LINE_POS(val) ((val) & GENMASK(1, 0))
  271. #define VID_HPOS 0xec
  272. #define HORIZ_VAL(val) (((val) & GENMASK(17, 3)) >> 3)
  273. #define HORIZ_POS(val) ((val) & GENMASK(2, 0))
  274. #define VID_MODE_STS 0xf0
  275. #define VID_MODE_STS_CTL 0x140
  276. #define VID_MODE_STS_CLR 0x160
  277. #define VID_MODE_STS_FLAG 0x180
  278. #define VSG_RECOVERY BIT(10)
  279. #define ERR_VRS_WRONG_LEN BIT(9)
  280. #define ERR_LONG_READ BIT(8)
  281. #define ERR_LINE_WRITE BIT(7)
  282. #define ERR_BURST_WRITE BIT(6)
  283. #define ERR_SMALL_HEIGHT BIT(5)
  284. #define ERR_SMALL_LEN BIT(4)
  285. #define ERR_MISSING_VSYNC BIT(3)
  286. #define ERR_MISSING_HSYNC BIT(2)
  287. #define ERR_MISSING_DATA BIT(1)
  288. #define VSG_RUNNING BIT(0)
  289. #define VID_VCA_SETTING1 0xf4
  290. #define BURST_LP BIT(16)
  291. #define MAX_BURST_LIMIT(x) (x)
  292. #define VID_VCA_SETTING2 0xf8
  293. #define MAX_LINE_LIMIT(x) ((x) << 16)
  294. #define EXACT_BURST_LIMIT(x) (x)
  295. #define TVG_CTL 0xfc
  296. #define TVG_STRIPE_SIZE(x) ((x) << 5)
  297. #define TVG_MODE_MASK GENMASK(4, 3)
  298. #define TVG_MODE_SINGLE_COLOR (0 << 3)
  299. #define TVG_MODE_VSTRIPES (2 << 3)
  300. #define TVG_MODE_HSTRIPES (3 << 3)
  301. #define TVG_STOPMODE_MASK GENMASK(2, 1)
  302. #define TVG_STOPMODE_EOF (0 << 1)
  303. #define TVG_STOPMODE_EOL (1 << 1)
  304. #define TVG_STOPMODE_NOW (2 << 1)
  305. #define TVG_RUN BIT(0)
  306. #define TVG_IMG_SIZE 0x100
  307. #define TVG_NBLINES(x) ((x) << 16)
  308. #define TVG_LINE_SIZE(x) (x)
  309. #define TVG_COLOR1 0x104
  310. #define TVG_COL1_GREEN(x) ((x) << 12)
  311. #define TVG_COL1_RED(x) (x)
  312. #define TVG_COLOR1_BIS 0x108
  313. #define TVG_COL1_BLUE(x) (x)
  314. #define TVG_COLOR2 0x10c
  315. #define TVG_COL2_GREEN(x) ((x) << 12)
  316. #define TVG_COL2_RED(x) (x)
  317. #define TVG_COLOR2_BIS 0x110
  318. #define TVG_COL2_BLUE(x) (x)
  319. #define TVG_STS 0x114
  320. #define TVG_STS_CTL 0x144
  321. #define TVG_STS_CLR 0x164
  322. #define TVG_STS_FLAG 0x184
  323. #define TVG_STS_RUNNING BIT(0)
  324. #define STS_CTL_EDGE(e) ((e) << 16)
  325. #define DPHY_LANES_MAP 0x198
  326. #define DAT_REMAP_CFG(b, l) ((l) << ((b) * 8))
  327. #define DPI_IRQ_EN 0x1a0
  328. #define DPI_IRQ_CLR 0x1a4
  329. #define DPI_IRQ_STS 0x1a8
  330. #define PIXEL_BUF_OVERFLOW BIT(0)
  331. #define DPI_CFG 0x1ac
  332. #define DPI_CFG_FIFO_DEPTH(x) ((x) >> 16)
  333. #define DPI_CFG_FIFO_LEVEL(x) ((x) & GENMASK(15, 0))
  334. #define TEST_GENERIC 0x1f0
  335. #define TEST_STATUS(x) ((x) >> 16)
  336. #define TEST_CTRL(x) (x)
  337. #define ID_REG 0x1fc
  338. #define REV_VENDOR_ID(x) (((x) & GENMASK(31, 20)) >> 20)
  339. #define REV_PRODUCT_ID(x) (((x) & GENMASK(19, 12)) >> 12)
  340. #define REV_HW(x) (((x) & GENMASK(11, 8)) >> 8)
  341. #define REV_MAJOR(x) (((x) & GENMASK(7, 4)) >> 4)
  342. #define REV_MINOR(x) ((x) & GENMASK(3, 0))
  343. #define DSI_OUTPUT_PORT 0
  344. #define DSI_INPUT_PORT(inputid) (1 + (inputid))
  345. #define DSI_HBP_FRAME_OVERHEAD 12
  346. #define DSI_HSA_FRAME_OVERHEAD 14
  347. #define DSI_HFP_FRAME_OVERHEAD 6
  348. #define DSI_HSS_VSS_VSE_FRAME_OVERHEAD 4
  349. #define DSI_BLANKING_FRAME_OVERHEAD 6
  350. #define DSI_NULL_FRAME_OVERHEAD 6
  351. #define DSI_EOT_PKT_SIZE 4
  352. #define ARRAY_SIZE_DSI(x) (sizeof(x) / sizeof((x)[0]))
  353. #define TEST_CTRL(x) (x)
  354. #define AON_POWER_READY_N_WIDTH 0x1U
  355. #define AON_POWER_READY_N_SHIFT 0x0U
  356. #define AON_POWER_READY_N_MASK 0x1U
  357. #define CFG_CKLANE_SET_WIDTH 0x5U
  358. #define CFG_CKLANE_SET_SHIFT 0x1U
  359. #define CFG_CKLANE_SET_MASK 0x3EU
  360. #define CFG_DATABUS16_SEL_WIDTH 0x1U
  361. #define CFG_DATABUS16_SEL_SHIFT 0x6U
  362. #define CFG_DATABUS16_SEL_MASK 0x40U
  363. #define CFG_DPDN_SWAP_WIDTH 0x5U
  364. #define CFG_DPDN_SWAP_SHIFT 0x7U
  365. #define CFG_DPDN_SWAP_MASK 0xF80U
  366. #define CFG_L0_SWAP_SEL_WIDTH 0x3U
  367. #define CFG_L0_SWAP_SEL_SHIFT 0xCU
  368. #define CFG_L0_SWAP_SEL_MASK 0x7000U
  369. #define CFG_L1_SWAP_SEL_WIDTH 0x3U
  370. #define CFG_L1_SWAP_SEL_SHIFT 0xFU
  371. #define CFG_L1_SWAP_SEL_MASK 0x38000U
  372. #define CFG_L2_SWAP_SEL_WIDTH 0x3U
  373. #define CFG_L2_SWAP_SEL_SHIFT 0x12U
  374. #define CFG_L2_SWAP_SEL_MASK 0x1C0000U
  375. #define CFG_L3_SWAP_SEL_WIDTH 0x3U
  376. #define CFG_L3_SWAP_SEL_SHIFT 0x15U
  377. #define CFG_L3_SWAP_SEL_MASK 0xE00000U
  378. #define CFG_L4_SWAP_SEL_WIDTH 0x3U
  379. #define CFG_L4_SWAP_SEL_SHIFT 0x18U
  380. #define CFG_L4_SWAP_SEL_MASK 0x7000000U
  381. #define MPOSV_31_0__WIDTH 0x20U
  382. #define MPOSV_31_0__SHIFT 0x0U
  383. #define MPOSV_31_0__MASK 0xFFFFFFFFU
  384. #define MPOSV_46_32__WIDTH 0xFU
  385. #define MPOSV_46_32__SHIFT 0x0U
  386. #define MPOSV_46_32__MASK 0x7FFFU
  387. #define RGS_CDTX_PLL_FM_CPLT_WIDTH 0x1U
  388. #define RGS_CDTX_PLL_FM_CPLT_SHIFT 0xFU
  389. #define RGS_CDTX_PLL_FM_CPLT_MASK 0x8000U
  390. #define RGS_CDTX_PLL_FM_OVER_WIDTH 0x1U
  391. #define RGS_CDTX_PLL_FM_OVER_SHIFT 0x10U
  392. #define RGS_CDTX_PLL_FM_OVER_MASK 0x10000U
  393. #define RGS_CDTX_PLL_FM_UNDER_WIDTH 0x1U
  394. #define RGS_CDTX_PLL_FM_UNDER_SHIFT 0x11U
  395. #define RGS_CDTX_PLL_FM_UNDER_MASK 0x20000U
  396. #define RGS_CDTX_PLL_UNLOCK_WIDTH 0x1U
  397. #define RGS_CDTX_PLL_UNLOCK_SHIFT 0x12U
  398. #define RGS_CDTX_PLL_UNLOCK_MASK 0x40000U
  399. #define RG_CDTX_L0N_HSTX_RES_WIDTH 0x5U
  400. #define RG_CDTX_L0N_HSTX_RES_SHIFT 0x13U
  401. #define RG_CDTX_L0N_HSTX_RES_MASK 0xF80000U
  402. #define RG_CDTX_L0P_HSTX_RES_WIDTH 0x5U
  403. #define RG_CDTX_L0P_HSTX_RES_SHIFT 0x18U
  404. #define RG_CDTX_L0P_HSTX_RES_MASK 0x1F000000U
  405. #define RG_CDTX_L1N_HSTX_RES_WIDTH 0x5U
  406. #define RG_CDTX_L1N_HSTX_RES_SHIFT 0x0U
  407. #define RG_CDTX_L1N_HSTX_RES_MASK 0x1FU
  408. #define RG_CDTX_L1P_HSTX_RES_WIDTH 0x5U
  409. #define RG_CDTX_L1P_HSTX_RES_SHIFT 0x5U
  410. #define RG_CDTX_L1P_HSTX_RES_MASK 0x3E0U
  411. #define RG_CDTX_L2N_HSTX_RES_WIDTH 0x5U
  412. #define RG_CDTX_L2N_HSTX_RES_SHIFT 0xAU
  413. #define RG_CDTX_L2N_HSTX_RES_MASK 0x7C00U
  414. #define RG_CDTX_L2P_HSTX_RES_WIDTH 0x5U
  415. #define RG_CDTX_L2P_HSTX_RES_SHIFT 0xFU
  416. #define RG_CDTX_L2P_HSTX_RES_MASK 0xF8000U
  417. #define RG_CDTX_L3N_HSTX_RES_WIDTH 0x5U
  418. #define RG_CDTX_L3N_HSTX_RES_SHIFT 0x14U
  419. #define RG_CDTX_L3N_HSTX_RES_MASK 0x1F00000U
  420. #define RG_CDTX_L3P_HSTX_RES_WIDTH 0x5U
  421. #define RG_CDTX_L3P_HSTX_RES_SHIFT 0x19U
  422. #define RG_CDTX_L3P_HSTX_RES_MASK 0x3E000000U
  423. #define RG_CDTX_L4N_HSTX_RES_WIDTH 0x5U
  424. #define RG_CDTX_L4N_HSTX_RES_SHIFT 0x0U
  425. #define RG_CDTX_L4N_HSTX_RES_MASK 0x1FU
  426. #define RG_CDTX_L4P_HSTX_RES_WIDTH 0x5U
  427. #define RG_CDTX_L4P_HSTX_RES_SHIFT 0x5U
  428. #define RG_CDTX_L4P_HSTX_RES_MASK 0x3E0U
  429. #define RG_CDTX_PLL_FBK_FRA_WIDTH 0x18U
  430. #define RG_CDTX_PLL_FBK_FRA_SHIFT 0x0U
  431. #define RG_CDTX_PLL_FBK_FRA_MASK 0xFFFFFFU
  432. #define RG_CDTX_PLL_FBK_INT_WIDTH 0x9U
  433. #define RG_CDTX_PLL_FBK_INT_SHIFT 0x0U
  434. #define RG_CDTX_PLL_FBK_INT_MASK 0x1FFU
  435. #define RG_CDTX_PLL_FM_EN_WIDTH 0x1U
  436. #define RG_CDTX_PLL_FM_EN_SHIFT 0x9U
  437. #define RG_CDTX_PLL_FM_EN_MASK 0x200U
  438. #define RG_CDTX_PLL_LDO_STB_X2_EN_WIDTH 0x1U
  439. #define RG_CDTX_PLL_LDO_STB_X2_EN_SHIFT 0xAU
  440. #define RG_CDTX_PLL_LDO_STB_X2_EN_MASK 0x400U
  441. #define RG_CDTX_PLL_PRE_DIV_WIDTH 0x2U
  442. #define RG_CDTX_PLL_PRE_DIV_SHIFT 0xBU
  443. #define RG_CDTX_PLL_PRE_DIV_MASK 0x1800U
  444. #define RG_CDTX_PLL_SSC_DELTA_WIDTH 0x12U
  445. #define RG_CDTX_PLL_SSC_DELTA_SHIFT 0xDU
  446. #define RG_CDTX_PLL_SSC_DELTA_MASK 0x7FFFE000U
  447. #define RG_CDTX_PLL_SSC_DELTA_INIT_WIDTH 0x12U
  448. #define RG_CDTX_PLL_SSC_DELTA_INIT_SHIFT 0x0U
  449. #define RG_CDTX_PLL_SSC_DELTA_INIT_MASK 0x3FFFFU
  450. #define RG_CDTX_PLL_SSC_EN_WIDTH 0x1U
  451. #define RG_CDTX_PLL_SSC_EN_SHIFT 0x12U
  452. #define RG_CDTX_PLL_SSC_EN_MASK 0x40000U
  453. #define RG_CDTX_PLL_SSC_PRD_WIDTH 0xAU
  454. #define RG_CDTX_PLL_SSC_PRD_SHIFT 0x13U
  455. #define RG_CDTX_PLL_SSC_PRD_MASK 0x1FF80000U
  456. #define RG_CLANE_HS_CLK_POST_TIME_WIDTH 0x8U
  457. #define RG_CLANE_HS_CLK_POST_TIME_SHIFT 0x0U
  458. #define RG_CLANE_HS_CLK_POST_TIME_MASK 0xFFU
  459. #define RG_CLANE_HS_CLK_PRE_TIME_WIDTH 0x8U
  460. #define RG_CLANE_HS_CLK_PRE_TIME_SHIFT 0x8U
  461. #define RG_CLANE_HS_CLK_PRE_TIME_MASK 0xFF00U
  462. #define RG_CLANE_HS_PRE_TIME_WIDTH 0x8U
  463. #define RG_CLANE_HS_PRE_TIME_SHIFT 0x10U
  464. #define RG_CLANE_HS_PRE_TIME_MASK 0xFF0000U
  465. #define RG_CLANE_HS_TRAIL_TIME_WIDTH 0x8U
  466. #define RG_CLANE_HS_TRAIL_TIME_SHIFT 0x18U
  467. #define RG_CLANE_HS_TRAIL_TIME_MASK 0xFF000000U
  468. #define RG_CLANE_HS_ZERO_TIME_WIDTH 0x8U
  469. #define RG_CLANE_HS_ZERO_TIME_SHIFT 0x0U
  470. #define RG_CLANE_HS_ZERO_TIME_MASK 0xFFU
  471. #define RG_DLANE_HS_PRE_TIME_WIDTH 0x8U
  472. #define RG_DLANE_HS_PRE_TIME_SHIFT 0x8U
  473. #define RG_DLANE_HS_PRE_TIME_MASK 0xFF00U
  474. #define RG_DLANE_HS_TRAIL_TIME_WIDTH 0x8U
  475. #define RG_DLANE_HS_TRAIL_TIME_SHIFT 0x10U
  476. #define RG_DLANE_HS_TRAIL_TIME_MASK 0xFF0000U
  477. #define RG_DLANE_HS_ZERO_TIME_WIDTH 0x8U
  478. #define RG_DLANE_HS_ZERO_TIME_SHIFT 0x18U
  479. #define RG_DLANE_HS_ZERO_TIME_MASK 0xFF000000U
  480. #define RG_EXTD_CYCLE_SEL_WIDTH 0x3U
  481. #define RG_EXTD_CYCLE_SEL_SHIFT 0x0U
  482. #define RG_EXTD_CYCLE_SEL_MASK 0x7U
  483. #define SCFG_C_HS_PRE_ZERO_TIME_WIDTH 0x20U
  484. #define SCFG_C_HS_PRE_ZERO_TIME_SHIFT 0x0U
  485. #define SCFG_C_HS_PRE_ZERO_TIME_MASK 0xFFFFFFFFU
  486. #define SCFG_DPHY_SRC_SEL_WIDTH 0x1U
  487. #define SCFG_DPHY_SRC_SEL_SHIFT 0x0U
  488. #define SCFG_DPHY_SRC_SEL_MASK 0x1U
  489. #define SCFG_DSI_TXREADY_ESC_SEL_WIDTH 0x2U
  490. #define SCFG_DSI_TXREADY_ESC_SEL_SHIFT 0x1U
  491. #define SCFG_DSI_TXREADY_ESC_SEL_MASK 0x6U
  492. #define SCFG_PPI_C_READY_SEL_WIDTH 0x2U
  493. #define SCFG_PPI_C_READY_SEL_SHIFT 0x3U
  494. #define SCFG_PPI_C_READY_SEL_MASK 0x18U
  495. #define VCONTROL_WIDTH 0x5U
  496. #define VCONTROL_SHIFT 0x5U
  497. #define VCONTROL_MASK 0x3E0U
  498. #define XCFGI_DW00_WIDTH 0x20U
  499. #define XCFGI_DW00_SHIFT 0x0U
  500. #define XCFGI_DW00_MASK 0xFFFFFFFFU
  501. #define XCFGI_DW01_WIDTH 0x20U
  502. #define XCFGI_DW01_SHIFT 0x0U
  503. #define XCFGI_DW01_MASK 0xFFFFFFFFU
  504. #define XCFGI_DW02_WIDTH 0x20U
  505. #define XCFGI_DW02_SHIFT 0x0U
  506. #define XCFGI_DW02_MASK 0xFFFFFFFFU
  507. #define XCFGI_DW03_WIDTH 0x20U
  508. #define XCFGI_DW03_SHIFT 0x0U
  509. #define XCFGI_DW03_MASK 0xFFFFFFFFU
  510. #define XCFGI_DW04_WIDTH 0x20U
  511. #define XCFGI_DW04_SHIFT 0x0U
  512. #define XCFGI_DW04_MASK 0xFFFFFFFFU
  513. #define XCFGI_DW05_WIDTH 0x20U
  514. #define XCFGI_DW05_SHIFT 0x0U
  515. #define XCFGI_DW05_MASK 0xFFFFFFFFU
  516. #define XCFGI_DW06_WIDTH 0x20U
  517. #define XCFGI_DW06_SHIFT 0x0U
  518. #define XCFGI_DW06_MASK 0xFFFFFFFFU
  519. #define XCFGI_DW07_WIDTH 0x20U
  520. #define XCFGI_DW07_SHIFT 0x0U
  521. #define XCFGI_DW07_MASK 0xFFFFFFFFU
  522. #define XCFGI_DW08_WIDTH 0x20U
  523. #define XCFGI_DW08_SHIFT 0x0U
  524. #define XCFGI_DW08_MASK 0xFFFFFFFFU
  525. #define XCFGI_DW09_WIDTH 0x20U
  526. #define XCFGI_DW09_SHIFT 0x0U
  527. #define XCFGI_DW09_MASK 0xFFFFFFFFU
  528. #define XCFGI_DW0A_WIDTH 0x20U
  529. #define XCFGI_DW0A_SHIFT 0x0U
  530. #define XCFGI_DW0A_MASK 0xFFFFFFFFU
  531. #define XCFGI_DW0B_WIDTH 0x20U
  532. #define XCFGI_DW0B_SHIFT 0x0U
  533. #define XCFGI_DW0B_MASK 0xFFFFFFFFU
  534. #define DBG1_MUX_DOUT_WIDTH 0x8U
  535. #define DBG1_MUX_DOUT_SHIFT 0x0U
  536. #define DBG1_MUX_DOUT_MASK 0xFFU
  537. #define DBG1_MUX_SEL_WIDTH 0x5U
  538. #define DBG1_MUX_SEL_SHIFT 0x8U
  539. #define DBG1_MUX_SEL_MASK 0x1F00U
  540. #define DBG2_MUX_DOUT_WIDTH 0x8U
  541. #define DBG2_MUX_DOUT_SHIFT 0xDU
  542. #define DBG2_MUX_DOUT_MASK 0x1FE000U
  543. #define DBG2_MUX_SEL_WIDTH 0x5U
  544. #define DBG2_MUX_SEL_SHIFT 0x15U
  545. #define DBG2_MUX_SEL_MASK 0x3E00000U
  546. #define REFCLK_IN_SEL_WIDTH 0x3U
  547. #define REFCLK_IN_SEL_SHIFT 0x1AU
  548. #define REFCLK_IN_SEL_MASK 0x1C000000U
  549. #define RESETB_WIDTH 0x1U
  550. #define RESETB_SHIFT 0x1DU
  551. #define RESETB_MASK 0x20000000U
  552. //aonsys con
  553. #define AON_GP_REG_WIDTH 0x20U
  554. #define AON_GP_REG_SHIFT 0x0U
  555. #define AON_GP_REG_MASK 0xFFFFFFFFU
  556. #define M31_DPHY_REFCLK_RESERVED 0
  557. #define M31_DPHY_REFCLK_12M 1
  558. #define M31_DPHY_REFCLK_19_2M 2
  559. #define M31_DPHY_REFCLK_25M 3
  560. #define M31_DPHY_REFCLK_26M 4
  561. #define M31_DPHY_REFCLK_27M 5
  562. #define M31_DPHY_REFCLK_38_4M 6
  563. #define M31_DPHY_REFCLK_52M 7
  564. #define M31_DPHY_REFCLK_BUTT 8
  565. #define DPHY_TX_PSW_EN_MASK (1<<30)
  566. struct m31_dphy_config {
  567. int ref_clk;
  568. unsigned long bitrate;
  569. uint32_t pll_prev_div, pll_fbk_int, pll_fbk_fra, extd_cycle_sel;
  570. uint32_t dlane_hs_pre_time, dlane_hs_zero_time, dlane_hs_trail_time;
  571. uint32_t clane_hs_pre_time, clane_hs_zero_time, clane_hs_trail_time;
  572. uint32_t clane_hs_clk_pre_time, clane_hs_clk_post_time;
  573. };
  574. #define M31_DPHY_REFCLK M31_DPHY_REFCLK_12M
  575. #define M31_DPHY_BITRATE_ALIGN 10000000
  576. static const struct m31_dphy_config m31_dphy_configs[] = {
  577. #if (M31_DPHY_REFCLK == M31_DPHY_REFCLK_25M)
  578. {25000000, 100000000, 0x1, 0x80, 0x000000, 0x4, 0x10, 0x21, 0x17, 0x07, 0x35, 0x0F, 0x0F, 0x73,},
  579. {25000000, 200000000, 0x1, 0x80, 0x000000, 0x3, 0x0C, 0x1B, 0x13, 0x07, 0x35, 0x0F, 0x07, 0x3F,},
  580. {25000000, 300000000, 0x1, 0xC0, 0x000000, 0x3, 0x11, 0x25, 0x19, 0x0A, 0x50, 0x15, 0x07, 0x45,},
  581. {25000000, 400000000, 0x1, 0x80, 0x000000, 0x2, 0x0A, 0x18, 0x11, 0x07, 0x35, 0x0F, 0x03, 0x25,},
  582. {25000000, 500000000, 0x1, 0xA0, 0x000000, 0x2, 0x0C, 0x1D, 0x14, 0x09, 0x42, 0x12, 0x03, 0x28,},
  583. {25000000, 600000000, 0x1, 0xC0, 0x000000, 0x2, 0x0E, 0x23, 0x17, 0x0A, 0x50, 0x15, 0x03, 0x2B,},
  584. {25000000, 700000000, 0x1, 0x70, 0x000000, 0x1, 0x08, 0x14, 0x0F, 0x06, 0x2F, 0x0E, 0x01, 0x16,},
  585. {25000000, 800000000, 0x1, 0x80, 0x000000, 0x1, 0x09, 0x17, 0x10, 0x07, 0x35, 0x0F, 0x01, 0x18,},
  586. {25000000, 900000000, 0x1, 0x90, 0x000000, 0x1, 0x0A, 0x19, 0x12, 0x08, 0x3C, 0x10, 0x01, 0x19,},
  587. {25000000, 1000000000, 0x1, 0xA0, 0x000000, 0x1, 0x0B, 0x1C, 0x13, 0x09, 0x42, 0x12, 0x01, 0x1B,},
  588. {25000000, 1100000000, 0x1, 0xB0, 0x000000, 0x1, 0x0C, 0x1E, 0x15, 0x09, 0x4A, 0x14, 0x01, 0x1D,},
  589. {25000000, 1200000000, 0x1, 0xC0, 0x000000, 0x1, 0x0E, 0x20, 0x16, 0x0A, 0x50, 0x15, 0x01, 0x1E,},
  590. {25000000, 1300000000, 0x1, 0x68, 0x000000, 0x0, 0x07, 0x12, 0x0D, 0x05, 0x2C, 0x0D, 0x00, 0x0F,},
  591. {25000000, 1400000000, 0x1, 0x70, 0x000000, 0x0, 0x07, 0x14, 0x0E, 0x06, 0x2F, 0x0E, 0x00, 0x10,},
  592. {25000000, 1500000000, 0x1, 0x78, 0x000000, 0x0, 0x08, 0x14, 0x0F, 0x06, 0x32, 0x0E, 0x00, 0x11,},
  593. {25000000, 1600000000, 0x1, 0x80, 0x000000, 0x0, 0x09, 0x15, 0x10, 0x07, 0x35, 0x0F, 0x00, 0x12,},
  594. {25000000, 1700000000, 0x1, 0x88, 0x000000, 0x0, 0x09, 0x17, 0x10, 0x07, 0x39, 0x10, 0x00, 0x12,},
  595. {25000000, 1800000000, 0x1, 0x90, 0x000000, 0x0, 0x0A, 0x18, 0x11, 0x08, 0x3C, 0x10, 0x00, 0x13,},
  596. {25000000, 1900000000, 0x1, 0x98, 0x000000, 0x0, 0x0A, 0x1A, 0x12, 0x08, 0x3F, 0x11, 0x00, 0x14,},
  597. {25000000, 2000000000, 0x1, 0xA0, 0x000000, 0x0, 0x0B, 0x1B, 0x13, 0x09, 0x42, 0x12, 0x00, 0x15,},
  598. {25000000, 2100000000, 0x1, 0xA8, 0x000000, 0x0, 0x0B, 0x1C, 0x13, 0x09, 0x46, 0x13, 0x00, 0x15,},
  599. {25000000, 2200000000, 0x1, 0xB0, 0x000000, 0x0, 0x0C, 0x1D, 0x14, 0x09, 0x4A, 0x14, 0x00, 0x16,},
  600. {25000000, 2300000000, 0x1, 0xB8, 0x000000, 0x0, 0x0C, 0x1F, 0x15, 0x0A, 0x4C, 0x14, 0x00, 0x17,},
  601. {25000000, 2400000000, 0x1, 0xC0, 0x000000, 0x0, 0x0D, 0x20, 0x16, 0x0A, 0x50, 0x15, 0x00, 0x18,},
  602. {25000000, 2500000000, 0x1, 0xC8, 0x000000, 0x0, 0x0E, 0x21, 0x16, 0x0B, 0x53, 0x16, 0x00, 0x18,},
  603. #elif (M31_DPHY_REFCLK == M31_DPHY_REFCLK_12M)
  604. {12000000, 160000000, 0x0, 0x6a, 0xaa<<16|0xaa<<8|0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d,},
  605. {12000000, 170000000, 0x0, 0x71, 0x55<<16|0x55<<8|0x55, 0x3, 0xb, 0x18, 0x11, 0x5, 0x2e, 0xd, 0x7, 0x3d,},
  606. {12000000, 180000000, 0x0, 0x78, 0x0<<16|0x0<<8|0x0, 0x3, 0xb, 0x19, 0x12, 0x6, 0x30, 0xe, 0x7, 0x3e,},
  607. {12000000, 190000000, 0x0, 0x7e, 0xaa<<16|0xaa<<8|0xaa, 0x3, 0xc, 0x1a, 0x12, 0x6, 0x33, 0xe, 0x7, 0x3e,},
  608. {12000000, 200000000, 0x0, 0x85, 0x55<<16|0x55<<8|0x55, 0x3, 0xc, 0x1b, 0x13, 0x7, 0x35, 0xf, 0x7, 0x3f,},
  609. {12000000, 320000000, 0x0, 0x6a, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0x8, 0x14, 0xf, 0x5, 0x2b, 0xd, 0x3, 0x23,},
  610. {12000000, 330000000, 0x0, 0x6e, 0x0<<16|0x0<<8|0x0, 0x2, 0x8, 0x15, 0xf, 0x5, 0x2d, 0xd, 0x3, 0x23,},
  611. {12000000, 340000000, 0x0, 0x71, 0x55<<16|0x55<<8|0x55, 0x2, 0x9, 0x15, 0xf, 0x5, 0x2e, 0xd, 0x3, 0x23,},
  612. {12000000, 350000000, 0x0, 0x74, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0x9, 0x15, 0x10, 0x6, 0x2f, 0xe, 0x3, 0x24,},
  613. {12000000, 360000000, 0x0, 0x78, 0x0<<16|0x0<<8|0x0, 0x2, 0x9, 0x16, 0x10, 0x6, 0x30, 0xe, 0x3, 0x24,},
  614. {12000000, 370000000, 0x0, 0x7b, 0x55<<16|0x55<<8|0x55, 0x2, 0x9, 0x17, 0x10, 0x6, 0x32, 0xe, 0x3, 0x24,},
  615. {12000000, 380000000, 0x0, 0x7e, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xa, 0x17, 0x10, 0x6, 0x33, 0xe, 0x3, 0x24,},
  616. {12000000, 390000000, 0x0, 0x82, 0x0<<16|0x0<<8|0x0, 0x2, 0xa, 0x17, 0x11, 0x6, 0x35, 0xf, 0x3, 0x25,},
  617. {12000000, 400000000, 0x0, 0x85, 0x55<<16|0x55<<8|0x55, 0x2, 0xa, 0x18, 0x11, 0x7, 0x35, 0xf, 0x3, 0x25,},
  618. {12000000, 410000000, 0x0, 0x88, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xa, 0x19, 0x11, 0x7, 0x37, 0xf, 0x3, 0x25,},
  619. {12000000, 420000000, 0x0, 0x8c, 0x0<<16|0x0<<8|0x0, 0x2, 0xa, 0x19, 0x12, 0x7, 0x38, 0x10, 0x3, 0x26,},
  620. {12000000, 430000000, 0x0, 0x8f, 0x55<<16|0x55<<8|0x55, 0x2, 0xb, 0x19, 0x12, 0x7, 0x39, 0x10, 0x3, 0x26,},
  621. {12000000, 440000000, 0x0, 0x92, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xb, 0x1a, 0x12, 0x7, 0x3b, 0x10, 0x3, 0x26,},
  622. {12000000, 450000000, 0x0, 0x96, 0x0<<16|0x0<<8|0x0, 0x2, 0xb, 0x1b, 0x12, 0x8, 0x3c, 0x10, 0x3, 0x26,},
  623. {12000000, 460000000, 0x0, 0x99, 0x55<<16|0x55<<8|0x55, 0x2, 0xb, 0x1b, 0x13, 0x8, 0x3d, 0x11, 0x3, 0x27,},
  624. {12000000, 470000000, 0x0, 0x9c, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xc, 0x1b, 0x13, 0x8, 0x3e, 0x11, 0x3, 0x27,},
  625. {12000000, 480000000, 0x0, 0xa0, 0x0<<16|0x0<<8|0x0, 0x2, 0xc, 0x1c, 0x13, 0x8, 0x40, 0x11, 0x3, 0x27,},
  626. {12000000, 490000000, 0x0, 0xa3, 0x55<<16|0x55<<8|0x55, 0x2, 0xc, 0x1d, 0x14, 0x8, 0x42, 0x12, 0x3, 0x28,},
  627. {12000000, 500000000, 0x0, 0xa6, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xc, 0x1d, 0x14, 0x9, 0x42, 0x12, 0x3, 0x28,},
  628. {12000000, 510000000, 0x0, 0xaa, 0x0<<16|0x0<<8|0x0, 0x2, 0xc, 0x1e, 0x14, 0x9, 0x44, 0x12, 0x3, 0x28,},
  629. {12000000, 520000000, 0x0, 0xad, 0x55<<16|0x55<<8|0x55, 0x2, 0xd, 0x1e, 0x15, 0x9, 0x45, 0x13, 0x3, 0x29,},
  630. {12000000, 530000000, 0x0, 0xb0, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xd, 0x1e, 0x15, 0x9, 0x47, 0x13, 0x3, 0x29,},
  631. {12000000, 540000000, 0x0, 0xb4, 0x0<<16|0x0<<8|0x0, 0x2, 0xd, 0x1f, 0x15, 0x9, 0x48, 0x13, 0x3, 0x29,},
  632. {12000000, 550000000, 0x0, 0xb7, 0x55<<16|0x55<<8|0x55, 0x2, 0xd, 0x20, 0x16, 0x9, 0x4a, 0x14, 0x3, 0x2a,},
  633. {12000000, 560000000, 0x0, 0xba, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xe, 0x20, 0x16, 0xa, 0x4a, 0x14, 0x3, 0x2a,},
  634. {12000000, 570000000, 0x0, 0xbe, 0x0<<16|0x0<<8|0x0, 0x2, 0xe, 0x20, 0x16, 0xa, 0x4c, 0x14, 0x3, 0x2a,},
  635. {12000000, 580000000, 0x0, 0xc1, 0x55<<16|0x55<<8|0x55, 0x2, 0xe, 0x21, 0x16, 0xa, 0x4d, 0x14, 0x3, 0x2a,},
  636. {12000000, 590000000, 0x0, 0xc4, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xe, 0x22, 0x17, 0xa, 0x4f, 0x15, 0x3, 0x2b,},
  637. {12000000, 600000000, 0x0, 0xc8, 0x0<<16|0x0<<8|0x0, 0x2, 0xe, 0x23, 0x17, 0xa, 0x50, 0x15, 0x3, 0x2b,},
  638. {12000000, 610000000, 0x0, 0xcb, 0x55<<16|0x55<<8|0x55, 0x2, 0xf, 0x22, 0x17, 0xb, 0x50, 0x15, 0x3, 0x2b,},
  639. {12000000, 620000000, 0x0, 0xce, 0xaa<<16|0xaa<<8|0xaa, 0x2, 0xf, 0x23, 0x18, 0xb, 0x52, 0x16, 0x3, 0x2c,},
  640. {12000000, 630000000, 0x0, 0x69, 0x0<<16|0x0<<8|0x0, 0x1, 0x7, 0x12, 0xd, 0x5, 0x2a, 0xc, 0x1, 0x15,},
  641. {12000000, 640000000, 0x0, 0x6a, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x7, 0x13, 0xe, 0x5, 0x2b, 0xd, 0x1, 0x16,},
  642. {12000000, 650000000, 0x0, 0x6c, 0x55<<16|0x55<<8|0x55, 0x1, 0x7, 0x13, 0xe, 0x5, 0x2c, 0xd, 0x1, 0x16,},
  643. {12000000, 660000000, 0x0, 0x6e, 0x0<<16|0x0<<8|0x0, 0x1, 0x7, 0x13, 0xe, 0x5, 0x2d, 0xd, 0x1, 0x16,},
  644. {12000000, 670000000, 0x0, 0x6f, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x8, 0x13, 0xe, 0x5, 0x2d, 0xd, 0x1, 0x16,},
  645. {12000000, 680000000, 0x0, 0x71, 0x55<<16|0x55<<8|0x55, 0x1, 0x8, 0x13, 0xe, 0x5, 0x2e, 0xd, 0x1, 0x16,},
  646. {12000000, 690000000, 0x0, 0x73, 0x0<<16|0x0<<8|0x0, 0x1, 0x8, 0x14, 0xe, 0x6, 0x2e, 0xd, 0x1, 0x16,},
  647. {12000000, 700000000, 0x0, 0x74, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x8, 0x14, 0xf, 0x6, 0x2f, 0xe, 0x1, 0x16,},
  648. {12000000, 710000000, 0x0, 0x76, 0x55<<16|0x55<<8|0x55, 0x1, 0x8, 0x14, 0xf, 0x6, 0x2f, 0xe, 0x1, 0x17,},
  649. {12000000, 720000000, 0x0, 0x78, 0x0<<16|0x0<<8|0x0, 0x1, 0x8, 0x15, 0xf, 0x6, 0x30, 0xe, 0x1, 0x17,},
  650. {12000000, 730000000, 0x0, 0x79, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x8, 0x15, 0xf, 0x6, 0x31, 0xe, 0x1, 0x17,},
  651. {12000000, 740000000, 0x0, 0x7b, 0x55<<16|0x55<<8|0x55, 0x1, 0x8, 0x15, 0xf, 0x6, 0x32, 0xe, 0x1, 0x17,},
  652. {12000000, 750000000, 0x0, 0x7d, 0x0<<16|0x0<<8|0x0, 0x1, 0x8, 0x16, 0xf, 0x6, 0x32, 0xe, 0x1, 0x17,},
  653. {12000000, 760000000, 0x0, 0x7e, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x9, 0x15, 0xf, 0x6, 0x33, 0xe, 0x1, 0x17,},
  654. {12000000, 770000000, 0x0, 0x80, 0x55<<16|0x55<<8|0x55, 0x1, 0x9, 0x15, 0x10, 0x6, 0x34, 0xf, 0x1, 0x18,},
  655. {12000000, 780000000, 0x0, 0x82, 0x0<<16|0x0<<8|0x0, 0x1, 0x9, 0x16, 0x10, 0x6, 0x35, 0xf, 0x1, 0x18,},
  656. {12000000, 790000000, 0x0, 0x83, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x9, 0x16, 0x10, 0x7, 0x34, 0xf, 0x1, 0x18,},
  657. {12000000, 800000000, 0x0, 0x85, 0x55<<16|0x55<<8|0x55, 0x1, 0x9, 0x17, 0x10, 0x7, 0x35, 0xf, 0x1, 0x18,},
  658. {12000000, 810000000, 0x0, 0x87, 0x0<<16|0x0<<8|0x0, 0x1, 0x9, 0x17, 0x10, 0x7, 0x36, 0xf, 0x1, 0x18,},
  659. {12000000, 820000000, 0x0, 0x88, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0x9, 0x17, 0x10, 0x7, 0x37, 0xf, 0x1, 0x18,},
  660. {12000000, 830000000, 0x0, 0x8a, 0x55<<16|0x55<<8|0x55, 0x1, 0x9, 0x18, 0x10, 0x7, 0x37, 0xf, 0x1, 0x18,},
  661. {12000000, 840000000, 0x0, 0x8c, 0x0<<16|0x0<<8|0x0, 0x1, 0x9, 0x18, 0x11, 0x7, 0x38, 0x10, 0x1, 0x19,},
  662. {12000000, 850000000, 0x0, 0x8d, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xa, 0x17, 0x11, 0x7, 0x39, 0x10, 0x1, 0x19,},
  663. {12000000, 860000000, 0x0, 0x8f, 0x55<<16|0x55<<8|0x55, 0x1, 0xa, 0x18, 0x11, 0x7, 0x39, 0x10, 0x1, 0x19,},
  664. {12000000, 870000000, 0x0, 0x91, 0x0<<16|0x0<<8|0x0, 0x1, 0xa, 0x18, 0x11, 0x7, 0x3a, 0x10, 0x1, 0x19,},
  665. {12000000, 880000000, 0x0, 0x92, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xa, 0x18, 0x11, 0x7, 0x3b, 0x10, 0x1, 0x19,},
  666. {12000000, 890000000, 0x0, 0x94, 0x55<<16|0x55<<8|0x55, 0x1, 0xa, 0x19, 0x11, 0x7, 0x3c, 0x10, 0x1, 0x19,},
  667. {12000000, 900000000, 0x0, 0x96, 0x0<<16|0x0<<8|0x0, 0x1, 0xa, 0x19, 0x12, 0x8, 0x3c, 0x10, 0x1, 0x19,},
  668. {12000000, 910000000, 0x0, 0x97, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xa, 0x19, 0x12, 0x8, 0x3c, 0x11, 0x1, 0x1a,},
  669. {12000000, 920000000, 0x0, 0x99, 0x55<<16|0x55<<8|0x55, 0x1, 0xa, 0x1a, 0x12, 0x8, 0x3d, 0x11, 0x1, 0x1a,},
  670. {12000000, 930000000, 0x0, 0x9b, 0x0<<16|0x0<<8|0x0, 0x1, 0xa, 0x1a, 0x12, 0x8, 0x3e, 0x11, 0x1, 0x1a,},
  671. {12000000, 940000000, 0x0, 0x9c, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xb, 0x1a, 0x12, 0x8, 0x3e, 0x11, 0x1, 0x1a,},
  672. {12000000, 950000000, 0x0, 0x9e, 0x55<<16|0x55<<8|0x55, 0x1, 0xb, 0x1a, 0x12, 0x8, 0x3f, 0x11, 0x1, 0x1a,},
  673. {12000000, 960000000, 0x0, 0xa0, 0x0<<16|0x0<<8|0x0, 0x1, 0xb, 0x1a, 0x12, 0x8, 0x40, 0x11, 0x1, 0x1a,},
  674. {12000000, 970000000, 0x0, 0xa1, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xb, 0x1b, 0x13, 0x8, 0x41, 0x12, 0x1, 0x1b,},
  675. {12000000, 980000000, 0x0, 0xa3, 0x55<<16|0x55<<8|0x55, 0x1, 0xb, 0x1b, 0x13, 0x8, 0x42, 0x12, 0x1, 0x1b,},
  676. {12000000, 990000000, 0x0, 0xa5, 0x0<<16|0x0<<8|0x0, 0x1, 0xb, 0x1b, 0x13, 0x8, 0x42, 0x12, 0x1, 0x1b,},
  677. {12000000, 1000000000, 0x0, 0xa6, 0xaa<<16|0xaa<<8|0xaa, 0x1, 0xb, 0x1c, 0x13, 0x9, 0x42, 0x12, 0x1, 0x1b,},
  678. #endif
  679. };
  680. struct dsi_sf_priv {
  681. void __iomem *dsi_reg;
  682. void __iomem *phy_reg;//0x295e0000
  683. void __iomem *sys_reg;
  684. struct mipi_dsi_device device;
  685. struct udevice *panel;
  686. struct udevice *dsi_host;
  687. unsigned int data_lanes;
  688. struct display_timing timings;
  689. struct clk dsi_sys_clk;
  690. struct clk apb_clk;
  691. struct clk txesc_clk;
  692. struct clk dpi_clk;
  693. struct clk dphy_txesc_clk;
  694. struct reset_ctl dpi_rst;
  695. struct reset_ctl apb_rst;
  696. struct reset_ctl rxesc_rst;
  697. struct reset_ctl sys_rst;
  698. struct reset_ctl txbytehs_rst;
  699. struct reset_ctl txesc_rst;
  700. struct reset_ctl dphy_sys;
  701. struct reset_ctl dphy_txbytehs;
  702. uint32_t direct_cmd_fifo_depth;
  703. uint32_t rx_fifo_depth;
  704. int direct_cmd_comp;
  705. bool link_initialized;
  706. };
  707. int rk_mipi_read_timing(struct udevice *dev,
  708. struct display_timing *timing);
  709. int rk_mipi_dsi_enable(struct udevice *dev,
  710. const struct display_timing *timing);
  711. int rk_mipi_phy_enable(struct udevice *dev);
  712. #endif