mipi_dsi_northwest_regs.h 4.6 KB

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  1. /*
  2. * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved.
  3. * Copyright 2017 NXP
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #ifndef __MIPI_DSI_NORTHWEST_REGS_H
  8. #define __MIPI_DSI_NORTHWEST_REGS_H
  9. /* ---------------------------- register offsets --------------------------- */
  10. /* sim */
  11. #define SIM_SOPT1 0x0
  12. #define MIPI_ISO_DISABLE 0x8
  13. #define SIM_SOPT1CFG 0x4
  14. #define DSI_RST_DPI_N 0x80000000
  15. #define DSI_RST_ESC_N 0x40000000
  16. #define DSI_RST_BYTE_N 0x20000000
  17. #define DSI_SD 0x200
  18. #define DSI_CM 0x100
  19. #define DSI_PLL_EN 0x80
  20. /* dphy */
  21. #define DPHY_PD_DPHY 0x300
  22. #define DPHY_M_PRG_HS_PREPARE 0x304
  23. #define DPHY_MC_PRG_HS_PREPARE 0x308
  24. #define DPHY_M_PRG_HS_ZERO 0x30c
  25. #define DPHY_MC_PRG_HS_ZERO 0x310
  26. #define DPHY_M_PRG_HS_TRAIL 0x314
  27. #define DPHY_MC_PRG_HS_TRAIL 0x318
  28. #define DPHY_PD_PLL 0x31c
  29. #define DPHY_TST 0x320
  30. #define DPHY_CN 0x324
  31. #define DPHY_CM 0x328
  32. #define DPHY_CO 0x32c
  33. #define DPHY_LOCK 0x330
  34. #define DPHY_LOCK_BYP 0x334
  35. #define DPHY_RTERM_SEL 0x338
  36. #define DPHY_AUTO_PD_EN 0x33c
  37. #define DPHY_RXLPRP 0x340
  38. #define DPHY_RXCDRP 0x344
  39. /* host */
  40. #define HOST_CFG_NUM_LANES 0x0
  41. #define HOST_CFG_NONCONTINUOUS_CLK 0x4
  42. #define HOST_CFG_T_PRE 0x8
  43. #define HOST_CFG_T_POST 0xc
  44. #define HOST_CFG_TX_GAP 0x10
  45. #define HOST_CFG_AUTOINSERT_EOTP 0x14
  46. #define HOST_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
  47. #define HOST_CFG_HTX_TO_COUNT 0x1c
  48. #define HOST_CFG_LRX_H_TO_COUNT 0x20
  49. #define HOST_CFG_BTA_H_TO_COUNT 0x24
  50. #define HOST_CFG_TWAKEUP 0x28
  51. #define HOST_CFG_STATUS_OUT 0x2c
  52. #define HOST_RX_ERROR_STATUS 0x30
  53. /* dpi */
  54. #define DPI_PIXEL_PAYLOAD_SIZE 0x200
  55. #define DPI_PIXEL_FIFO_SEND_LEVEL 0x204
  56. #define DPI_INTERFACE_COLOR_CODING 0x208
  57. #define DPI_PIXEL_FORMAT 0x20c
  58. #define DPI_VSYNC_POLARITY 0x210
  59. #define DPI_HSYNC_POLARITY 0x214
  60. #define DPI_VIDEO_MODE 0x218
  61. #define DPI_HFP 0x21c
  62. #define DPI_HBP 0x220
  63. #define DPI_HSA 0x224
  64. #define DPI_ENABLE_MULT_PKTS 0x228
  65. #define DPI_VBP 0x22c
  66. #define DPI_VFP 0x230
  67. #define DPI_BLLP_MODE 0x234
  68. #define DPI_USE_NULL_PKT_BLLP 0x238
  69. #define DPI_VACTIVE 0x23c
  70. #define DPI_VC 0x240
  71. /* apb pkt */
  72. #define HOST_TX_PAYLOAD 0x280
  73. #define HOST_PKT_CONTROL 0x284
  74. #define HOST_PKT_CONTROL_WC(x) (((x) & 0xffff) << 0)
  75. #define HOST_PKT_CONTROL_VC(x) (((x) & 0x3) << 16)
  76. #define HOST_PKT_CONTROL_DT(x) (((x) & 0x3f) << 18)
  77. #define HOST_PKT_CONTROL_HS_SEL(x) (((x) & 0x1) << 24)
  78. #define HOST_PKT_CONTROL_BTA_TX(x) (((x) & 0x1) << 25)
  79. #define HOST_PKT_CONTROL_BTA_NO_TX(x) (((x) & 0x1) << 26)
  80. #define HOST_SEND_PACKET 0x288
  81. #define HOST_PKT_STATUS 0x28c
  82. #define HOST_PKT_FIFO_WR_LEVEL 0x290
  83. #define HOST_PKT_FIFO_RD_LEVEL 0x294
  84. #define HOST_PKT_RX_PAYLOAD 0x298
  85. #define HOST_PKT_RX_PKT_HEADER 0x29c
  86. #define HOST_PKT_RX_PKT_HEADER_WC(x) (((x) & 0xffff) << 0)
  87. #define HOST_PKT_RX_PKT_HEADER_DT(x) (((x) & 0x3f) << 16)
  88. #define HOST_PKT_RX_PKT_HEADER_VC(x) (((x) & 0x3) << 22)
  89. #define HOST_IRQ_STATUS 0x2a0
  90. #define HOST_IRQ_STATUS_SM_NOT_IDLE (1 << 0)
  91. #define HOST_IRQ_STATUS_TX_PKT_DONE (1 << 1)
  92. #define HOST_IRQ_STATUS_DPHY_DIRECTION (1 << 2)
  93. #define HOST_IRQ_STATUS_TX_FIFO_OVFLW (1 << 3)
  94. #define HOST_IRQ_STATUS_TX_FIFO_UDFLW (1 << 4)
  95. #define HOST_IRQ_STATUS_RX_FIFO_OVFLW (1 << 5)
  96. #define HOST_IRQ_STATUS_RX_FIFO_UDFLW (1 << 6)
  97. #define HOST_IRQ_STATUS_RX_PKT_HDR_RCVD (1 << 7)
  98. #define HOST_IRQ_STATUS_RX_PKT_PAYLOAD_DATA_RCVD (1 << 8)
  99. #define HOST_IRQ_STATUS_HOST_BTA_TIMEOUT (1 << 29)
  100. #define HOST_IRQ_STATUS_LP_RX_TIMEOUT (1 << 30)
  101. #define HOST_IRQ_STATUS_HS_TX_TIMEOUT (1 << 31)
  102. #define HOST_IRQ_STATUS2 0x2a4
  103. #define HOST_IRQ_STATUS2_SINGLE_BIT_ECC_ERR (1 << 0)
  104. #define HOST_IRQ_STATUS2_MULTI_BIT_ECC_ERR (1 << 1)
  105. #define HOST_IRQ_STATUS2_CRC_ERR (1 << 2)
  106. #define HOST_IRQ_MASK 0x2a8
  107. #define HOST_IRQ_MASK_SM_NOT_IDLE_MASK (1 << 0)
  108. #define HOST_IRQ_MASK_TX_PKT_DONE_MASK (1 << 1)
  109. #define HOST_IRQ_MASK_DPHY_DIRECTION_MASK (1 << 2)
  110. #define HOST_IRQ_MASK_TX_FIFO_OVFLW_MASK (1 << 3)
  111. #define HOST_IRQ_MASK_TX_FIFO_UDFLW_MASK (1 << 4)
  112. #define HOST_IRQ_MASK_RX_FIFO_OVFLW_MASK (1 << 5)
  113. #define HOST_IRQ_MASK_RX_FIFO_UDFLW_MASK (1 << 6)
  114. #define HOST_IRQ_MASK_RX_PKT_HDR_RCVD_MASK (1 << 7)
  115. #define HOST_IRQ_MASK_RX_PKT_PAYLOAD_DATA_RCVD_MASK (1 << 8)
  116. #define HOST_IRQ_MASK_HOST_BTA_TIMEOUT_MASK (1 << 29)
  117. #define HOST_IRQ_MASK_LP_RX_TIMEOUT_MASK (1 << 30)
  118. #define HOST_IRQ_MASK_HS_TX_TIMEOUT_MASK (1 << 31)
  119. #define HOST_IRQ_MASK2 0x2ac
  120. #define HOST_IRQ_MASK2_SINGLE_BIT_ECC_ERR_MASK (1 << 0)
  121. #define HOST_IRQ_MASK2_MULTI_BIT_ECC_ERR_MASK (1 << 1)
  122. #define HOST_IRQ_MASK2_CRC_ERR_MASK (1 << 2)
  123. /* ------------------------------------- end -------------------------------- */
  124. #endif