ppc4xx.h 7.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225
  1. /*----------------------------------------------------------------------------+
  2. | This source code is dual-licensed. You may use it under the terms of
  3. | the GNU General Public License version 2, or under the license below.
  4. |
  5. | This source code has been made available to you by IBM on an AS-IS
  6. | basis. Anyone receiving this source is licensed under IBM
  7. | copyrights to use it in any way he or she deems fit, including
  8. | copying it, modifying it, compiling it, and redistributing it either
  9. | with or without modifications. No license under IBM patents or
  10. | patent applications is to be implied by the copyright license.
  11. |
  12. | Any user of this software should understand that IBM cannot provide
  13. | technical support for this software and will not be responsible for
  14. | any consequences resulting from the use of this software.
  15. |
  16. | Any person who transfers this source code or any derivative work
  17. | must include the IBM copyright notice, this paragraph, and the
  18. | preceding two paragraphs in the transferred software.
  19. |
  20. | COPYRIGHT I B M CORPORATION 1999
  21. | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
  22. +----------------------------------------------------------------------------*/
  23. #ifndef __PPC4XX_H__
  24. #define __PPC4XX_H__
  25. /*
  26. * Configure which SDRAM/DDR/DDR2 controller is equipped
  27. */
  28. #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
  29. defined(CONFIG_AP1000) || defined(CONFIG_ML2)
  30. #define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
  31. #endif
  32. #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
  33. defined(CONFIG_440EP) || defined(CONFIG_440GR)
  34. #define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
  35. #endif
  36. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  37. #define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
  38. #endif
  39. #if defined(CONFIG_405EX) || \
  40. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  41. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  42. defined(CONFIG_460SX)
  43. #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
  44. #endif
  45. #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  46. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  47. defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
  48. defined(CONFIG_460EX) || defined(CONFIG_460GT)
  49. #define CONFIG_NAND_NDFC
  50. #endif
  51. /* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
  52. #if defined(CONFIG_405EX) || \
  53. defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
  54. defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
  55. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  56. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  57. defined(CONFIG_460SX)
  58. #define PLB_ARBITER_BASE 0x80
  59. #define PLB0_ACR (PLB_ARBITER_BASE + 0x01)
  60. #define PLB0_ACR_PPM_MASK 0xF0000000
  61. #define PLB0_ACR_PPM_FIXED 0x00000000
  62. #define PLB0_ACR_PPM_FAIR 0xD0000000
  63. #define PLB0_ACR_HBU_MASK 0x08000000
  64. #define PLB0_ACR_HBU_DISABLED 0x00000000
  65. #define PLB0_ACR_HBU_ENABLED 0x08000000
  66. #define PLB0_ACR_RDP_MASK 0x06000000
  67. #define PLB0_ACR_RDP_DISABLED 0x00000000
  68. #define PLB0_ACR_RDP_2DEEP 0x02000000
  69. #define PLB0_ACR_RDP_3DEEP 0x04000000
  70. #define PLB0_ACR_RDP_4DEEP 0x06000000
  71. #define PLB0_ACR_WRP_MASK 0x01000000
  72. #define PLB0_ACR_WRP_DISABLED 0x00000000
  73. #define PLB0_ACR_WRP_2DEEP 0x01000000
  74. #define PLB1_ACR (PLB_ARBITER_BASE + 0x09)
  75. #define PLB1_ACR_PPM_MASK 0xF0000000
  76. #define PLB1_ACR_PPM_FIXED 0x00000000
  77. #define PLB1_ACR_PPM_FAIR 0xD0000000
  78. #define PLB1_ACR_HBU_MASK 0x08000000
  79. #define PLB1_ACR_HBU_DISABLED 0x00000000
  80. #define PLB1_ACR_HBU_ENABLED 0x08000000
  81. #define PLB1_ACR_RDP_MASK 0x06000000
  82. #define PLB1_ACR_RDP_DISABLED 0x00000000
  83. #define PLB1_ACR_RDP_2DEEP 0x02000000
  84. #define PLB1_ACR_RDP_3DEEP 0x04000000
  85. #define PLB1_ACR_RDP_4DEEP 0x06000000
  86. #define PLB1_ACR_WRP_MASK 0x01000000
  87. #define PLB1_ACR_WRP_DISABLED 0x00000000
  88. #define PLB1_ACR_WRP_2DEEP 0x01000000
  89. #endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
  90. #if defined(CONFIG_440)
  91. #include <ppc440.h>
  92. #else
  93. #include <ppc405.h>
  94. #endif
  95. #include <asm/ppc4xx-sdram.h>
  96. #include <asm/ppc4xx-ebc.h>
  97. #if !defined(CONFIG_XILINX_440)
  98. #include <asm/ppc4xx-uic.h>
  99. #endif
  100. /*
  101. * Macro for generating register field mnemonics
  102. */
  103. #define PPC_REG_BITS 32
  104. #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
  105. /*
  106. * Elide casts when assembling register mnemonics
  107. */
  108. #ifndef __ASSEMBLY__
  109. #define static_cast(type, val) (type)(val)
  110. #else
  111. #define static_cast(type, val) (val)
  112. #endif
  113. /*
  114. * Common stuff for 4xx (405 and 440)
  115. */
  116. #define EXC_OFF_SYS_RESET 0x0100 /* System reset */
  117. #define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
  118. #define RESET_VECTOR 0xfffffffc
  119. #define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
  120. cache line aligned data. */
  121. #define CPR0_DCR_BASE 0x0C
  122. #define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0)
  123. #define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1)
  124. #define SDR_DCR_BASE 0x0E
  125. #define SDR0_CFGADDR (SDR_DCR_BASE + 0x0)
  126. #define SDR0_CFGDATA (SDR_DCR_BASE + 0x1)
  127. #define SDRAM_DCR_BASE 0x10
  128. #define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0)
  129. #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1)
  130. #define EBC_DCR_BASE 0x12
  131. #define EBC0_CFGADDR (EBC_DCR_BASE + 0x0)
  132. #define EBC0_CFGDATA (EBC_DCR_BASE + 0x1)
  133. /*
  134. * Macros for indirect DCR access
  135. */
  136. #define mtcpr(reg, d) \
  137. do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
  138. #define mfcpr(reg, d) \
  139. do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
  140. #define mtebc(reg, d) \
  141. do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
  142. #define mfebc(reg, d) \
  143. do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
  144. #define mtsdram(reg, d) \
  145. do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
  146. #define mfsdram(reg, d) \
  147. do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
  148. #define mtsdr(reg, d) \
  149. do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
  150. #define mfsdr(reg, d) \
  151. do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
  152. #ifndef __ASSEMBLY__
  153. typedef struct
  154. {
  155. unsigned long freqDDR;
  156. unsigned long freqEBC;
  157. unsigned long freqOPB;
  158. unsigned long freqPCI;
  159. unsigned long freqPLB;
  160. unsigned long freqTmrClk;
  161. unsigned long freqUART;
  162. unsigned long freqProcessor;
  163. unsigned long freqVCOHz;
  164. unsigned long freqVCOMhz; /* in MHz */
  165. unsigned long pciClkSync; /* PCI clock is synchronous */
  166. unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
  167. unsigned long pllExtBusDiv;
  168. unsigned long pllFbkDiv;
  169. unsigned long pllFwdDiv;
  170. unsigned long pllFwdDivA;
  171. unsigned long pllFwdDivB;
  172. unsigned long pllOpbDiv;
  173. unsigned long pllPciDiv;
  174. unsigned long pllPlbDiv;
  175. } PPC4xx_SYS_INFO;
  176. static inline u32 get_mcsr(void)
  177. {
  178. u32 val;
  179. asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
  180. return val;
  181. }
  182. static inline void set_mcsr(u32 val)
  183. {
  184. asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
  185. }
  186. int ppc4xx_pci_sync_clock_config(u32 async);
  187. #endif /* __ASSEMBLY__ */
  188. /* for multi-cpu support */
  189. #define NA_OR_UNKNOWN_CPU -1
  190. #endif /* __PPC4XX_H__ */