socrates.h 16 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
  4. *
  5. * Wolfgang Denk <wd@denx.de>
  6. * Copyright 2004 Freescale Semiconductor.
  7. * (C) Copyright 2002,2003 Motorola,Inc.
  8. * Xianghua Xiao <X.Xiao@motorola.com>
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. /*
  29. * Socrates
  30. */
  31. #ifndef __CONFIG_H
  32. #define __CONFIG_H
  33. /* new uImage format support */
  34. #define CONFIG_FIT 1
  35. #define CONFIG_OF_LIBFDT 1
  36. #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
  37. /* High Level Configuration Options */
  38. #define CONFIG_BOOKE 1 /* BOOKE */
  39. #define CONFIG_E500 1 /* BOOKE e500 family */
  40. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
  41. #define CONFIG_MPC8544 1
  42. #define CONFIG_SOCRATES 1
  43. #define CONFIG_PCI
  44. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  45. #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
  46. #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
  47. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  48. /*
  49. * Only possible on E500 Version 2 or newer cores.
  50. */
  51. #define CONFIG_ENABLE_36BIT_PHYS 1
  52. /*
  53. * sysclk for MPC85xx
  54. *
  55. * Two valid values are:
  56. * 33000000
  57. * 66000000
  58. *
  59. * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  60. * is likely the desired value here, so that is now the default.
  61. * The board, however, can run at 66MHz. In any event, this value
  62. * must match the settings of some switches. Details can be found
  63. * in the README.mpc85xxads.
  64. */
  65. #ifndef CONFIG_SYS_CLK_FREQ
  66. #define CONFIG_SYS_CLK_FREQ 66666666
  67. #endif
  68. /*
  69. * These can be toggled for performance analysis, otherwise use default.
  70. */
  71. #define CONFIG_L2_CACHE /* toggle L2 cache */
  72. #define CONFIG_BTB /* toggle branch predition */
  73. #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
  74. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  75. #define CONFIG_SYS_MEMTEST_START 0x00400000
  76. #define CONFIG_SYS_MEMTEST_END 0x00C00000
  77. /*
  78. * Base addresses -- Note these are effective addresses where the
  79. * actual resources get mapped (not physical addresses)
  80. */
  81. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
  82. #define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
  83. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
  84. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  85. /* DDR Setup */
  86. #define CONFIG_FSL_DDR2
  87. #undef CONFIG_FSL_DDR_INTERACTIVE
  88. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  89. #define CONFIG_DDR_SPD
  90. #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  91. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  92. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  93. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  94. #define CONFIG_VERY_BIG_RAM
  95. #define CONFIG_NUM_DDR_CONTROLLERS 1
  96. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  97. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  98. /* I2C addresses of SPD EEPROMs */
  99. #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
  100. #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
  101. /* Hardcoded values, to use instead of SPD */
  102. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
  103. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
  104. #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  105. #define CONFIG_SYS_DDR_TIMING_1 0x3935D322
  106. #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
  107. #define CONFIG_SYS_DDR_MODE 0x00480432
  108. #define CONFIG_SYS_DDR_INTERVAL 0x030C0100
  109. #define CONFIG_SYS_DDR_CONFIG_2 0x04400000
  110. #define CONFIG_SYS_DDR_CONFIG 0xC3008000
  111. #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
  112. #define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
  113. /*
  114. * Flash on the LocalBus
  115. */
  116. #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
  117. #define CONFIG_SYS_FLASH0 0xFE000000
  118. #define CONFIG_SYS_FLASH1 0xFC000000
  119. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
  120. #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
  121. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
  122. #define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
  123. #define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
  124. #define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
  125. #define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
  126. #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
  127. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
  128. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  129. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
  130. #undef CONFIG_SYS_FLASH_CHECKSUM
  131. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  132. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  133. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  134. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  135. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  136. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  137. #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
  138. #define CONFIG_SYS_INIT_RAM_LOCK 1
  139. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  140. #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */
  141. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data*/
  142. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  143. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  144. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */
  145. #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
  146. /* FPGA and NAND */
  147. #define CONFIG_SYS_FPGA_BASE 0xc0000000
  148. #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
  149. #define CONFIG_SYS_HMI_BASE 0xc0010000
  150. #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
  151. #define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
  152. #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
  153. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  154. #define CONFIG_CMD_NAND
  155. /* LIME GDC */
  156. #define CONFIG_SYS_LIME_BASE 0xc8000000
  157. #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
  158. #define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
  159. #define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
  160. #define CONFIG_VIDEO
  161. #define CONFIG_VIDEO_MB862xx
  162. #define CONFIG_VIDEO_MB862xx_ACCEL
  163. #define CONFIG_CFB_CONSOLE
  164. #define CONFIG_VIDEO_LOGO
  165. #define CONFIG_VIDEO_BMP_LOGO
  166. #define CONFIG_CONSOLE_EXTRA_INFO
  167. #define VIDEO_FB_16BPP_PIXEL_SWAP
  168. #define VIDEO_FB_16BPP_WORD_SWAP
  169. #define CONFIG_VGA_AS_SINGLE_DEVICE
  170. #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  171. #define CONFIG_VIDEO_SW_CURSOR
  172. #define CONFIG_SPLASH_SCREEN
  173. #define CONFIG_VIDEO_BMP_GZIP
  174. #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
  175. /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
  176. #define CONFIG_SYS_MB862xx_CCF 0x10000
  177. /* SDRAM parameter */
  178. #define CONFIG_SYS_MB862xx_MMR 0x4157BA63
  179. /* Serial Port */
  180. #define CONFIG_CONS_INDEX 1
  181. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  182. #define CONFIG_SYS_NS16550
  183. #define CONFIG_SYS_NS16550_SERIAL
  184. #define CONFIG_SYS_NS16550_REG_SIZE 1
  185. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  186. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  187. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  188. #define CONFIG_BAUDRATE 115200
  189. #define CONFIG_SYS_BAUDRATE_TABLE \
  190. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  191. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  192. #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
  193. #ifdef CONFIG_SYS_HUSH_PARSER
  194. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  195. #endif
  196. /*
  197. * I2C
  198. */
  199. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  200. #define CONFIG_HARD_I2C /* I2C with hardware support */
  201. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  202. #define CONFIG_SYS_I2C_SPEED 102124 /* I2C speed and slave address */
  203. #define CONFIG_SYS_I2C_SLAVE 0x7F
  204. #define CONFIG_SYS_I2C_OFFSET 0x3000
  205. #define CONFIG_I2C_MULTI_BUS
  206. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  207. /* I2C RTC */
  208. #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
  209. #define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */
  210. /* I2C W83782G HW-Monitoring IC */
  211. #define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */
  212. /* I2C temp sensor */
  213. /* Socrates uses Maxim's DS75, which is compatible with LM75 */
  214. #define CONFIG_DTT_LM75 1
  215. #define CONFIG_DTT_SENSORS {4} /* Sensor addresses */
  216. #define CONFIG_SYS_DTT_MAX_TEMP 125
  217. #define CONFIG_SYS_DTT_LOW_TEMP -55
  218. #define CONFIG_SYS_DTT_HYSTERESIS 3
  219. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
  220. /*
  221. * General PCI
  222. * Memory space is mapped 1-1.
  223. */
  224. #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
  225. /* PCI is clocked by the external source at 33 MHz */
  226. #define CONFIG_PCI_CLK_FREQ 33000000
  227. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  228. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  229. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  230. #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
  231. #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
  232. #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
  233. #if defined(CONFIG_PCI)
  234. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  235. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  236. #endif /* CONFIG_PCI */
  237. #define CONFIG_NET_MULTI 1
  238. #define CONFIG_MII 1 /* MII PHY management */
  239. #define CONFIG_TSEC1 1
  240. #define CONFIG_TSEC1_NAME "TSEC0"
  241. #define CONFIG_TSEC3 1
  242. #define CONFIG_TSEC3_NAME "TSEC1"
  243. #undef CONFIG_MPC85XX_FEC
  244. #define TSEC1_PHY_ADDR 0
  245. #define TSEC3_PHY_ADDR 1
  246. #define TSEC1_PHYIDX 0
  247. #define TSEC3_PHYIDX 0
  248. #define TSEC1_FLAGS TSEC_GIGABIT
  249. #define TSEC3_FLAGS TSEC_GIGABIT
  250. /* Options are: TSEC[0,1] */
  251. #define CONFIG_ETHPRIME "TSEC0"
  252. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  253. #define CONFIG_HAS_ETH0
  254. #define CONFIG_HAS_ETH1
  255. /*
  256. * Environment
  257. */
  258. #define CONFIG_ENV_IS_IN_FLASH 1
  259. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
  260. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  261. #define CONFIG_ENV_SIZE 0x4000
  262. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
  263. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  264. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  265. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  266. #define CONFIG_TIMESTAMP /* Print image info with ts */
  267. /*
  268. * BOOTP options
  269. */
  270. #define CONFIG_BOOTP_BOOTFILESIZE
  271. #define CONFIG_BOOTP_BOOTPATH
  272. #define CONFIG_BOOTP_GATEWAY
  273. #define CONFIG_BOOTP_HOSTNAME
  274. /*
  275. * Command line configuration.
  276. */
  277. #include <config_cmd_default.h>
  278. #define CONFIG_CMD_DATE
  279. #define CONFIG_CMD_DHCP
  280. #define CONFIG_CMD_DTT
  281. #undef CONFIG_CMD_EEPROM
  282. #define CONFIG_CMD_I2C
  283. #define CONFIG_CMD_SDRAM
  284. #define CONFIG_CMD_MII
  285. #define CONFIG_CMD_NFS
  286. #define CONFIG_CMD_PING
  287. #define CONFIG_CMD_SNTP
  288. #define CONFIG_CMD_USB
  289. #define CONFIG_CMD_EXT2 /* EXT2 Support */
  290. #define CONFIG_CMD_BMP
  291. #if defined(CONFIG_PCI)
  292. #define CONFIG_CMD_PCI
  293. #endif
  294. #undef CONFIG_WATCHDOG /* watchdog disabled */
  295. /*
  296. * Miscellaneous configurable options
  297. */
  298. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  299. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  300. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  301. #if defined(CONFIG_CMD_KGDB)
  302. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  303. #else
  304. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  305. #endif
  306. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */
  307. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  308. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  309. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  310. /*
  311. * For booting Linux, the board info and command line data
  312. * have to be in the first 8 MB of memory, since this is
  313. * the maximum mapped by the Linux kernel during initialization.
  314. */
  315. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  316. /*
  317. * Internal Definitions
  318. *
  319. * Boot Flags
  320. */
  321. #define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
  322. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  323. #if defined(CONFIG_CMD_KGDB)
  324. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
  325. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  326. #endif
  327. #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
  328. #define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */
  329. #define CONFIG_PREBOOT "echo;" \
  330. "echo Welcome on the ABB Socrates Board;" \
  331. "echo"
  332. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  333. #define CONFIG_EXTRA_ENV_SETTINGS \
  334. "netdev=eth0\0" \
  335. "consdev=ttyS0\0" \
  336. "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
  337. "bootfile=/home/tftp/syscon3/uImage\0" \
  338. "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
  339. "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
  340. "uboot_addr=FFFA0000\0" \
  341. "kernel_addr=FE000000\0" \
  342. "fdt_addr=FE1E0000\0" \
  343. "ramdisk_addr=FE200000\0" \
  344. "fdt_addr_r=B00000\0" \
  345. "kernel_addr_r=200000\0" \
  346. "ramdisk_addr_r=400000\0" \
  347. "rootpath=/opt/eldk/ppc_85xxDP\0" \
  348. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  349. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  350. "nfsroot=$serverip:$rootpath\0" \
  351. "addcons=setenv bootargs $bootargs " \
  352. "console=$consdev,$baudrate\0" \
  353. "addip=setenv bootargs $bootargs " \
  354. "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
  355. ":$hostname:$netdev:off panic=1\0" \
  356. "boot_nor=run ramargs addcons;" \
  357. "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
  358. "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
  359. "tftp ${fdt_addr_r} ${fdt_file}; " \
  360. "run nfsargs addip addcons;" \
  361. "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  362. "update_uboot=tftp 100000 ${uboot_file};" \
  363. "protect off fffa0000 ffffffff;" \
  364. "era fffa0000 ffffffff;" \
  365. "cp.b 100000 fffa0000 ${filesize};" \
  366. "setenv filesize;saveenv\0" \
  367. "update_kernel=tftp 100000 ${bootfile};" \
  368. "era fe000000 fe1dffff;" \
  369. "cp.b 100000 fe000000 ${filesize};" \
  370. "setenv filesize;saveenv\0" \
  371. "update_fdt=tftp 100000 ${fdt_file};" \
  372. "era fe1e0000 fe1fffff;" \
  373. "cp.b 100000 fe1e0000 ${filesize};" \
  374. "setenv filesize;saveenv\0" \
  375. "update_initrd=tftp 100000 ${initrd_file};" \
  376. "era fe200000 fe9fffff;" \
  377. "cp.b 100000 fe200000 ${filesize};" \
  378. "setenv filesize;saveenv\0" \
  379. "clean_data=era fea00000 fff5ffff\0" \
  380. "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
  381. "load_usb=usb start;" \
  382. "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
  383. "boot_usb=run load_usb usbargs addcons;" \
  384. "bootm ${kernel_addr_r} - ${fdt_addr};" \
  385. "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
  386. ""
  387. #define CONFIG_BOOTCOMMAND "run boot_nor"
  388. /* pass open firmware flat tree */
  389. #define CONFIG_OF_LIBFDT 1
  390. #define CONFIG_OF_BOARD_SETUP 1
  391. /* USB support */
  392. #define CONFIG_USB_OHCI_NEW 1
  393. #define CONFIG_PCI_OHCI 1
  394. #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
  395. #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
  396. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  397. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
  398. #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
  399. #define CONFIG_DOS_PARTITION 1
  400. #define CONFIG_USB_STORAGE 1
  401. #endif /* __CONFIG_H */