sbc8641d.h 22 KB

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  1. /*
  2. * Copyright 2007 Wind River Systems <www.windriver.com>
  3. * Copyright 2007 Embedded Specialties, Inc.
  4. * Joe Hamman <joe.hamman@embeddedspecialties.com>
  5. *
  6. * Copyright 2006 Freescale Semiconductor.
  7. *
  8. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. /*
  29. * SBC8641D board configuration file
  30. *
  31. * Make sure you change the MAC address and other network params first,
  32. * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  33. */
  34. #ifndef __CONFIG_H
  35. #define __CONFIG_H
  36. /* High Level Configuration Options */
  37. #define CONFIG_MPC86xx 1 /* MPC86xx */
  38. #define CONFIG_MPC8641 1 /* MPC8641 specific */
  39. #define CONFIG_SBC8641D 1 /* SBC8641D board specific */
  40. #define CONFIG_MP 1 /* support multiple processors */
  41. #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
  42. #ifdef RUN_DIAG
  43. #define CONFIG_SYS_DIAG_ADDR 0xff800000
  44. #endif
  45. #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
  46. /*
  47. * virtual address to be used for temporary mappings. There
  48. * should be 128k free at this VA.
  49. */
  50. #define CONFIG_SYS_SCRATCH_VA 0xe8000000
  51. #define CONFIG_PCI 1 /* Enable PCIE */
  52. #define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */
  53. #define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */
  54. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  55. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  56. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  57. #define CONFIG_ENV_OVERWRITE
  58. #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
  59. #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
  60. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  61. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  62. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  63. #define CONFIG_NUM_DDR_CONTROLLERS 2
  64. #define CACHE_LINE_INTERLEAVING 0x20000000
  65. #define PAGE_INTERLEAVING 0x21000000
  66. #define BANK_INTERLEAVING 0x22000000
  67. #define SUPER_BANK_INTERLEAVING 0x23000000
  68. #define CONFIG_ALTIVEC 1
  69. /*
  70. * L2CR setup -- make sure this is right for your board!
  71. */
  72. #define CONFIG_SYS_L2
  73. #define L2_INIT 0
  74. #define L2_ENABLE (L2CR_L2E)
  75. #ifndef CONFIG_SYS_CLK_FREQ
  76. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
  77. #endif
  78. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
  79. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  80. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
  81. #define CONFIG_SYS_MEMTEST_END 0x00400000
  82. /*
  83. * Base addresses -- Note these are effective addresses where the
  84. * actual resources get mapped (not physical addresses)
  85. */
  86. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  87. #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
  88. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  89. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  90. #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
  91. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
  92. #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
  93. #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
  94. /*
  95. * DDR Setup
  96. */
  97. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
  98. #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
  99. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  100. #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
  101. #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
  102. #define CONFIG_VERY_BIG_RAM
  103. #define CONFIG_NUM_DDR_CONTROLLERS 2
  104. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  105. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  106. #if defined(CONFIG_SPD_EEPROM)
  107. /*
  108. * Determine DDR configuration from I2C interface.
  109. */
  110. #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
  111. #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
  112. #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
  113. #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
  114. #else
  115. /*
  116. * Manually set up DDR1 & DDR2 parameters
  117. */
  118. #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
  119. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
  120. #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
  121. #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
  122. #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
  123. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
  124. #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
  125. #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
  126. #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
  127. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  128. #define CONFIG_SYS_DDR_TIMING_0 0x00220802
  129. #define CONFIG_SYS_DDR_TIMING_1 0x38377322
  130. #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
  131. #define CONFIG_SYS_DDR_CFG_1A 0x43008008
  132. #define CONFIG_SYS_DDR_CFG_2 0x24401000
  133. #define CONFIG_SYS_DDR_MODE_1 0x23c00542
  134. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  135. #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
  136. #define CONFIG_SYS_DDR_INTERVAL 0x05080100
  137. #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
  138. #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
  139. #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
  140. #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
  141. #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
  142. #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
  143. #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
  144. #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
  145. #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
  146. #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
  147. #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
  148. #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
  149. #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
  150. #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
  151. #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
  152. #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
  153. #define CONFIG_SYS_DDR2_CFG_2 0x24401000
  154. #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
  155. #define CONFIG_SYS_DDR2_MODE_2 0x00000000
  156. #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
  157. #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
  158. #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
  159. #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
  160. #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
  161. #endif
  162. /* #define CONFIG_ID_EEPROM 1
  163. #define ID_EEPROM_ADDR 0x57 */
  164. /*
  165. * The SBC8641D contains 16MB flash space at ff000000.
  166. */
  167. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
  168. /* Flash */
  169. #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
  170. #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
  171. /* 64KB EEPROM */
  172. #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */
  173. #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
  174. /* EPLD - User switches, board id, LEDs */
  175. #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */
  176. #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
  177. /* Local bus SDRAM 128MB */
  178. #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */
  179. #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
  180. #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */
  181. #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
  182. /* Disk on Chip (DOC) 128MB */
  183. #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */
  184. #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
  185. /* LCD */
  186. #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */
  187. #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
  188. /* Control logic & misc peripherals */
  189. #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */
  190. #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
  191. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  192. #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */
  193. #undef CONFIG_SYS_FLASH_CHECKSUM
  194. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  195. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  196. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  197. #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
  198. #define CONFIG_FLASH_CFI_DRIVER
  199. #define CONFIG_SYS_FLASH_CFI
  200. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  201. #define CONFIG_SYS_FLASH_EMPTY_INFO
  202. #define CONFIG_SYS_FLASH_PROTECTION
  203. #undef CONFIG_CLOCKS_IN_MHZ
  204. #define CONFIG_SYS_INIT_RAM_LOCK 1
  205. #ifndef CONFIG_SYS_INIT_RAM_LOCK
  206. #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
  207. #else
  208. #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
  209. #endif
  210. #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
  211. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  212. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  213. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  214. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  215. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  216. /* Serial Port */
  217. #define CONFIG_CONS_INDEX 1
  218. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  219. #define CONFIG_SYS_NS16550
  220. #define CONFIG_SYS_NS16550_SERIAL
  221. #define CONFIG_SYS_NS16550_REG_SIZE 1
  222. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  223. #define CONFIG_SYS_BAUDRATE_TABLE \
  224. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  225. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  226. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  227. /* Use the HUSH parser */
  228. #define CONFIG_SYS_HUSH_PARSER
  229. #ifdef CONFIG_SYS_HUSH_PARSER
  230. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  231. #endif
  232. /*
  233. * Pass open firmware flat tree to kernel
  234. */
  235. #define CONFIG_OF_LIBFDT 1
  236. #define CONFIG_OF_BOARD_SETUP 1
  237. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  238. /*
  239. * I2C
  240. */
  241. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  242. #define CONFIG_HARD_I2C /* I2C with hardware support*/
  243. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  244. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  245. #define CONFIG_SYS_I2C_SLAVE 0x7F
  246. #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  247. #define CONFIG_SYS_I2C_OFFSET 0x3100
  248. /*
  249. * RapidIO MMU
  250. */
  251. #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
  252. #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
  253. #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
  254. /*
  255. * General PCI
  256. * Addresses are mapped 1-1.
  257. */
  258. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  259. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
  260. #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
  261. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  262. #define CONFIG_SYS_PCI1_IO_BUS 0xe2000000
  263. #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS
  264. #define CONFIG_SYS_PCI1_IO_VIRT CONFIG_SYS_PCI1_IO_BUS
  265. #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
  266. #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
  267. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS
  268. #define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BUS
  269. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  270. #define CONFIG_SYS_PCI2_IO_BUS 0xe3000000
  271. #define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BUS
  272. #define CONFIG_SYS_PCI2_IO_VIRT CONFIG_SYS_PCI2_IO_BUS
  273. #define CONFIG_SYS_PCI2_IO_SIZE 0x1000000 /* 16M */
  274. #if defined(CONFIG_PCI)
  275. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  276. #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
  277. #define CONFIG_NET_MULTI
  278. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  279. #undef CONFIG_EEPRO100
  280. #undef CONFIG_TULIP
  281. #if !defined(CONFIG_PCI_PNP)
  282. #define PCI_ENET0_IOADDR 0xe0000000
  283. #define PCI_ENET0_MEMADDR 0xe0000000
  284. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  285. #endif
  286. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  287. #define CONFIG_DOS_PARTITION
  288. #undef CONFIG_SCSI_AHCI
  289. #ifdef CONFIG_SCSI_AHCI
  290. #define CONFIG_SATA_ULI5288
  291. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
  292. #define CONFIG_SYS_SCSI_MAX_LUN 1
  293. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
  294. #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
  295. #endif
  296. #endif /* CONFIG_PCI */
  297. #if defined(CONFIG_TSEC_ENET)
  298. #ifndef CONFIG_NET_MULTI
  299. #define CONFIG_NET_MULTI 1
  300. #endif
  301. /* #define CONFIG_MII 1 */ /* MII PHY management */
  302. #define CONFIG_TSEC1 1
  303. #define CONFIG_TSEC1_NAME "eTSEC1"
  304. #define CONFIG_TSEC2 1
  305. #define CONFIG_TSEC2_NAME "eTSEC2"
  306. #define CONFIG_TSEC3 1
  307. #define CONFIG_TSEC3_NAME "eTSEC3"
  308. #define CONFIG_TSEC4 1
  309. #define CONFIG_TSEC4_NAME "eTSEC4"
  310. #define TSEC1_PHY_ADDR 0x1F
  311. #define TSEC2_PHY_ADDR 0x00
  312. #define TSEC3_PHY_ADDR 0x01
  313. #define TSEC4_PHY_ADDR 0x02
  314. #define TSEC1_PHYIDX 0
  315. #define TSEC2_PHYIDX 0
  316. #define TSEC3_PHYIDX 0
  317. #define TSEC4_PHYIDX 0
  318. #define TSEC1_FLAGS TSEC_GIGABIT
  319. #define TSEC2_FLAGS TSEC_GIGABIT
  320. #define TSEC3_FLAGS TSEC_GIGABIT
  321. #define TSEC4_FLAGS TSEC_GIGABIT
  322. #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
  323. #define CONFIG_ETHPRIME "eTSEC1"
  324. #endif /* CONFIG_TSEC_ENET */
  325. /*
  326. * BAT0 2G Cacheable, non-guarded
  327. * 0x0000_0000 2G DDR
  328. */
  329. #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  330. #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
  331. #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
  332. #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
  333. /*
  334. * BAT1 1G Cache-inhibited, guarded
  335. * 0x8000_0000 512M PCI-Express 1 Memory
  336. * 0xa000_0000 512M PCI-Express 2 Memory
  337. * Changed it for operating from 0xd0000000
  338. */
  339. #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
  340. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  341. #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
  342. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
  343. #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
  344. /*
  345. * BAT2 512M Cache-inhibited, guarded
  346. * 0xc000_0000 512M RapidIO Memory
  347. */
  348. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \
  349. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  350. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
  351. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
  352. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  353. /*
  354. * BAT3 4M Cache-inhibited, guarded
  355. * 0xf800_0000 4M CCSR
  356. */
  357. #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
  358. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  359. #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
  360. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
  361. #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
  362. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
  363. #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
  364. | BATL_PP_RW | BATL_CACHEINHIBIT \
  365. | BATL_GUARDEDSTORAGE)
  366. #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
  367. | BATU_BL_1M | BATU_VS | BATU_VP)
  368. #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
  369. | BATL_PP_RW | BATL_CACHEINHIBIT)
  370. #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
  371. #endif
  372. /*
  373. * BAT4 32M Cache-inhibited, guarded
  374. * 0xe200_0000 16M PCI-Express 1 I/O
  375. * 0xe300_0000 16M PCI-Express 2 I/0
  376. * Note that this is at 0xe0000000
  377. */
  378. #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
  379. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  380. #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
  381. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
  382. #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
  383. /*
  384. * BAT5 128K Cacheable, non-guarded
  385. * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
  386. */
  387. #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
  388. #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  389. #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
  390. #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
  391. /*
  392. * BAT6 32M Cache-inhibited, guarded
  393. * 0xfe00_0000 32M FLASH
  394. */
  395. #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
  396. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  397. #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
  398. #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
  399. #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
  400. /* Map the last 1M of flash where we're running from reset */
  401. #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
  402. | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  403. #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
  404. #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
  405. | BATL_MEMCOHERENCE)
  406. #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
  407. #define CONFIG_SYS_DBAT7L 0x00000000
  408. #define CONFIG_SYS_DBAT7U 0x00000000
  409. #define CONFIG_SYS_IBAT7L 0x00000000
  410. #define CONFIG_SYS_IBAT7U 0x00000000
  411. /*
  412. * Environment
  413. */
  414. #define CONFIG_ENV_IS_IN_FLASH 1
  415. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
  416. #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
  417. #define CONFIG_ENV_SIZE 0x2000
  418. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  419. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  420. #include <config_cmd_default.h>
  421. #define CONFIG_CMD_PING
  422. #define CONFIG_CMD_I2C
  423. #define CONFIG_CMD_REGINFO
  424. #if defined(CONFIG_PCI)
  425. #define CONFIG_CMD_PCI
  426. #endif
  427. #undef CONFIG_WATCHDOG /* watchdog disabled */
  428. /*
  429. * Miscellaneous configurable options
  430. */
  431. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  432. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  433. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  434. #if defined(CONFIG_CMD_KGDB)
  435. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  436. #else
  437. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  438. #endif
  439. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  440. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  441. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  442. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  443. /*
  444. * For booting Linux, the board info and command line data
  445. * have to be in the first 8 MB of memory, since this is
  446. * the maximum mapped by the Linux kernel during initialization.
  447. */
  448. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  449. /* Cache Configuration */
  450. #define CONFIG_SYS_DCACHE_SIZE 32768
  451. #define CONFIG_SYS_CACHELINE_SIZE 32
  452. #if defined(CONFIG_CMD_KGDB)
  453. #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
  454. #endif
  455. /*
  456. * Internal Definitions
  457. *
  458. * Boot Flags
  459. */
  460. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  461. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  462. #if defined(CONFIG_CMD_KGDB)
  463. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  464. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  465. #endif
  466. /*
  467. * Environment Configuration
  468. */
  469. /* The mac addresses for all ethernet interface */
  470. #if defined(CONFIG_TSEC_ENET)
  471. #define CONFIG_ETHADDR 02:E0:0C:00:00:01
  472. #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
  473. #define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
  474. #define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
  475. #endif
  476. #define CONFIG_HAS_ETH0 1
  477. #define CONFIG_HAS_ETH1 1
  478. #define CONFIG_HAS_ETH2 1
  479. #define CONFIG_HAS_ETH3 1
  480. #define CONFIG_IPADDR 192.168.0.50
  481. #define CONFIG_HOSTNAME sbc8641d
  482. #define CONFIG_ROOTPATH /opt/eldk/ppc_74xx
  483. #define CONFIG_BOOTFILE uImage
  484. #define CONFIG_SERVERIP 192.168.0.2
  485. #define CONFIG_GATEWAYIP 192.168.0.1
  486. #define CONFIG_NETMASK 255.255.255.0
  487. /* default location for tftp and bootm */
  488. #define CONFIG_LOADADDR 1000000
  489. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  490. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  491. #define CONFIG_BAUDRATE 115200
  492. #define CONFIG_EXTRA_ENV_SETTINGS \
  493. "netdev=eth0\0" \
  494. "consoledev=ttyS0\0" \
  495. "ramdiskaddr=2000000\0" \
  496. "ramdiskfile=uRamdisk\0" \
  497. "dtbaddr=400000\0" \
  498. "dtbfile=sbc8641d.dtb\0" \
  499. "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
  500. "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
  501. "maxcpus=1"
  502. #define CONFIG_NFSBOOTCOMMAND \
  503. "setenv bootargs root=/dev/nfs rw " \
  504. "nfsroot=$serverip:$rootpath " \
  505. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  506. "console=$consoledev,$baudrate $othbootargs;" \
  507. "tftp $loadaddr $bootfile;" \
  508. "tftp $dtbaddr $dtbfile;" \
  509. "bootm $loadaddr - $dtbaddr"
  510. #define CONFIG_RAMBOOTCOMMAND \
  511. "setenv bootargs root=/dev/ram rw " \
  512. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  513. "console=$consoledev,$baudrate $othbootargs;" \
  514. "tftp $ramdiskaddr $ramdiskfile;" \
  515. "tftp $loadaddr $bootfile;" \
  516. "tftp $dtbaddr $dtbfile;" \
  517. "bootm $loadaddr $ramdiskaddr $dtbaddr"
  518. #define CONFIG_FLASHBOOTCOMMAND \
  519. "setenv bootargs root=/dev/ram rw " \
  520. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  521. "console=$consoledev,$baudrate $othbootargs;" \
  522. "bootm ffd00000 ffb00000 ffa00000"
  523. #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
  524. #endif /* __CONFIG_H */