quad100hd.h 12 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /************************************************************************
  24. * quad100hd.h - configuration for Quad100hd board
  25. ***********************************************************************/
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*-----------------------------------------------------------------------
  29. * High Level Configuration Options
  30. *----------------------------------------------------------------------*/
  31. #define CONFIG_QUAD100HD 1 /* Board is Quad100hd */
  32. #define CONFIG_4xx 1 /* ... PPC4xx family */
  33. #define CONFIG_405EP 1 /* Specifc 405EP support*/
  34. #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
  35. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  36. #define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */
  37. #define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */
  38. /* the environment is in the EEPROM by default */
  39. #define CONFIG_ENV_IS_IN_EEPROM
  40. #undef CONFIG_ENV_IS_IN_FLASH
  41. #define CONFIG_PPC4xx_EMAC
  42. #define CONFIG_NET_MULTI 1
  43. #define CONFIG_HAS_ETH1 1
  44. #define CONFIG_MII 1 /* MII PHY management */
  45. #define CONFIG_PHY_ADDR 0x01 /* PHY address */
  46. #define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
  47. #define CONFIG_PHY_RESET 1
  48. #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
  49. /*
  50. * Command line configuration.
  51. */
  52. #include <config_cmd_default.h>
  53. #undef CONFIG_CMD_ASKENV
  54. #undef CONFIG_CMD_CACHE
  55. #define CONFIG_CMD_DHCP
  56. #undef CONFIG_CMD_DIAG
  57. #define CONFIG_CMD_EEPROM
  58. #undef CONFIG_CMD_ELF
  59. #define CONFIG_CMD_I2C
  60. #undef CONFIG_CMD_IRQ
  61. #define CONFIG_CMD_JFFS2
  62. #undef CONFIG_CMD_LOG
  63. #undef CONFIG_CMD_MII
  64. #define CONFIG_CMD_NAND
  65. #undef CONFIG_CMD_PING
  66. #define CONFIG_CMD_REGINFO
  67. #undef CONFIG_WATCHDOG /* watchdog disabled */
  68. /*-----------------------------------------------------------------------
  69. * SDRAM
  70. *----------------------------------------------------------------------*/
  71. /*
  72. * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  73. */
  74. #define CONFIG_SDRAM_BANK0 1
  75. /* FIX! SDRAM timings used in datasheet */
  76. #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
  77. #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
  78. #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
  79. #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
  80. #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
  81. /*
  82. * JFFS2
  83. */
  84. #define CONFIG_SYS_JFFS2_FIRST_BANK 0
  85. #ifdef CONFIG_SYS_KERNEL_IN_JFFS2
  86. #define CONFIG_SYS_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */
  87. #else /* kernel not in JFFS */
  88. #define CONFIG_SYS_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */
  89. #endif
  90. #define CONFIG_SYS_JFFS2_NUM_BANKS 1
  91. /*-----------------------------------------------------------------------
  92. * Serial Port
  93. *----------------------------------------------------------------------*/
  94. #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
  95. #define CONFIG_SYS_BASE_BAUD 691200
  96. #define CONFIG_BAUDRATE 115200
  97. #define CONFIG_SERIAL_MULTI
  98. /* The following table includes the supported baudrates */
  99. #define CONFIG_SYS_BAUDRATE_TABLE \
  100. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
  101. /*-----------------------------------------------------------------------
  102. * Miscellaneous configurable options
  103. *----------------------------------------------------------------------*/
  104. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  105. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  106. #if defined(CONFIG_CMD_KGDB)
  107. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  108. #else
  109. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  110. #endif
  111. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  112. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  113. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  114. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  115. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  116. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  117. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
  118. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  119. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  120. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  121. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  122. #define CONFIG_LOOPW 1 /* enable loopw command */
  123. #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
  124. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  125. #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  126. /*-----------------------------------------------------------------------
  127. * I2C
  128. *----------------------------------------------------------------------*/
  129. #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  130. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  131. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  132. #define CONFIG_SYS_I2C_SLAVE 0x7F
  133. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
  134. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */
  135. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */
  136. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  137. #define CONFIG_SYS_EEPROM_SIZE 0x2000
  138. /*-----------------------------------------------------------------------
  139. * Start addresses for the final memory configuration
  140. * (Set up by the startup code)
  141. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  142. */
  143. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  144. #define CONFIG_SYS_FLASH_BASE 0xFFC00000
  145. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
  146. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  147. #define CONFIG_SYS_MONITOR_BASE (TEXT_BASE)
  148. /*
  149. * For booting Linux, the board info and command line data
  150. * have to be in the first 8 MB of memory, since this is
  151. * the maximum mapped by the Linux kernel during initialization.
  152. */
  153. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  154. /*-----------------------------------------------------------------------
  155. * FLASH organization
  156. */
  157. #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  158. #define CONFIG_FLASH_CFI_DRIVER
  159. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  160. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  161. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
  162. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  163. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  164. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
  165. #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
  166. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  167. #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
  168. #ifdef CONFIG_ENV_IS_IN_FLASH
  169. #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
  170. /* the environment is located before u-boot */
  171. #define CONFIG_ENV_ADDR (TEXT_BASE - CONFIG_ENV_SECT_SIZE)
  172. /* Address and size of Redundant Environment Sector */
  173. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
  174. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
  175. #endif
  176. #ifdef CONFIG_ENV_IS_IN_EEPROM
  177. #define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars */
  178. #define CONFIG_ENV_OFFSET 0x00000000
  179. #define CONFIG_SYS_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */
  180. #endif
  181. /* partly from PPCBoot */
  182. /* NAND */
  183. #define CONFIG_NAND
  184. #ifdef CONFIG_NAND
  185. #define CONFIG_SYS_NAND_BASE 0x60000000
  186. #define CONFIG_SYS_NAND_CS 10 /* our CS is GPIO10 */
  187. #define CONFIG_SYS_NAND_RDY 23 /* our RDY is GPIO23 */
  188. #define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */
  189. #define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */
  190. #define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */
  191. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  192. #endif
  193. /*-----------------------------------------------------------------------
  194. * Definitions for initial stack pointer and data area (in data cache)
  195. */
  196. /* use on chip memory (OCM) for temperary stack until sdram is tested */
  197. /* see ./cpu/ppc4xx/start.S */
  198. #define CONFIG_SYS_TEMP_STACK_OCM 1
  199. /* On Chip Memory location */
  200. #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
  201. #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
  202. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
  203. #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
  204. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  205. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  206. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  207. /*-----------------------------------------------------------------------
  208. * External Bus Controller (EBC) Setup
  209. * Taken from PPCBoot board/icecube/icecube.h
  210. */
  211. /* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
  212. #define CONFIG_SYS_EBC_PB0AP 0x04002480
  213. /* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
  214. #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
  215. #define CONFIG_SYS_EBC_PB1AP 0x04005480
  216. #define CONFIG_SYS_EBC_PB1CR 0x60018000
  217. #define CONFIG_SYS_EBC_PB2AP 0x00000000
  218. #define CONFIG_SYS_EBC_PB2CR 0x00000000
  219. #define CONFIG_SYS_EBC_PB3AP 0x00000000
  220. #define CONFIG_SYS_EBC_PB3CR 0x00000000
  221. #define CONFIG_SYS_EBC_PB4AP 0x00000000
  222. #define CONFIG_SYS_EBC_PB4CR 0x00000000
  223. /*-----------------------------------------------------------------------
  224. * Definitions for GPIO setup (PPC405EP specific)
  225. *
  226. * Taken in part from PPCBoot board/icecube/icecube.h
  227. */
  228. /* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
  229. #define CONFIG_SYS_GPIO0_OSRH 0x55555550
  230. #define CONFIG_SYS_GPIO0_OSRL 0x00000110
  231. #define CONFIG_SYS_GPIO0_ISR1H 0x00000000
  232. #define CONFIG_SYS_GPIO0_ISR1L 0x15555445
  233. #define CONFIG_SYS_GPIO0_TSRH 0x00000000
  234. #define CONFIG_SYS_GPIO0_TSRL 0x00000000
  235. #define CONFIG_SYS_GPIO0_TCR 0xFFFF8097
  236. #define CONFIG_SYS_GPIO0_ODR 0x00000000
  237. #if defined(CONFIG_CMD_KGDB)
  238. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  239. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  240. #endif
  241. /* ENVIRONMENT VARS */
  242. #define CONFIG_IPADDR 192.168.1.67
  243. #define CONFIG_SERVERIP 192.168.1.50
  244. #define CONFIG_GATEWAYIP 192.168.1.1
  245. #define CONFIG_NETMASK 255.255.255.0
  246. #define CONFIG_LOADADDR 300000
  247. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  248. /* pass open firmware flat tree */
  249. #define CONFIG_OF_LIBFDT 1
  250. #endif /* __CONFIG_H */