pm9263.h 13 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stelian Pop <stelian.pop@leadtechdesign.com>
  4. * Lead Tech Design <www.leadtechdesign.com>
  5. * Ilko Iliev <www.ronetix.at>
  6. *
  7. * Configuation settings for the RONETIX PM9263 board.
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #ifndef __CONFIG_H
  28. #define __CONFIG_H
  29. /* ARM asynchronous clock */
  30. #define CONFIG_DISPLAY_CPUINFO
  31. #define CONFIG_DISPLAY_BOARDINFO
  32. #define MASTER_PLL_DIV 6
  33. #define MASTER_PLL_MUL 65
  34. #define MAIN_PLL_DIV 2 /* 2 or 4 */
  35. #define AT91_MAIN_CLOCK 18432000
  36. #define CONFIG_SYS_HZ 1000
  37. #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
  38. #define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
  39. #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
  40. #define CONFIG_ARCH_CPU_INIT
  41. #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
  42. /* clocks */
  43. #define CONFIG_SYS_MOR_VAL \
  44. (AT91_PMC_MOSCEN | \
  45. (255 << 8)) /* Main Oscillator Start-up Time */
  46. #define CONFIG_SYS_PLLAR_VAL \
  47. (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
  48. AT91_PMC_OUT | \
  49. AT91_PMC_PLLCOUNT | /* PLL Counter */ \
  50. (2 << 28) | /* PLL Clock Frequency Range */ \
  51. ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  52. #if (MAIN_PLL_DIV == 2)
  53. /* PCK/2 = MCK Master Clock from PLLA */
  54. #define CONFIG_SYS_MCKR1_VAL \
  55. (AT91_PMC_CSS_SLOW | \
  56. AT91_PMC_PRES_1 | \
  57. AT91SAM9_PMC_MDIV_2 | \
  58. AT91_PMC_PDIV_1)
  59. /* PCK/2 = MCK Master Clock from PLLA */
  60. #define CONFIG_SYS_MCKR2_VAL \
  61. (AT91_PMC_CSS_PLLA | \
  62. AT91_PMC_PRES_1 | \
  63. AT91SAM9_PMC_MDIV_2 | \
  64. AT91_PMC_PDIV_1)
  65. #else
  66. /* PCK/4 = MCK Master Clock from PLLA */
  67. #define CONFIG_SYS_MCKR1_VAL \
  68. (AT91_PMC_CSS_SLOW | \
  69. AT91_PMC_PRES_1 | \
  70. AT91RM9200_PMC_MDIV_3 | \
  71. AT91_PMC_PDIV_1)
  72. /* PCK/4 = MCK Master Clock from PLLA */
  73. #define CONFIG_SYS_MCKR2_VAL \
  74. (AT91_PMC_CSS_PLLA | \
  75. AT91_PMC_PRES_1 | \
  76. AT91RM9200_PMC_MDIV_3 | \
  77. AT91_PMC_PDIV_1)
  78. #endif
  79. /* define PDC[31:16] as DATA[31:16] */
  80. #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
  81. /* no pull-up for D[31:16] */
  82. #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
  83. /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
  84. #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
  85. (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
  86. AT91_MATRIX_EBI0_CS1A_SDRAMC)
  87. /* SDRAM */
  88. /* SDRAMC_MR Mode register */
  89. #define CONFIG_SYS_SDRC_MR_VAL1 0
  90. /* SDRAMC_TR - Refresh Timer register */
  91. #define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
  92. /* SDRAMC_CR - Configuration register*/
  93. #define CONFIG_SYS_SDRC_CR_VAL \
  94. (AT91_SDRAMC_NC_9 | \
  95. AT91_SDRAMC_NR_13 | \
  96. AT91_SDRAMC_NB_4 | \
  97. AT91_SDRAMC_CAS_2 | \
  98. AT91_SDRAMC_DBW_32 | \
  99. (2 << 8) | /* tWR - Write Recovery Delay */ \
  100. (7 << 12) | /* tRC - Row Cycle Delay */ \
  101. (2 << 16) | /* tRP - Row Precharge Delay */ \
  102. (2 << 20) | /* tRCD - Row to Column Delay */ \
  103. (5 << 24) | /* tRAS - Active to Precharge Delay */ \
  104. (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
  105. /* Memory Device Register -> SDRAM */
  106. #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
  107. #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
  108. #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
  109. #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
  110. #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
  111. #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
  112. #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
  113. #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
  114. #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
  115. #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
  116. #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
  117. #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
  118. #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
  119. #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
  120. #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
  121. #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
  122. #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
  123. #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
  124. /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
  125. #define CONFIG_SYS_SMC0_SETUP0_VAL \
  126. (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
  127. AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
  128. #define CONFIG_SYS_SMC0_PULSE0_VAL \
  129. (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
  130. AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
  131. #define CONFIG_SYS_SMC0_CYCLE0_VAL \
  132. (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
  133. #define CONFIG_SYS_SMC0_MODE0_VAL \
  134. (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
  135. AT91_SMC_DBW_16 | \
  136. AT91_SMC_TDFMODE | \
  137. AT91_SMC_TDF_(6))
  138. /* user reset enable */
  139. #define CONFIG_SYS_RSTC_RMR_VAL \
  140. (AT91_RSTC_KEY | \
  141. AT91_RSTC_PROCRST | \
  142. AT91_RSTC_RSTTYP_WAKEUP | \
  143. AT91_RSTC_RSTTYP_WATCHDOG)
  144. /* Disable Watchdog */
  145. #define CONFIG_SYS_WDTC_WDMR_VAL \
  146. (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
  147. AT91_WDT_WDV | \
  148. AT91_WDT_WDDIS | \
  149. AT91_WDT_WDD)
  150. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  151. #define CONFIG_SETUP_MEMORY_TAGS 1
  152. #define CONFIG_INITRD_TAG 1
  153. #undef CONFIG_SKIP_LOWLEVEL_INIT
  154. #undef CONFIG_SKIP_RELOCATE_UBOOT
  155. #define CONFIG_USER_LOWLEVEL_INIT 1
  156. /*
  157. * Hardware drivers
  158. */
  159. #define CONFIG_ATMEL_USART 1
  160. #undef CONFIG_USART0
  161. #undef CONFIG_USART1
  162. #undef CONFIG_USART2
  163. #define CONFIG_USART3 1 /* USART 3 is DBGU */
  164. /* LCD */
  165. #define CONFIG_LCD 1
  166. #define LCD_BPP LCD_COLOR8
  167. #define CONFIG_LCD_LOGO 1
  168. #undef LCD_TEST_PATTERN
  169. #define CONFIG_LCD_INFO 1
  170. #define CONFIG_LCD_INFO_BELOW_LOGO 1
  171. #define CONFIG_SYS_WHITE_ON_BLACK 1
  172. #define CONFIG_ATMEL_LCD 1
  173. #define CONFIG_ATMEL_LCD_BGR555 1
  174. #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
  175. #define CONFIG_LCD_IN_PSRAM 1
  176. /* LED */
  177. #define CONFIG_AT91_LED
  178. #define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */
  179. #define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
  180. #define CONFIG_BOOTDELAY 3
  181. /*
  182. * BOOTP options
  183. */
  184. #define CONFIG_BOOTP_BOOTFILESIZE 1
  185. #define CONFIG_BOOTP_BOOTPATH 1
  186. #define CONFIG_BOOTP_GATEWAY 1
  187. #define CONFIG_BOOTP_HOSTNAME 1
  188. /*
  189. * Command line configuration.
  190. */
  191. #include <config_cmd_default.h>
  192. #undef CONFIG_CMD_BDI
  193. #undef CONFIG_CMD_IMI
  194. #undef CONFIG_CMD_AUTOSCRIPT
  195. #undef CONFIG_CMD_FPGA
  196. #undef CONFIG_CMD_LOADS
  197. #undef CONFIG_CMD_IMLS
  198. #define CONFIG_CMD_PING 1
  199. #define CONFIG_CMD_DHCP 1
  200. #define CONFIG_CMD_NAND 1
  201. #define CONFIG_CMD_USB 1
  202. /* SDRAM */
  203. #define CONFIG_NR_DRAM_BANKS 1
  204. #define PHYS_SDRAM 0x20000000
  205. #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
  206. /* DataFlash */
  207. #define CONFIG_ATMEL_DATAFLASH_SPI
  208. #define CONFIG_HAS_DATAFLASH 1
  209. #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
  210. #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
  211. #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
  212. #define AT91_SPI_CLK 15000000
  213. #define DATAFLASH_TCSS (0x1a << 16)
  214. #define DATAFLASH_TCHS (0x1 << 24)
  215. /* NOR flash, if populated */
  216. #define CONFIG_SYS_FLASH_CFI 1
  217. #define CONFIG_FLASH_CFI_DRIVER 1
  218. #define PHYS_FLASH_1 0x10000000
  219. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  220. #define CONFIG_SYS_MAX_FLASH_SECT 256
  221. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  222. /* NAND flash */
  223. #ifdef CONFIG_CMD_NAND
  224. #define CONFIG_NAND_ATMEL
  225. #define CONFIG_SYS_NAND_MAX_CHIPS 1
  226. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  227. #define CONFIG_SYS_NAND_BASE 0x40000000
  228. #define CONFIG_SYS_NAND_DBW_8 1
  229. /* our ALE is AD21 */
  230. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  231. /* our CLE is AD22 */
  232. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  233. #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
  234. #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30
  235. #endif
  236. #define CONFIG_CMD_JFFS2 1
  237. #define CONFIG_JFFS2_CMDLINE 1
  238. #define CONFIG_JFFS2_NAND 1
  239. #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
  240. #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
  241. #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
  242. /* PSRAM */
  243. #define PHYS_PSRAM 0x70000000
  244. #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
  245. /* Ethernet */
  246. #define CONFIG_MACB 1
  247. #define CONFIG_RMII 1
  248. #define CONFIG_NET_MULTI 1
  249. #define CONFIG_NET_RETRY_COUNT 20
  250. #define CONFIG_RESET_PHY_R 1
  251. /* USB */
  252. #define CONFIG_USB_ATMEL
  253. #define CONFIG_USB_OHCI_NEW 1
  254. #define CONFIG_DOS_PARTITION 1
  255. #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
  256. #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
  257. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
  258. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  259. #define CONFIG_USB_STORAGE 1
  260. #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  261. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  262. #define CONFIG_SYS_MEMTEST_END 0x23e00000
  263. #define CONFIG_SYS_USE_FLASH 1
  264. #undef CONFIG_SYS_USE_DATAFLASH
  265. #undef CONFIG_SYS_USE_NANDFLASH
  266. #ifdef CONFIG_SYS_USE_DATAFLASH
  267. /* bootstrap + u-boot + env + linux in dataflash on CS0 */
  268. #define CONFIG_ENV_IS_IN_DATAFLASH
  269. #define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
  270. #define CONFIG_ENV_OFFSET 0x4200
  271. #define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
  272. #define CONFIG_ENV_SIZE 0x4200
  273. #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
  274. #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
  275. "root=/dev/mtdblock0 " \
  276. "mtdparts=atmel_nand:-(root) "\
  277. "rw rootfstype=jffs2"
  278. #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
  279. /* bootstrap + u-boot + env + linux in nandflash */
  280. #define CONFIG_ENV_IS_IN_NAND
  281. #define CONFIG_ENV_OFFSET 0x60000
  282. #define CONFIG_ENV_OFFSET_REDUND 0x80000
  283. #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
  284. #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
  285. #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
  286. "root=/dev/mtdblock5 " \
  287. "mtdparts=atmel_nand:" \
  288. "128k(bootstrap)ro," \
  289. "256k(uboot)ro," \
  290. "128k(env1)ro," \
  291. "128k(env2)ro," \
  292. "2M(linux)," \
  293. "-(root) " \
  294. "rw rootfstype=jffs2"
  295. #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
  296. #define CONFIG_ENV_IS_IN_FLASH 1
  297. #define CONFIG_ENV_OFFSET 0x40000
  298. #define CONFIG_ENV_SECT_SIZE 0x10000
  299. #define CONFIG_ENV_SIZE 0x10000
  300. #define CONFIG_ENV_OVERWRITE 1
  301. /* JFFS Partition offset set */
  302. #define CONFIG_SYS_JFFS2_FIRST_BANK 0
  303. #define CONFIG_SYS_JFFS2_NUM_BANKS 1
  304. /* 512k reserved for u-boot */
  305. #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
  306. #define CONFIG_BOOTCOMMAND "run flashboot"
  307. #define CONFIG_ROOTPATH /ronetix/rootfs
  308. #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
  309. #define CONFIG_CON_ROT "fbcon=rotate:3 "
  310. #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\
  311. CONFIG_CON_ROT
  312. #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
  313. #define MTDPARTS_DEFAULT \
  314. "mtdparts=physmap-flash.0:" \
  315. "256k(u-boot)ro," \
  316. "64k(u-boot-env)ro," \
  317. "1408k(kernel)," \
  318. "-(rootfs);" \
  319. "nand:-(nand)"
  320. #define CONFIG_EXTRA_ENV_SETTINGS \
  321. "mtdids=" MTDIDS_DEFAULT "\0" \
  322. "mtdparts=" MTDPARTS_DEFAULT "\0" \
  323. "partition=nand0,0\0" \
  324. "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
  325. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  326. CONFIG_CON_ROT \
  327. "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
  328. "addip=setenv bootargs $(bootargs) " \
  329. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
  330. ":$(hostname):eth0:off\0" \
  331. "ramboot=tftpboot 0x22000000 vmImage;" \
  332. "run ramargs;run addip;bootm 22000000\0" \
  333. "nfsboot=tftpboot 0x22000000 vmImage;" \
  334. "run nfsargs;run addip;bootm 22000000\0" \
  335. "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
  336. ""
  337. #else
  338. #error "Undefined memory device"
  339. #endif
  340. #define CONFIG_BAUDRATE 115200
  341. #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
  342. #define CONFIG_SYS_PROMPT "u-boot-pm9263> "
  343. #define CONFIG_SYS_CBSIZE 256
  344. #define CONFIG_SYS_MAXARGS 16
  345. #define CONFIG_SYS_PBSIZE \
  346. (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  347. #define CONFIG_SYS_LONGHELP 1
  348. #define CONFIG_CMDLINE_EDITING 1
  349. /*
  350. * Size of malloc() pool
  351. */
  352. #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
  353. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
  354. #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
  355. #ifdef CONFIG_USE_IRQ
  356. #error CONFIG_USE_IRQ not supported
  357. #endif
  358. #endif