pm9261.h 12 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stelian Pop <stelian.pop@leadtechdesign.com>
  4. * Lead Tech Design <www.leadtechdesign.com>
  5. * Ilko Iliev <www.ronetix.at>
  6. *
  7. * Configuation settings for the RONETIX PM9261 board.
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #ifndef __CONFIG_H
  28. #define __CONFIG_H
  29. /* ARM asynchronous clock */
  30. #define AT91_CPU_NAME "AT91SAM9261"
  31. #define CONFIG_DISPLAY_BOARDINFO
  32. #define MASTER_PLL_DIV 15
  33. #define MASTER_PLL_MUL 162
  34. #define MAIN_PLL_DIV 2
  35. #define AT91_MAIN_CLOCK 18432000
  36. #define CONFIG_SYS_HZ 1000
  37. #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
  38. #define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/
  39. #define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */
  40. #define CONFIG_ARCH_CPU_INIT
  41. #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
  42. /* clocks */
  43. /* CKGR_MOR - enable main osc. */
  44. #define CONFIG_SYS_MOR_VAL \
  45. (AT91_PMC_MOSCEN | \
  46. (255 << 8)) /* Main Oscillator Start-up Time */
  47. #define CONFIG_SYS_PLLAR_VAL \
  48. (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
  49. AT91_PMC_OUT | \
  50. ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  51. /* PCK/2 = MCK Master Clock from PLLA */
  52. #define CONFIG_SYS_MCKR1_VAL \
  53. (AT91_PMC_CSS_SLOW | \
  54. AT91_PMC_PRES_1 | \
  55. AT91SAM9_PMC_MDIV_2 | \
  56. AT91_PMC_PDIV_1)
  57. /* PCK/2 = MCK Master Clock from PLLA */
  58. #define CONFIG_SYS_MCKR2_VAL \
  59. (AT91_PMC_CSS_PLLA | \
  60. AT91_PMC_PRES_1 | \
  61. AT91SAM9_PMC_MDIV_2 | \
  62. AT91_PMC_PDIV_1)
  63. /* define PDC[31:16] as DATA[31:16] */
  64. #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
  65. /* no pull-up for D[31:16] */
  66. #define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
  67. /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
  68. #define CONFIG_SYS_MATRIX_EBICSA_VAL \
  69. (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC)
  70. /* SDRAM */
  71. /* SDRAMC_MR Mode register */
  72. #define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
  73. /* SDRAMC_TR - Refresh Timer register */
  74. #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
  75. /* SDRAMC_CR - Configuration register*/
  76. #define CONFIG_SYS_SDRC_CR_VAL \
  77. (AT91_SDRAMC_NC_9 | \
  78. AT91_SDRAMC_NR_13 | \
  79. AT91_SDRAMC_NB_4 | \
  80. AT91_SDRAMC_CAS_3 | \
  81. AT91_SDRAMC_DBW_32 | \
  82. (1 << 8) | /* Write Recovery Delay */ \
  83. (7 << 12) | /* Row Cycle Delay */ \
  84. (3 << 16) | /* Row Precharge Delay */ \
  85. (2 << 20) | /* Row to Column Delay */ \
  86. (5 << 24) | /* Active to Precharge Delay */ \
  87. (1 << 28)) /* Exit Self Refresh to Active Delay */
  88. /* Memory Device Register -> SDRAM */
  89. #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
  90. #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
  91. #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
  92. #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
  93. #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
  94. #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
  95. #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
  96. #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
  97. #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
  98. #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
  99. #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
  100. #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
  101. #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
  102. #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
  103. #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
  104. #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
  105. #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
  106. #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
  107. /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
  108. #define CONFIG_SYS_SMC0_SETUP0_VAL \
  109. (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
  110. AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
  111. #define CONFIG_SYS_SMC0_PULSE0_VAL \
  112. (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
  113. AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
  114. #define CONFIG_SYS_SMC0_CYCLE0_VAL \
  115. (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
  116. #define CONFIG_SYS_SMC0_MODE0_VAL \
  117. (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
  118. AT91_SMC_DBW_16 | \
  119. AT91_SMC_TDFMODE | \
  120. AT91_SMC_TDF_(6))
  121. /* user reset enable */
  122. #define CONFIG_SYS_RSTC_RMR_VAL \
  123. (AT91_RSTC_KEY | \
  124. AT91_RSTC_PROCRST | \
  125. AT91_RSTC_RSTTYP_WAKEUP | \
  126. AT91_RSTC_RSTTYP_WATCHDOG)
  127. /* Disable Watchdog */
  128. #define CONFIG_SYS_WDTC_WDMR_VAL \
  129. (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
  130. AT91_WDT_WDV | \
  131. AT91_WDT_WDDIS | \
  132. AT91_WDT_WDD)
  133. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  134. #define CONFIG_SETUP_MEMORY_TAGS 1
  135. #define CONFIG_INITRD_TAG 1
  136. #undef CONFIG_SKIP_LOWLEVEL_INIT
  137. #undef CONFIG_SKIP_RELOCATE_UBOOT
  138. /*
  139. * Hardware drivers
  140. */
  141. #define CONFIG_ATMEL_USART 1
  142. #undef CONFIG_USART0
  143. #undef CONFIG_USART1
  144. #undef CONFIG_USART2
  145. #define CONFIG_USART3 1 /* USART 3 is DBGU */
  146. /* LCD */
  147. #define CONFIG_LCD 1
  148. #define LCD_BPP LCD_COLOR8
  149. #define CONFIG_LCD_LOGO 1
  150. #undef LCD_TEST_PATTERN
  151. #define CONFIG_LCD_INFO 1
  152. #define CONFIG_LCD_INFO_BELOW_LOGO 1
  153. #define CONFIG_SYS_WHITE_ON_BLACK 1
  154. #define CONFIG_ATMEL_LCD 1
  155. #define CONFIG_ATMEL_LCD_BGR555 1
  156. #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
  157. /* LED */
  158. #define CONFIG_AT91_LED
  159. #define CONFIG_RED_LED AT91_PIN_PC12
  160. #define CONFIG_GREEN_LED AT91_PIN_PC13
  161. #define CONFIG_YELLOW_LED AT91_PIN_PC15
  162. #define CONFIG_BOOTDELAY 3
  163. /*
  164. * BOOTP options
  165. */
  166. #define CONFIG_BOOTP_BOOTFILESIZE 1
  167. #define CONFIG_BOOTP_BOOTPATH 1
  168. #define CONFIG_BOOTP_GATEWAY 1
  169. #define CONFIG_BOOTP_HOSTNAME 1
  170. /*
  171. * Command line configuration.
  172. */
  173. #include <config_cmd_default.h>
  174. #undef CONFIG_CMD_BDI
  175. #undef CONFIG_CMD_IMI
  176. #undef CONFIG_CMD_AUTOSCRIPT
  177. #undef CONFIG_CMD_FPGA
  178. #undef CONFIG_CMD_LOADS
  179. #undef CONFIG_CMD_IMLS
  180. #define CONFIG_CMD_PING 1
  181. #define CONFIG_CMD_DHCP 1
  182. #define CONFIG_CMD_NAND 1
  183. #define CONFIG_CMD_USB 1
  184. /* SDRAM */
  185. #define CONFIG_NR_DRAM_BANKS 1
  186. #define PHYS_SDRAM 0x20000000
  187. #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
  188. /* DataFlash */
  189. #define CONFIG_ATMEL_DATAFLASH_SPI
  190. #define CONFIG_HAS_DATAFLASH
  191. #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
  192. #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
  193. #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
  194. #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */
  195. #define AT91_SPI_CLK 15000000
  196. #define DATAFLASH_TCSS (0x1a << 16)
  197. #define DATAFLASH_TCHS (0x1 << 24)
  198. /* NAND flash */
  199. #define CONFIG_NAND_ATMEL
  200. #define NAND_MAX_CHIPS 1
  201. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  202. #define CONFIG_SYS_NAND_BASE 0x40000000
  203. #define CONFIG_SYS_NAND_DBW_8 1
  204. /* our ALE is AD22 */
  205. #define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
  206. /* our CLE is AD21 */
  207. #define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
  208. #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
  209. #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16
  210. /* NOR flash */
  211. #define CONFIG_SYS_FLASH_CFI 1
  212. #define CONFIG_FLASH_CFI_DRIVER 1
  213. #define PHYS_FLASH_1 0x10000000
  214. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  215. #define CONFIG_SYS_MAX_FLASH_SECT 256
  216. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  217. /* Ethernet */
  218. #define CONFIG_DRIVER_DM9000 1
  219. #define CONFIG_DM9000_BASE 0x30000000
  220. #define DM9000_IO CONFIG_DM9000_BASE
  221. #define DM9000_DATA (CONFIG_DM9000_BASE + 4)
  222. #define CONFIG_DM9000_USE_16BIT 1
  223. #define CONFIG_NET_RETRY_COUNT 20
  224. #define CONFIG_RESET_PHY_R 1
  225. #define CONFIG_NET_MULTI
  226. /* USB */
  227. #define CONFIG_USB_ATMEL
  228. #define CONFIG_USB_OHCI_NEW 1
  229. #define CONFIG_DOS_PARTITION 1
  230. #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
  231. #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
  232. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
  233. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  234. #define CONFIG_USB_STORAGE 1
  235. #define CONFIG_SYS_LOAD_ADDR 0x22000000
  236. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  237. #define CONFIG_SYS_MEMTEST_END 0x23e00000
  238. #undef CONFIG_SYS_USE_DATAFLASH_CS0
  239. #undef CONFIG_SYS_USE_NANDFLASH
  240. #define CONFIG_SYS_USE_FLASH 1
  241. #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
  242. /* bootstrap + u-boot + env + linux in dataflash on CS0 */
  243. #define CONFIG_ENV_IS_IN_DATAFLASH 1
  244. #define CONFIG_SYS_MONITOR_BASE \
  245. (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
  246. #define CONFIG_ENV_OFFSET 0x4200
  247. #define CONFIG_ENV_ADDR \
  248. (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
  249. #define CONFIG_ENV_SIZE 0x4200
  250. #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
  251. #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
  252. "root=/dev/mtdblock0 " \
  253. "mtdparts=atmel_nand:-(root) " \
  254. "rw rootfstype=jffs2"
  255. #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
  256. /* bootstrap + u-boot + env + linux in nandflash */
  257. #define CONFIG_ENV_IS_IN_NAND 1
  258. #define CONFIG_ENV_OFFSET 0x60000
  259. #define CONFIG_ENV_OFFSET_REDUND 0x80000
  260. #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
  261. #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
  262. #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
  263. "root=/dev/mtdblock5 " \
  264. "mtdparts=atmel_nand:128k(bootstrap)ro," \
  265. "256k(uboot)ro,128k(env1)ro," \
  266. "128k(env2)ro,2M(linux),-(root) " \
  267. "rw rootfstype=jffs2"
  268. #elif defined (CONFIG_SYS_USE_FLASH)
  269. #define CONFIG_ENV_IS_IN_FLASH 1
  270. #define CONFIG_ENV_OFFSET 0x40000
  271. #define CONFIG_ENV_SECT_SIZE 0x10000
  272. #define CONFIG_ENV_SIZE 0x10000
  273. #define CONFIG_ENV_OVERWRITE 1
  274. /* JFFS Partition offset set */
  275. #define CONFIG_SYS_JFFS2_FIRST_BANK 0
  276. #define CONFIG_SYS_JFFS2_NUM_BANKS 1
  277. /* 512k reserved for u-boot */
  278. #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
  279. #define CONFIG_BOOTCOMMAND "run flashboot"
  280. #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
  281. #define MTDPARTS_DEFAULT \
  282. "mtdparts=physmap-flash.0:" \
  283. "256k(u-boot)ro," \
  284. "64k(u-boot-env)ro," \
  285. "1408k(kernel)," \
  286. "-(rootfs);" \
  287. "nand:-(nand)"
  288. #define CONFIG_CON_ROT "fbcon=rotate:3 "
  289. #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT
  290. #define CONFIG_EXTRA_ENV_SETTINGS \
  291. "mtdids=" MTDIDS_DEFAULT "\0" \
  292. "mtdparts=" MTDPARTS_DEFAULT "\0" \
  293. "partition=nand0,0\0" \
  294. "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
  295. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  296. CONFIG_CON_ROT \
  297. "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
  298. "addip=setenv bootargs $(bootargs) " \
  299. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
  300. ":$(hostname):eth0:off\0" \
  301. "ramboot=tftpboot 0x22000000 vmImage;" \
  302. "run ramargs;run addip;bootm 22000000\0" \
  303. "nfsboot=tftpboot 0x22000000 vmImage;" \
  304. "run nfsargs;run addip;bootm 22000000\0" \
  305. "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
  306. ""
  307. #else
  308. #error "Undefined memory device"
  309. #endif
  310. #define CONFIG_BAUDRATE 115200
  311. #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
  312. #define CONFIG_SYS_PROMPT "pm9261> "
  313. #define CONFIG_SYS_CBSIZE 256
  314. #define CONFIG_SYS_MAXARGS 16
  315. #define CONFIG_SYS_PBSIZE \
  316. (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  317. #define CONFIG_SYS_LONGHELP 1
  318. #define CONFIG_CMDLINE_EDITING 1
  319. /*
  320. * Size of malloc() pool
  321. */
  322. #define CONFIG_SYS_MALLOC_LEN \
  323. ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
  324. #define CONFIG_SYS_GBL_DATA_SIZE 128
  325. #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
  326. #ifdef CONFIG_USE_IRQ
  327. #error CONFIG_USE_IRQ not supported
  328. #endif
  329. #endif