pdnb3.h 12 KB

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  1. /*
  2. * (C) Copyright 2006-2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * Configuation settings for the PDNB3 board.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #ifndef __CONFIG_H
  26. #define __CONFIG_H
  27. /*
  28. * High Level Configuration Options
  29. * (easy to change)
  30. */
  31. #define CONFIG_IXP425 1 /* This is an IXP425 CPU */
  32. #define CONFIG_PDNB3 1 /* on an PDNB3 board */
  33. #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
  34. #define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
  35. /*
  36. * Ethernet
  37. */
  38. #define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */
  39. #define CONFIG_NET_MULTI 1
  40. #define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */
  41. #define CONFIG_HAS_ETH1
  42. #define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */
  43. #define CONFIG_MII 1 /* MII PHY management */
  44. #define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
  45. /*
  46. * Misc configuration options
  47. */
  48. #define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */
  49. #define CONFIG_TIMER_IRQ
  50. #define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
  51. #define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
  52. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  53. #define CONFIG_SETUP_MEMORY_TAGS 1
  54. #define CONFIG_INITRD_TAG 1
  55. /*
  56. * Size of malloc() pool
  57. */
  58. #define CONFIG_SYS_MALLOC_LEN (1 << 20)
  59. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  60. /* allow to overwrite serial and ethaddr */
  61. #define CONFIG_ENV_OVERWRITE
  62. #define CONFIG_IXP_SERIAL
  63. #define CONFIG_BAUDRATE 115200
  64. #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
  65. /*
  66. * BOOTP options
  67. */
  68. #define CONFIG_BOOTP_BOOTFILESIZE
  69. #define CONFIG_BOOTP_BOOTPATH
  70. #define CONFIG_BOOTP_GATEWAY
  71. #define CONFIG_BOOTP_HOSTNAME
  72. /*
  73. * Command line configuration.
  74. */
  75. #include <config_cmd_default.h>
  76. #define CONFIG_CMD_DHCP
  77. #define CONFIG_CMD_DATE
  78. #define CONFIG_CMD_NET
  79. #define CONFIG_CMD_MII
  80. #define CONFIG_CMD_I2C
  81. #define CONFIG_CMD_ELF
  82. #define CONFIG_CMD_PING
  83. #if !defined(CONFIG_SCPU)
  84. #define CONFIG_CMD_NAND
  85. #endif
  86. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  87. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  88. /*
  89. * Miscellaneous configurable options
  90. */
  91. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  92. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  93. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  94. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  95. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  96. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  97. #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
  98. #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
  99. #define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
  100. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  101. /* valid baudrates */
  102. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  103. /*
  104. * Stack sizes
  105. *
  106. * The stack sizes are set up in start.S using the settings below
  107. */
  108. #define CONFIG_STACKSIZE (128*1024) /* regular stack */
  109. #ifdef CONFIG_USE_IRQ
  110. #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
  111. #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
  112. #endif
  113. /***************************************************************
  114. * Platform/Board specific defines start here.
  115. ***************************************************************/
  116. /*-----------------------------------------------------------------------
  117. * Default configuration (environment varibles...)
  118. *----------------------------------------------------------------------*/
  119. #define CONFIG_PREBOOT "echo;" \
  120. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  121. "echo"
  122. #undef CONFIG_BOOTARGS
  123. #define CONFIG_EXTRA_ENV_SETTINGS \
  124. "netdev=eth0\0" \
  125. "hostname=pdnb3\0" \
  126. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  127. "nfsroot=${serverip}:${rootpath}\0" \
  128. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  129. "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
  130. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  131. ":${hostname}:${netdev}:off panic=1\0" \
  132. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \
  133. "mtdparts=${mtdparts}\0" \
  134. "flash_nfs=run nfsargs addip addtty;" \
  135. "bootm ${kernel_addr}\0" \
  136. "flash_self=run ramargs addip addtty;" \
  137. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  138. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  139. "bootm\0" \
  140. "rootpath=/opt/buildroot\0" \
  141. "bootfile=/tftpboot/netbox/uImage\0" \
  142. "kernel_addr=50080000\0" \
  143. "ramdisk_addr=50200000\0" \
  144. "load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \
  145. "update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \
  146. "cp.b 100000 50000000 ${filesize};" \
  147. "setenv filesize;saveenv\0" \
  148. "upd=run load update\0" \
  149. "ipaddr=10.0.0.233\0" \
  150. "serverip=10.0.0.152\0" \
  151. "netmask=255.255.0.0\0" \
  152. "ethaddr=c6:6f:13:36:f3:81\0" \
  153. "eth1addr=c6:6f:13:36:f3:82\0" \
  154. "mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \
  155. "4k@508k(renv)\0" \
  156. ""
  157. #define CONFIG_BOOTCOMMAND "run net_nfs"
  158. /*
  159. * Physical Memory Map
  160. */
  161. #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  162. #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
  163. #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
  164. #define CONFIG_SYS_FLASH_BASE 0x50000000
  165. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  166. #if defined(CONFIG_SCPU)
  167. #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */
  168. #else
  169. #define CONFIG_SYS_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */
  170. #endif
  171. /*
  172. * Expansion bus settings
  173. */
  174. #if defined(CONFIG_SCPU)
  175. #define CONFIG_SYS_EXP_CS0 0x94d23C42 /* 8bit, max size */
  176. #else
  177. #define CONFIG_SYS_EXP_CS0 0x94913C43 /* 8bit, max size */
  178. #endif
  179. #define CONFIG_SYS_EXP_CS1 0x85000043 /* 8bit, 512bytes */
  180. /*
  181. * SDRAM settings
  182. */
  183. #define CONFIG_SYS_SDR_CONFIG 0x18
  184. #define CONFIG_SYS_SDR_MODE_CONFIG 0x1
  185. #define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
  186. /*
  187. * FLASH and environment organization
  188. */
  189. #if defined(CONFIG_SCPU)
  190. #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  191. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  192. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
  193. #endif
  194. #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
  195. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  196. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  197. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  198. #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
  199. #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
  200. #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
  201. #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
  202. /*
  203. * The following defines are added for buggy IOP480 byte interface.
  204. * All other boards should use the standard values (CPCI405 etc.)
  205. */
  206. #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
  207. #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
  208. #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
  209. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  210. #define CONFIG_ENV_IS_IN_FLASH 1
  211. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
  212. #if defined(CONFIG_SCPU)
  213. /* no redundant environment on SCPU */
  214. #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
  215. #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  216. #else
  217. #define CONFIG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
  218. #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
  219. /* Address and size of Redundant Environment Sector */
  220. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  221. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  222. #endif
  223. #if !defined(CONFIG_SCPU)
  224. /*
  225. * NAND-FLASH stuff
  226. */
  227. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  228. #define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
  229. #endif
  230. /*
  231. * GPIO settings
  232. */
  233. /* FPGA program pin configuration */
  234. #define CONFIG_SYS_GPIO_PRG 12 /* FPGA program pin (cpu output)*/
  235. #define CONFIG_SYS_GPIO_CLK 10 /* FPGA clk pin (cpu output) */
  236. #define CONFIG_SYS_GPIO_DATA 14 /* FPGA data pin (cpu output) */
  237. #define CONFIG_SYS_GPIO_INIT 13 /* FPGA init pin (cpu input) */
  238. #define CONFIG_SYS_GPIO_DONE 11 /* FPGA done pin (cpu input) */
  239. /* other GPIO's */
  240. #define CONFIG_SYS_GPIO_RESTORE_INT 0
  241. #define CONFIG_SYS_GPIO_RESTART_INT 1
  242. #define CONFIG_SYS_GPIO_SYS_RUNNING 2
  243. #define CONFIG_SYS_GPIO_PCI_INTA 3
  244. #define CONFIG_SYS_GPIO_PCI_INTB 4
  245. #define CONFIG_SYS_GPIO_I2C_SCL 6
  246. #define CONFIG_SYS_GPIO_I2C_SDA 7
  247. #define CONFIG_SYS_GPIO_FPGA_RESET 9
  248. #define CONFIG_SYS_GPIO_CLK_33M 15
  249. /*
  250. * I2C stuff
  251. */
  252. /* enable I2C and select the hardware/software driver */
  253. #undef CONFIG_HARD_I2C /* I2C with hardware support */
  254. #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
  255. #define CONFIG_SYS_I2C_SPEED 83000 /* 83 kHz is supposed to work */
  256. #define CONFIG_SYS_I2C_SLAVE 0xFE
  257. /*
  258. * Software (bit-bang) I2C driver configuration
  259. */
  260. #define PB_SCL (1 << CONFIG_SYS_GPIO_I2C_SCL)
  261. #define PB_SDA (1 << CONFIG_SYS_GPIO_I2C_SDA)
  262. #define I2C_INIT GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL)
  263. #define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA)
  264. #define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA)
  265. #define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0)
  266. #define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); \
  267. else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA)
  268. #define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); \
  269. else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL)
  270. #define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
  271. /*
  272. * I2C RTC
  273. */
  274. #if 0 /* test-only */
  275. #define CONFIG_RTC_DS1340 1
  276. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  277. #else
  278. /* M41T11 Serial Access Timekeeper(R) SRAM */
  279. #define CONFIG_RTC_M41T11 1
  280. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  281. #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
  282. #endif
  283. /*
  284. * Spartan3 FPGA configuration support
  285. */
  286. #define CONFIG_SYS_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */
  287. #define CONFIG_SYS_FPGA_PRG (1 << CONFIG_SYS_GPIO_PRG) /* FPGA program pin (cpu output)*/
  288. #define CONFIG_SYS_FPGA_CLK (1 << CONFIG_SYS_GPIO_CLK) /* FPGA clk pin (cpu output) */
  289. #define CONFIG_SYS_FPGA_DATA (1 << CONFIG_SYS_GPIO_DATA) /* FPGA data pin (cpu output) */
  290. #define CONFIG_SYS_FPGA_INIT (1 << CONFIG_SYS_GPIO_INIT) /* FPGA init pin (cpu input) */
  291. #define CONFIG_SYS_FPGA_DONE (1 << CONFIG_SYS_GPIO_DONE) /* FPGA done pin (cpu input) */
  292. /*
  293. * Cache Configuration
  294. */
  295. #define CONFIG_SYS_CACHELINE_SIZE 32
  296. #endif /* __CONFIG_H */