omap3_zoom2.h 8.0 KB

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  1. /*
  2. * (C) Copyright 2006-2009
  3. * Texas Instruments.
  4. * Richard Woodruff <r-woodruff2@ti.com>
  5. * Syed Mohammed Khasim <x0khasim@ti.com>
  6. * Nishanth Menon <nm@ti.com>
  7. * Tom Rix <Tom.Rix@windriver.com>
  8. *
  9. * Configuration settings for the TI OMAP3430 Zoom II board.
  10. *
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. #ifndef __CONFIG_H
  30. #define __CONFIG_H
  31. /*
  32. * High Level Configuration Options
  33. */
  34. #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
  35. #define CONFIG_OMAP 1 /* in a TI OMAP core */
  36. #define CONFIG_OMAP34XX 1 /* which is a 34XX */
  37. #define CONFIG_OMAP3430 1 /* which is in a 3430 */
  38. #define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */
  39. #include <asm/arch/cpu.h> /* get chip and board defs */
  40. #include <asm/arch/omap3.h>
  41. /*
  42. * Display CPU and Board information
  43. */
  44. #define CONFIG_DISPLAY_CPUINFO 1
  45. #define CONFIG_DISPLAY_BOARDINFO 1
  46. /* Clock Defines */
  47. #define V_OSCK 26000000 /* Clock output from T2 */
  48. #define V_SCLK (V_OSCK >> 1)
  49. #undef CONFIG_USE_IRQ /* no support for IRQs */
  50. #define CONFIG_MISC_INIT_R
  51. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  52. #define CONFIG_SETUP_MEMORY_TAGS 1
  53. #define CONFIG_INITRD_TAG 1
  54. #define CONFIG_REVISION_TAG 1
  55. /*
  56. * Size of malloc() pool
  57. */
  58. #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
  59. /* Sector */
  60. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
  61. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
  62. /* initial data */
  63. /*
  64. * Hardware drivers
  65. */
  66. /*
  67. * NS16550 Configuration
  68. * Zoom2 uses the TL16CP754C on the debug board
  69. */
  70. #define CONFIG_SERIAL_MULTI 1
  71. /*
  72. * 0 - 1 : first USB with respect to the left edge of the debug board
  73. * 2 - 3 : second USB with respect to the left edge of the debug board
  74. */
  75. #define ZOOM2_DEFAULT_SERIAL_DEVICE (&zoom2_serial_device0)
  76. #define V_NS16550_CLK (1843200) /* 1.8432 Mhz */
  77. #define CONFIG_SYS_NS16550
  78. #define CONFIG_SYS_NS16550_REG_SIZE (-2)
  79. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  80. #define CONFIG_BAUDRATE 115200
  81. #define CONFIG_SYS_BAUDRATE_TABLE {115200}
  82. /* allow to overwrite serial and ethaddr */
  83. #define CONFIG_ENV_OVERWRITE
  84. #define CONFIG_MMC 1
  85. #define CONFIG_OMAP3_MMC 1
  86. #define CONFIG_DOS_PARTITION 1
  87. /* DDR - I use Micron DDR */
  88. #define CONFIG_OMAP3_MICRON_DDR 1
  89. /* Status LED */
  90. #define CONFIG_STATUS_LED 1 /* Status LED enabled */
  91. #define CONFIG_BOARD_SPECIFIC_LED 1
  92. #define STATUS_LED_BLUE 0
  93. #define STATUS_LED_RED 1
  94. /* Blue */
  95. #define STATUS_LED_BIT STATUS_LED_BLUE
  96. #define STATUS_LED_STATE STATUS_LED_ON
  97. #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
  98. /* Red */
  99. #define STATUS_LED_BIT1 STATUS_LED_RED
  100. #define STATUS_LED_STATE1 STATUS_LED_OFF
  101. #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
  102. /* Optional value */
  103. #define STATUS_LED_BOOT STATUS_LED_BIT
  104. /* GPIO banks */
  105. #ifdef CONFIG_STATUS_LED
  106. #define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */
  107. #define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */
  108. #endif
  109. #define CONFIG_OMAP3_GPIO_3 /* board revision */
  110. #define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */
  111. /* commands to include */
  112. #include <config_cmd_default.h>
  113. #define CONFIG_CMD_FAT /* FAT support */
  114. #define CONFIG_CMD_I2C /* I2C serial bus support */
  115. #define CONFIG_CMD_MMC /* MMC support */
  116. #define CONFIG_CMD_NAND /* NAND support */
  117. #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
  118. #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
  119. #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
  120. #undef CONFIG_CMD_IMI /* iminfo */
  121. #undef CONFIG_CMD_IMLS /* List all found images */
  122. #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
  123. #undef CONFIG_CMD_NFS /* NFS support */
  124. #define CONFIG_SYS_NO_FLASH
  125. #define CONFIG_HARD_I2C 1
  126. #define CONFIG_SYS_I2C_SPEED 100000
  127. #define CONFIG_SYS_I2C_SLAVE 1
  128. #define CONFIG_SYS_I2C_BUS 0
  129. #define CONFIG_SYS_I2C_BUS_SELECT 1
  130. #define CONFIG_DRIVER_OMAP34XX_I2C 1
  131. /*
  132. * TWL4030
  133. */
  134. #define CONFIG_TWL4030_POWER 1
  135. #define CONFIG_TWL4030_LED 1
  136. /*
  137. * Board NAND Info.
  138. */
  139. #define CONFIG_NAND_OMAP_GPMC
  140. #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  141. /* to access nand */
  142. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  143. /* to access nand at */
  144. /* CS0 */
  145. #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
  146. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  147. /* Environment information */
  148. #define CONFIG_BOOTDELAY 10
  149. /*
  150. * Miscellaneous configurable options
  151. */
  152. #define CONFIG_SYS_PROMPT "OMAP3 Zoom2 # "
  153. #define CONFIG_SYS_LONGHELP
  154. #define CONFIG_SYS_CBSIZE 256
  155. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  156. sizeof(CONFIG_SYS_PROMPT) + 16)
  157. #define CONFIG_SYS_MAXARGS 16
  158. #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
  159. /* Memtest from start of memory to 31MB */
  160. #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
  161. #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000)
  162. /* The default load address is the start of memory */
  163. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
  164. /* everything, incl board info, in Hz */
  165. #undef CONFIG_SYS_CLKS_IN_HZ
  166. /*
  167. * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
  168. * 32KHz clk, or from external sig. This rate is divided by a local divisor.
  169. */
  170. #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  171. #define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
  172. #define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
  173. /*-----------------------------------------------------------------------
  174. * Stack sizes
  175. *
  176. * The stack sizes are set up in start.S using these settings
  177. */
  178. #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
  179. #ifdef CONFIG_USE_IRQ
  180. #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
  181. #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
  182. #endif
  183. /*-----------------------------------------------------------------------
  184. * Physical Memory Map
  185. */
  186. #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  187. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  188. #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
  189. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  190. /* SDRAM Bank Allocation method */
  191. #define SDRC_R_B_C 1
  192. /*-----------------------------------------------------------------------
  193. * FLASH and environment organization
  194. */
  195. /* **** PISMO SUPPORT *** */
  196. /* Configure the PISMO */
  197. #define PISMO1_NAND_SIZE GPMC_SIZE_128M
  198. #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
  199. #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
  200. /* one chip */
  201. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
  202. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  203. #define CONFIG_SYS_FLASH_BASE boot_flash_base
  204. /* Monitor at start of flash */
  205. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  206. #define CONFIG_ENV_IS_IN_NAND 1
  207. #define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */
  208. #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
  209. #define CONFIG_ENV_OFFSET boot_flash_off
  210. #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
  211. /*-----------------------------------------------------------------------
  212. * CFI FLASH driver setup
  213. */
  214. /* timeout values are in ticks */
  215. #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
  216. #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
  217. #ifndef __ASSEMBLY__
  218. extern struct gpmc *gpmc_cfg;
  219. extern unsigned int boot_flash_base;
  220. extern volatile unsigned int boot_flash_env_addr;
  221. extern unsigned int boot_flash_off;
  222. extern unsigned int boot_flash_sec;
  223. extern unsigned int boot_flash_type;
  224. #endif
  225. #endif /* __CONFIG_H */