omap3_zoom1.h 9.3 KB

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  1. /*
  2. * (C) Copyright 2006-2008
  3. * Texas Instruments.
  4. * Richard Woodruff <r-woodruff2@ti.com>
  5. * Syed Mohammed Khasim <x0khasim@ti.com>
  6. * Nishanth Menon <nm@ti.com>
  7. *
  8. * Configuration settings for the TI OMAP3430 Zoom MDK board.
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. #ifndef __CONFIG_H
  29. #define __CONFIG_H
  30. /*
  31. * High Level Configuration Options
  32. */
  33. #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
  34. #define CONFIG_OMAP 1 /* in a TI OMAP core */
  35. #define CONFIG_OMAP34XX 1 /* which is a 34XX */
  36. #define CONFIG_OMAP3430 1 /* which is in a 3430 */
  37. #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
  38. #include <asm/arch/cpu.h> /* get chip and board defs */
  39. #include <asm/arch/omap3.h>
  40. /*
  41. * Display CPU and Board information
  42. */
  43. #define CONFIG_DISPLAY_CPUINFO 1
  44. #define CONFIG_DISPLAY_BOARDINFO 1
  45. /* Clock Defines */
  46. #define V_OSCK 26000000 /* Clock output from T2 */
  47. #define V_SCLK (V_OSCK >> 1)
  48. #undef CONFIG_USE_IRQ /* no support for IRQs */
  49. #define CONFIG_MISC_INIT_R
  50. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  51. #define CONFIG_SETUP_MEMORY_TAGS 1
  52. #define CONFIG_INITRD_TAG 1
  53. #define CONFIG_REVISION_TAG 1
  54. /*
  55. * Size of malloc() pool
  56. */
  57. #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
  58. /* Sector */
  59. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
  60. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
  61. /* initial data */
  62. /*
  63. * Hardware drivers
  64. */
  65. /*
  66. * NS16550 Configuration
  67. */
  68. #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  69. #define CONFIG_SYS_NS16550
  70. #define CONFIG_SYS_NS16550_SERIAL
  71. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  72. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  73. /*
  74. * select serial console configuration
  75. */
  76. #define CONFIG_CONS_INDEX 3
  77. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  78. #define CONFIG_SERIAL3 3 /* UART3 */
  79. /* allow to overwrite serial and ethaddr */
  80. #define CONFIG_ENV_OVERWRITE
  81. #define CONFIG_BAUDRATE 115200
  82. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  83. 115200}
  84. #define CONFIG_MMC 1
  85. #define CONFIG_OMAP3_MMC 1
  86. #define CONFIG_DOS_PARTITION 1
  87. /* DDR - I use Micron DDR */
  88. #define CONFIG_OMAP3_MICRON_DDR 1
  89. /* commands to include */
  90. #include <config_cmd_default.h>
  91. #define CONFIG_CMD_EXT2 /* EXT2 Support */
  92. #define CONFIG_CMD_FAT /* FAT support */
  93. #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
  94. #define CONFIG_CMD_I2C /* I2C serial bus support */
  95. #define CONFIG_CMD_MMC /* MMC support */
  96. #define CONFIG_CMD_NAND /* NAND support */
  97. #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
  98. #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
  99. #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
  100. #undef CONFIG_CMD_IMI /* iminfo */
  101. #undef CONFIG_CMD_IMLS /* List all found images */
  102. #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
  103. #undef CONFIG_CMD_NFS /* NFS support */
  104. #define CONFIG_SYS_NO_FLASH
  105. #define CONFIG_HARD_I2C 1
  106. #define CONFIG_SYS_I2C_SPEED 100000
  107. #define CONFIG_SYS_I2C_SLAVE 1
  108. #define CONFIG_SYS_I2C_BUS 0
  109. #define CONFIG_SYS_I2C_BUS_SELECT 1
  110. #define CONFIG_DRIVER_OMAP34XX_I2C 1
  111. /*
  112. * TWL4030
  113. */
  114. #define CONFIG_TWL4030_POWER 1
  115. #define CONFIG_TWL4030_LED 1
  116. /*
  117. * Board NAND Info.
  118. */
  119. #define CONFIG_NAND_OMAP_GPMC
  120. #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  121. /* to access nand */
  122. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  123. /* to access nand at */
  124. /* CS0 */
  125. #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
  126. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  127. /* devices */
  128. #define CONFIG_JFFS2_NAND
  129. /* nand device jffs2 lives on */
  130. #define CONFIG_JFFS2_DEV "nand0"
  131. /* start of jffs2 partition */
  132. #define CONFIG_JFFS2_PART_OFFSET 0x680000
  133. #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
  134. /* partition */
  135. /* Environment information */
  136. #define CONFIG_BOOTDELAY 10
  137. #define CONFIG_EXTRA_ENV_SETTINGS \
  138. "loadaddr=0x82000000\0" \
  139. "console=ttyS2,115200n8\0" \
  140. "videomode=1024x768@60,vxres=1024,vyres=768\0" \
  141. "videospec=omapfb:vram:2M,vram:4M\0" \
  142. "mmcargs=setenv bootargs console=${console} " \
  143. "video=${videospec},mode:${videomode} " \
  144. "root=/dev/mmcblk0p2 rw " \
  145. "rootfstype=ext3 rootwait\0" \
  146. "nandargs=setenv bootargs console=${console} " \
  147. "video=${videospec},mode:${videomode} " \
  148. "root=/dev/mtdblock4 rw " \
  149. "rootfstype=jffs2\0" \
  150. "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
  151. "bootscript=echo Running bootscript from mmc ...; " \
  152. "source ${loadaddr}\0" \
  153. "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
  154. "mmcboot=echo Booting from mmc ...; " \
  155. "run mmcargs; " \
  156. "bootm ${loadaddr}\0" \
  157. "nandboot=echo Booting from nand ...; " \
  158. "run nandargs; " \
  159. "nand read ${loadaddr} 280000 400000; " \
  160. "bootm ${loadaddr}\0" \
  161. #define CONFIG_BOOTCOMMAND \
  162. "if mmc init; then " \
  163. "if run loadbootscript; then " \
  164. "run bootscript; " \
  165. "else " \
  166. "if run loaduimage; then " \
  167. "run mmcboot; " \
  168. "else run nandboot; " \
  169. "fi; " \
  170. "fi; " \
  171. "else run nandboot; fi"
  172. #define CONFIG_AUTO_COMPLETE 1
  173. /*
  174. * Miscellaneous configurable options
  175. */
  176. #define V_PROMPT "OMAP3 Zoom1# "
  177. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  178. #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  179. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  180. #define CONFIG_SYS_PROMPT V_PROMPT
  181. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  182. /* Print Buffer Size */
  183. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  184. sizeof(CONFIG_SYS_PROMPT) + 16)
  185. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  186. /* Boot Argument Buffer Size */
  187. #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
  188. #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
  189. /* works on */
  190. #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
  191. 0x01F00000) /* 31MB */
  192. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
  193. /* load address */
  194. /*
  195. * OMAP3 has 12 GP timers, they can be driven by the system clock
  196. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  197. * This rate is divided by a local divisor.
  198. */
  199. #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
  200. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  201. #define CONFIG_SYS_HZ 1000
  202. /*-----------------------------------------------------------------------
  203. * Stack sizes
  204. *
  205. * The stack sizes are set up in start.S using the settings below
  206. */
  207. #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
  208. #ifdef CONFIG_USE_IRQ
  209. #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
  210. #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
  211. #endif
  212. /*-----------------------------------------------------------------------
  213. * Physical Memory Map
  214. */
  215. #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  216. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  217. #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
  218. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  219. /* SDRAM Bank Allocation method */
  220. #define SDRC_R_B_C 1
  221. /*-----------------------------------------------------------------------
  222. * FLASH and environment organization
  223. */
  224. /* **** PISMO SUPPORT *** */
  225. /* Configure the PISMO */
  226. #define PISMO1_NAND_SIZE GPMC_SIZE_128M
  227. #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
  228. #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
  229. /* one chip */
  230. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
  231. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  232. #define CONFIG_SYS_FLASH_BASE boot_flash_base
  233. /* Monitor at start of flash */
  234. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  235. #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
  236. #define CONFIG_ENV_IS_IN_NAND 1
  237. #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
  238. #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
  239. #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
  240. #define CONFIG_ENV_OFFSET boot_flash_off
  241. #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
  242. /*-----------------------------------------------------------------------
  243. * CFI FLASH driver setup
  244. */
  245. /* timeout values are in ticks */
  246. #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
  247. #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
  248. /* Flash banks JFFS2 should use */
  249. #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
  250. CONFIG_SYS_MAX_NAND_DEVICE)
  251. #define CONFIG_SYS_JFFS2_MEM_NAND
  252. /* use flash_info[2] */
  253. #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
  254. #define CONFIG_SYS_JFFS2_NUM_BANKS 1
  255. #ifndef __ASSEMBLY__
  256. extern struct gpmc *gpmc_cfg;
  257. extern unsigned int boot_flash_base;
  258. extern volatile unsigned int boot_flash_env_addr;
  259. extern unsigned int boot_flash_off;
  260. extern unsigned int boot_flash_sec;
  261. extern unsigned int boot_flash_type;
  262. #endif
  263. #endif /* __CONFIG_H */