mpc5121ads.h 20 KB

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  1. /*
  2. * (C) Copyright 2007-2009 DENX Software Engineering
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. /*
  23. * MPC5121ADS board configuration file
  24. */
  25. #ifndef __CONFIG_H
  26. #define __CONFIG_H
  27. #define CONFIG_MPC5121ADS 1
  28. /*
  29. * Memory map for the MPC5121ADS board:
  30. *
  31. * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
  32. * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
  33. * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
  34. * 0x8200_0000 - 0x8200_001F CPLD (32 B)
  35. * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
  36. * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
  37. * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
  38. * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
  39. */
  40. /*
  41. * High Level Configuration Options
  42. */
  43. #define CONFIG_E300 1 /* E300 Family */
  44. #define CONFIG_MPC512X 1 /* MPC512X family */
  45. #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
  46. #undef CONFIG_FSL_DIU_LOGO_BMP /* Don't include FSL DIU binary bmp */
  47. /* video */
  48. #undef CONFIG_VIDEO
  49. #if defined(CONFIG_VIDEO)
  50. #define CONFIG_CFB_CONSOLE
  51. #define CONFIG_VGA_AS_SINGLE_DEVICE
  52. #endif
  53. /* CONFIG_PCI is defined at config time */
  54. #ifdef CONFIG_MPC5121ADS_REV2
  55. #define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */
  56. #else
  57. #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
  58. #define CONFIG_PCI
  59. #endif
  60. #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
  61. #define CONFIG_MISC_INIT_R
  62. #define CONFIG_SYS_IMMR 0x80000000
  63. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
  64. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
  65. #define CONFIG_SYS_MEMTEST_END 0x00400000
  66. /*
  67. * DDR Setup - manually set all parameters as there's no SPD etc.
  68. */
  69. #ifdef CONFIG_MPC5121ADS_REV2
  70. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  71. #else
  72. #define CONFIG_SYS_DDR_SIZE 512 /* MB */
  73. #endif
  74. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  75. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  76. /* DDR Controller Configuration
  77. *
  78. * SYS_CFG:
  79. * [31:31] MDDRC Soft Reset: Diabled
  80. * [30:30] DRAM CKE pin: Enabled
  81. * [29:29] DRAM CLK: Enabled
  82. * [28:28] Command Mode: Enabled (For initialization only)
  83. * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
  84. * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
  85. * [20:19] Read Test: DON'T USE
  86. * [18:18] Self Refresh: Enabled
  87. * [17:17] 16bit Mode: Disabled
  88. * [16:13] Ready Delay: 2
  89. * [12:12] Half DQS Delay: Disabled
  90. * [11:11] Quarter DQS Delay: Disabled
  91. * [10:08] Write Delay: 2
  92. * [07:07] Early ODT: Disabled
  93. * [06:06] On DIE Termination: Disabled
  94. * [05:05] FIFO Overflow Clear: DON'T USE here
  95. * [04:04] FIFO Underflow Clear: DON'T USE here
  96. * [03:03] FIFO Overflow Pending: DON'T USE here
  97. * [02:02] FIFO Underlfow Pending: DON'T USE here
  98. * [01:01] FIFO Overlfow Enabled: Enabled
  99. * [00:00] FIFO Underflow Enabled: Enabled
  100. * TIME_CFG0
  101. * [31:16] DRAM Refresh Time: 0 CSB clocks
  102. * [15:8] DRAM Command Time: 0 CSB clocks
  103. * [07:00] DRAM Precharge Time: 0 CSB clocks
  104. * TIME_CFG1
  105. * [31:26] DRAM tRFC:
  106. * [25:21] DRAM tWR1:
  107. * [20:17] DRAM tWRT1:
  108. * [16:11] DRAM tDRR:
  109. * [10:05] DRAM tRC:
  110. * [04:00] DRAM tRAS:
  111. * TIME_CFG2
  112. * [31:28] DRAM tRCD:
  113. * [27:23] DRAM tFAW:
  114. * [22:19] DRAM tRTW1:
  115. * [18:15] DRAM tCCD:
  116. * [14:10] DRAM tRTP:
  117. * [09:05] DRAM tRP:
  118. * [04:00] DRAM tRPA
  119. */
  120. #ifdef CONFIG_MPC5121ADS_REV2
  121. #define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00
  122. #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168
  123. #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864
  124. #else
  125. #define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00
  126. #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
  127. #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
  128. #endif
  129. #define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E
  130. #define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00
  131. #define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189
  132. #define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864
  133. #define CONFIG_SYS_DDRCMD_NOP 0x01380000
  134. #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
  135. #define CONFIG_SYS_DDRCMD_EM2 0x01020000
  136. #define CONFIG_SYS_DDRCMD_EM3 0x01030000
  137. #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000
  138. #define CONFIG_SYS_DDRCMD_RFSH 0x01080000
  139. #define DDRCMD_EMR_OCD(pr, ohm) ( \
  140. (1 << 24) | /* MDDRC Command Request */ \
  141. (1 << 16) | /* MODE Reg BA[2:0] */ \
  142. (0 << 12) | /* Outputs 0=Enabled */ \
  143. (0 << 11) | /* RDQS */ \
  144. (1 << 10) | /* DQS# */ \
  145. (pr << 7) | /* OCD prog 7=deflt,0=exit */ \
  146. /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
  147. ((ohm & 0x2) << 5)| /* Rtt1 */ \
  148. (0 << 3) | /* additive posted CAS# */ \
  149. ((ohm & 0x1) << 2)| /* Rtt0 */ \
  150. (0 << 0) | /* Output Drive Strength */ \
  151. (0 << 0)) /* DLL Enable 0=Normal */
  152. #define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0)
  153. #define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0)
  154. #define DDRCMD_MODE_REG(cas, wr) ( \
  155. (1 << 24) | /* MDDRC Command Request */ \
  156. (0 << 16) | /* MODE Reg BA[2:0] */ \
  157. ((wr-1) << 9)| /* Write Recovery */ \
  158. (cas << 4) | /* CAS */ \
  159. (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \
  160. (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */
  161. #define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3)
  162. #define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4)
  163. #define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8))
  164. /* DDR Priority Manager Configuration */
  165. #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
  166. #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
  167. #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
  168. #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
  169. #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
  170. #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
  171. #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
  172. #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
  173. #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
  174. #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
  175. #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
  176. #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
  177. #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
  178. #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
  179. #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
  180. #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
  181. #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
  182. #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
  183. #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
  184. #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
  185. #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
  186. #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
  187. #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
  188. /*
  189. * NOR FLASH on the Local Bus
  190. */
  191. #undef CONFIG_BKUP_FLASH
  192. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  193. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  194. #ifdef CONFIG_BKUP_FLASH
  195. #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
  196. #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */
  197. #else
  198. #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
  199. #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */
  200. #endif
  201. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  202. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  203. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
  204. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
  205. #undef CONFIG_SYS_FLASH_CHECKSUM
  206. /*
  207. * NAND FLASH
  208. * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
  209. */
  210. #define CONFIG_CMD_NAND /* enable NAND support */
  211. #define CONFIG_JFFS2_NAND /* with JFFS2 on it */
  212. #define CONFIG_NAND_MPC5121_NFC
  213. #define CONFIG_SYS_NAND_BASE 0x40000000
  214. #define CONFIG_SYS_MAX_NAND_DEVICE 2
  215. #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
  216. #define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
  217. /*
  218. * Configuration parameters for MPC5121 NAND driver
  219. */
  220. #define CONFIG_FSL_NFC_WIDTH 1
  221. #define CONFIG_FSL_NFC_WRITE_SIZE 2048
  222. #define CONFIG_FSL_NFC_SPARE_SIZE 64
  223. #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
  224. /*
  225. * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
  226. * window is 64KB
  227. */
  228. #define CONFIG_SYS_CPLD_BASE 0x82000000
  229. #define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */
  230. #define CONFIG_SYS_SRAM_BASE 0x30000000
  231. #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
  232. #define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
  233. #define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
  234. #define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */
  235. /* Use SRAM for initial stack */
  236. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */
  237. #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE /* End of used area in RAM */
  238. #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
  239. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  240. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  241. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */
  242. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  243. #ifdef CONFIG_FSL_DIU_FB
  244. #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
  245. #else
  246. #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
  247. #endif
  248. /*
  249. * Serial Port
  250. */
  251. #define CONFIG_CONS_INDEX 1
  252. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  253. /*
  254. * Serial console configuration
  255. */
  256. #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
  257. #if CONFIG_PSC_CONSOLE != 3
  258. #error CONFIG_PSC_CONSOLE must be 3
  259. #endif
  260. #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
  261. #define CONFIG_SYS_BAUDRATE_TABLE \
  262. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  263. #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
  264. #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
  265. #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
  266. #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
  267. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  268. /* Use the HUSH parser */
  269. #define CONFIG_SYS_HUSH_PARSER
  270. #ifdef CONFIG_SYS_HUSH_PARSER
  271. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  272. #endif
  273. /*
  274. * PCI
  275. */
  276. #ifdef CONFIG_PCI
  277. /*
  278. * General PCI
  279. */
  280. #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
  281. #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
  282. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
  283. #define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
  284. #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
  285. #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
  286. #define CONFIG_SYS_PCI_IO_BASE 0x00000000
  287. #define CONFIG_SYS_PCI_IO_PHYS 0x84000000
  288. #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
  289. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  290. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  291. #endif
  292. /* I2C */
  293. #define CONFIG_HARD_I2C /* I2C with hardware support */
  294. #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
  295. #define CONFIG_I2C_MULTI_BUS
  296. #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
  297. #define CONFIG_SYS_I2C_SLAVE 0x7F
  298. #if 0
  299. #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
  300. #endif
  301. /*
  302. * IIM - IC Identification Module
  303. */
  304. #undef CONFIG_IIM
  305. /*
  306. * EEPROM configuration
  307. */
  308. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
  309. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
  310. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
  311. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
  312. /*
  313. * Ethernet configuration
  314. */
  315. #define CONFIG_MPC512x_FEC 1
  316. #define CONFIG_NET_MULTI
  317. #define CONFIG_PHY_ADDR 0x1
  318. #define CONFIG_MII 1 /* MII PHY management */
  319. #define CONFIG_FEC_AN_TIMEOUT 1
  320. #define CONFIG_HAS_ETH0
  321. /*
  322. * Configure on-board RTC
  323. */
  324. #define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */
  325. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  326. /*
  327. * Environment
  328. */
  329. #define CONFIG_ENV_IS_IN_FLASH 1
  330. /* This has to be a multiple of the Flash sector size */
  331. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  332. #define CONFIG_ENV_SIZE 0x2000
  333. #ifdef CONFIG_BKUP_FLASH
  334. #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */
  335. #else
  336. #define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
  337. #endif
  338. /* Address and size of Redundant Environment Sector */
  339. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  340. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  341. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  342. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  343. #include <config_cmd_default.h>
  344. #define CONFIG_CMD_ASKENV
  345. #define CONFIG_CMD_DATE
  346. #define CONFIG_CMD_DHCP
  347. #define CONFIG_CMD_EEPROM
  348. #define CONFIG_CMD_EXT2
  349. #define CONFIG_CMD_I2C
  350. #define CONFIG_CMD_IDE
  351. #define CONFIG_CMD_JFFS2
  352. #define CONFIG_CMD_MII
  353. #define CONFIG_CMD_NFS
  354. #define CONFIG_CMD_PING
  355. #define CONFIG_CMD_REGINFO
  356. #undef CONFIG_CMD_FUSE
  357. #if defined(CONFIG_PCI)
  358. #define CONFIG_CMD_PCI
  359. #endif
  360. /*
  361. * Dynamic MTD partition support
  362. */
  363. #define CONFIG_CMD_MTDPARTS
  364. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  365. #define CONFIG_FLASH_CFI_MTD
  366. #define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand"
  367. /*
  368. * NOR flash layout:
  369. *
  370. * FC000000 - FEABFFFF 42.75 MiB User Data
  371. * FEAC0000 - FFABFFFF 16 MiB Root File System
  372. * FFAC0000 - FFEBFFFF 4 MiB Linux Kernel
  373. * FFEC0000 - FFEFFFFF 256 KiB Device Tree
  374. * FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env
  375. *
  376. * NAND flash layout: one big partition
  377. */
  378. #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \
  379. "16m(rootfs)," \
  380. "4m(kernel)," \
  381. "256k(dtb)," \
  382. "1m(u-boot);" \
  383. "mpc5121.nand:-(data)"
  384. #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
  385. #define CONFIG_DOS_PARTITION
  386. #define CONFIG_MAC_PARTITION
  387. #define CONFIG_ISO_PARTITION
  388. #endif /* defined(CONFIG_CMD_IDE) */
  389. /*
  390. * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
  391. * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
  392. * to 0xFFFF, watchdog timeouts after about 64s. For details refer
  393. * to chapter 36 of the MPC5121e Reference Manual.
  394. */
  395. /* #define CONFIG_WATCHDOG */ /* enable watchdog */
  396. #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
  397. /*
  398. * Miscellaneous configurable options
  399. */
  400. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  401. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  402. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  403. #ifdef CONFIG_CMD_KGDB
  404. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  405. #else
  406. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  407. #endif
  408. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
  409. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  410. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  411. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  412. /*
  413. * For booting Linux, the board info and command line data
  414. * have to be in the first 8 MB of memory, since this is
  415. * the maximum mapped by the Linux kernel during initialization.
  416. */
  417. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  418. /* Cache Configuration */
  419. #define CONFIG_SYS_DCACHE_SIZE 32768
  420. #define CONFIG_SYS_CACHELINE_SIZE 32
  421. #ifdef CONFIG_CMD_KGDB
  422. #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
  423. #endif
  424. #define CONFIG_SYS_HID0_INIT 0x000000000
  425. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
  426. #define CONFIG_SYS_HID2 HID2_HBE
  427. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  428. /*
  429. * Internal Definitions
  430. *
  431. * Boot Flags
  432. */
  433. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  434. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  435. #ifdef CONFIG_CMD_KGDB
  436. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  437. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  438. #endif
  439. /*
  440. * Environment Configuration
  441. */
  442. #define CONFIG_TIMESTAMP
  443. #define CONFIG_HOSTNAME mpc5121ads
  444. #define CONFIG_BOOTFILE mpc5121ads/uImage
  445. #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
  446. #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
  447. #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
  448. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  449. #define CONFIG_BAUDRATE 115200
  450. #define CONFIG_PREBOOT "echo;" \
  451. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  452. "echo"
  453. #define CONFIG_EXTRA_ENV_SETTINGS \
  454. "u-boot_addr_r=200000\0" \
  455. "kernel_addr_r=600000\0" \
  456. "fdt_addr_r=880000\0" \
  457. "ramdisk_addr_r=900000\0" \
  458. "u-boot_addr=FFF00000\0" \
  459. "kernel_addr=FFAC0000\0" \
  460. "fdt_addr=FFEC0000\0" \
  461. "ramdisk_addr=FEAC0000\0" \
  462. "ramdiskfile=mpc5121ads/uRamdisk\0" \
  463. "u-boot=mpc5121ads/u-boot.bin\0" \
  464. "bootfile=mpc5121ads/uImage\0" \
  465. "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \
  466. "rootpath=/opt/eldk/ppc_6xx\n" \
  467. "netdev=eth0\0" \
  468. "consdev=ttyPSC0\0" \
  469. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  470. "nfsroot=${serverip}:${rootpath}\0" \
  471. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  472. "addip=setenv bootargs ${bootargs} " \
  473. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  474. ":${hostname}:${netdev}:off panic=1\0" \
  475. "addtty=setenv bootargs ${bootargs} " \
  476. "console=${consdev},${baudrate}\0" \
  477. "flash_nfs=run nfsargs addip addtty;" \
  478. "bootm ${kernel_addr} - ${fdt_addr}\0" \
  479. "flash_self=run ramargs addip addtty;" \
  480. "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
  481. "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
  482. "tftp ${fdt_addr_r} ${fdtfile};" \
  483. "run nfsargs addip addtty;" \
  484. "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  485. "net_self=tftp ${kernel_addr_r} ${bootfile};" \
  486. "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
  487. "tftp ${fdt_addr_r} ${fdtfile};" \
  488. "run ramargs addip addtty;" \
  489. "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
  490. "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
  491. "update=protect off ${u-boot_addr} +${filesize};" \
  492. "era ${u-boot_addr} +${filesize};" \
  493. "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
  494. "upd=run load update\0" \
  495. ""
  496. #define CONFIG_BOOTCOMMAND "run flash_self"
  497. #define CONFIG_OF_LIBFDT 1
  498. #define CONFIG_OF_BOARD_SETUP 1
  499. #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
  500. #define OF_CPU "PowerPC,5121@0"
  501. #define OF_SOC_COMPAT "fsl,mpc5121-immr"
  502. #define OF_TBCLK (bd->bi_busfreq / 4)
  503. #define OF_STDOUT_PATH "/soc@80000000/serial@11300"
  504. /*-----------------------------------------------------------------------
  505. * IDE/ATA stuff
  506. *-----------------------------------------------------------------------
  507. */
  508. #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
  509. #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  510. #undef CONFIG_IDE_LED /* LED for IDE not supported */
  511. #define CONFIG_IDE_RESET /* reset for IDE supported */
  512. #define CONFIG_IDE_PREINIT
  513. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
  514. #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
  515. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  516. #define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
  517. /* Offset for data I/O RefMan MPC5121EE Table 28-10 */
  518. #define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
  519. /* Offset for normal register accesses */
  520. #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
  521. /* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
  522. #define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
  523. /* Interval between registers */
  524. #define CONFIG_SYS_ATA_STRIDE 4
  525. #define ATA_BASE_ADDR get_pata_base()
  526. /*
  527. * Control register bit definitions
  528. */
  529. #define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
  530. #define FSL_ATA_CTRL_ATA_RST_B 0x40000000
  531. #define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
  532. #define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
  533. #define FSL_ATA_CTRL_DMA_PENDING 0x08000000
  534. #define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
  535. #define FSL_ATA_CTRL_DMA_WRITE 0x02000000
  536. #define FSL_ATA_CTRL_IORDY_EN 0x01000000
  537. #endif /* __CONFIG_H */