mecp5123.h 14 KB

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  1. /*
  2. * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
  3. * (C) Copyright 2009, DAVE Srl <www.dave.eu>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. * modifications for the MECP5123 by reinhard.arlt@esd-electronics.com
  24. *
  25. */
  26. /*
  27. * MECP5123 board configuration file
  28. */
  29. #ifndef __CONFIG_H
  30. #define __CONFIG_H
  31. #define CONFIG_MECP5123 1
  32. /*
  33. * Memory map for the MECP5123 board:
  34. *
  35. * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB)
  36. * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
  37. * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
  38. * 0x8200_0000 - 0x8200_FFFF VPC-3 (64 KB)
  39. * 0xFFC0_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
  40. */
  41. /*
  42. * High Level Configuration Options
  43. */
  44. #define CONFIG_E300 1 /* E300 Family */
  45. #define CONFIG_MPC512X 1 /* MPC512X family */
  46. #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
  47. #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
  48. #define CONFIG_MISC_INIT_R
  49. #define CONFIG_SYS_IMMR 0x80000000
  50. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
  51. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
  52. #define CONFIG_SYS_MEMTEST_END 0x00400000
  53. /*
  54. * DDR Setup - manually set all parameters as there's no SPD etc.
  55. */
  56. #define CONFIG_SYS_DDR_SIZE 512 /* MB */
  57. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
  58. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  59. /* DDR Controller Configuration
  60. *
  61. * SYS_CFG:
  62. * [31:31] MDDRC Soft Reset: Diabled
  63. * [30:30] DRAM CKE pin: Enabled
  64. * [29:29] DRAM CLK: Enabled
  65. * [28:28] Command Mode: Enabled (For initialization only)
  66. * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
  67. * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
  68. * [20:19] Read Test: DON'T USE
  69. * [18:18] Self Refresh: Enabled
  70. * [17:17] 16bit Mode: Disabled
  71. * [16:13] Ready Delay: 2
  72. * [12:12] Half DQS Delay: Disabled
  73. * [11:11] Quarter DQS Delay: Disabled
  74. * [10:08] Write Delay: 2
  75. * [07:07] Early ODT: Disabled
  76. * [06:06] On DIE Termination: Disabled
  77. * [05:05] FIFO Overflow Clear: DON'T USE here
  78. * [04:04] FIFO Underflow Clear: DON'T USE here
  79. * [03:03] FIFO Overflow Pending: DON'T USE here
  80. * [02:02] FIFO Underlfow Pending: DON'T USE here
  81. * [01:01] FIFO Overlfow Enabled: Enabled
  82. * [00:00] FIFO Underflow Enabled: Enabled
  83. * TIME_CFG0
  84. * [31:16] DRAM Refresh Time: 0 CSB clocks
  85. * [15:8] DRAM Command Time: 0 CSB clocks
  86. * [07:00] DRAM Precharge Time: 0 CSB clocks
  87. * TIME_CFG1
  88. * [31:26] DRAM tRFC:
  89. * [25:21] DRAM tWR1:
  90. * [20:17] DRAM tWRT1:
  91. * [16:11] DRAM tDRR:
  92. * [10:05] DRAM tRC:
  93. * [04:00] DRAM tRAS:
  94. * TIME_CFG2
  95. * [31:28] DRAM tRCD:
  96. * [27:23] DRAM tFAW:
  97. * [22:19] DRAM tRTW1:
  98. * [18:15] DRAM tCCD:
  99. * [14:10] DRAM tRTP:
  100. * [09:05] DRAM tRP:
  101. * [04:00] DRAM tRPA
  102. */
  103. #define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00
  104. #define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E
  105. #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
  106. #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
  107. #define CONFIG_SYS_DDRCMD_NOP 0x01380000
  108. #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
  109. #define CONFIG_SYS_DDRCMD_EM2 0x01020000
  110. #define CONFIG_SYS_DDRCMD_EM3 0x01030000
  111. #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000
  112. #define CONFIG_SYS_DDRCMD_RFSH 0x01080000
  113. #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
  114. #define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780
  115. /* DDR Priority Manager Configuration */
  116. #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
  117. #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
  118. #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
  119. #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
  120. #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
  121. #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
  122. #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
  123. #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
  124. #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
  125. #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
  126. #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
  127. #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
  128. #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
  129. #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
  130. #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
  131. #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
  132. #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
  133. #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
  134. #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
  135. #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
  136. #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
  137. #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
  138. #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
  139. /*
  140. * NOR FLASH on the Local Bus
  141. */
  142. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  143. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  144. #define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of FLASH */
  145. #define CONFIG_SYS_FLASH_SIZE 0x00400000 /* max flash size */
  146. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  147. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  148. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
  149. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
  150. #undef CONFIG_SYS_FLASH_CHECKSUM
  151. /*
  152. * NAND FLASH
  153. * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
  154. */
  155. #define CONFIG_CMD_NAND
  156. #define CONFIG_NAND_MPC5121_NFC
  157. #define CONFIG_SYS_NAND_BASE 0x40000000
  158. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  159. #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
  160. /*
  161. * Configuration parameters for MPC5121 NAND driver
  162. */
  163. #define CONFIG_FSL_NFC_WIDTH 1
  164. #define CONFIG_FSL_NFC_WRITE_SIZE 2048
  165. #define CONFIG_FSL_NFC_SPARE_SIZE 64
  166. #define CONFIG_FSL_NFC_CHIPS 1
  167. #define CONFIG_SYS_SRAM_BASE 0x30000000
  168. #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
  169. /* ALE active low, data size 4bytes */
  170. #define CONFIG_SYS_CS0_CFG 0x05051150
  171. /* Use not alternative CS timing */
  172. #define CONFIG_SYS_CS_ALETIMING 0x00000000
  173. /* ALE active low, data size 4bytes */
  174. #define CONFIG_SYS_CS1_CFG 0x1f1f3090
  175. #define CONFIG_SYS_VPC3_BASE 0x82000000 /* start of VPC3 space */
  176. #define CONFIG_SYS_VPC3_SIZE 0x00010000 /* max VPC3 size */
  177. /* Use SRAM for initial stack */
  178. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM addr */
  179. #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
  180. #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
  181. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  182. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  183. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */
  184. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Monitor length */
  185. #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Malloc size */
  186. /*
  187. * Serial Port
  188. */
  189. #define CONFIG_CONS_INDEX 1
  190. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  191. /*
  192. * Serial console configuration
  193. */
  194. #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
  195. #if CONFIG_PSC_CONSOLE != 3
  196. #error CONFIG_PSC_CONSOLE must be 3
  197. #endif
  198. #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
  199. #define CONFIG_SYS_BAUDRATE_TABLE \
  200. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  201. #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
  202. #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
  203. #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
  204. #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
  205. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  206. /* Use the HUSH parser */
  207. #define CONFIG_SYS_HUSH_PARSER
  208. #ifdef CONFIG_SYS_HUSH_PARSER
  209. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  210. #endif
  211. /* I2C */
  212. #define CONFIG_HARD_I2C /* I2C with hardware support */
  213. #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
  214. #define CONFIG_I2C_MULTI_BUS
  215. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
  216. #define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
  217. /*
  218. * IIM - IC Identification Module
  219. */
  220. #undef CONFIG_IIM
  221. /*
  222. * EEPROM configuration
  223. */
  224. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
  225. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
  226. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
  227. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
  228. #define CONFIG_SYS_EEPROM_WREN /* Use EEPROM write protect */
  229. /*
  230. * Ethernet configuration
  231. */
  232. #define CONFIG_MPC512x_FEC 1
  233. #define CONFIG_NET_MULTI
  234. #define CONFIG_PHY_ADDR 0x1
  235. #define CONFIG_MII 1 /* MII PHY management */
  236. #define CONFIG_FEC_AN_TIMEOUT 1
  237. #define CONFIG_HAS_ETH0
  238. /*
  239. * Configure on-board RTC
  240. */
  241. #define CONFIG_SYS_RTC_BUS_NUM 0x01
  242. #define CONFIG_SYS_I2C_RTC_ADDR 0x32
  243. #define CONFIG_RTC_RX8025
  244. /*
  245. * Environment
  246. */
  247. #define CONFIG_ENV_IS_IN_EEPROM /* Store env in I2C EEPROM */
  248. #define CONFIG_ENV_SIZE 0x1000
  249. #define CONFIG_ENV_OFFSET 0x0000 /* environment starts here */
  250. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  251. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  252. #include <config_cmd_default.h>
  253. #define CONFIG_CMD_ASKENV
  254. #define CONFIG_CMD_DHCP
  255. #define CONFIG_CMD_I2C
  256. #define CONFIG_CMD_MII
  257. #define CONFIG_CMD_NFS
  258. #define CONFIG_CMD_PING
  259. #define CONFIG_CMD_REGINFO
  260. #define CONFIG_CMD_EEPROM
  261. #define CONFIG_CMD_DATE
  262. #undef CONFIG_CMD_FUSE
  263. #undef CONFIG_CMD_IDE
  264. #undef CONFIG_CMD_EXT2
  265. #define CONFIG_CMD_FAT
  266. #define CONFIG_CMD_JFFS2
  267. #define CONFIG_CMD_ELF
  268. #define CONFIG_DOS_PARTITION
  269. /*
  270. * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
  271. * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
  272. * to 0xFFFF, watchdog timeouts after about 64s. For details refer
  273. * to chapter 36 of the MPC5121e Reference Manual.
  274. */
  275. /* #define CONFIG_WATCHDOG */ /* enable watchdog */
  276. #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
  277. /*
  278. * Miscellaneous configurable options
  279. */
  280. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  281. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  282. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  283. #ifdef CONFIG_CMD_KGDB
  284. # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  285. #else
  286. # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  287. #endif
  288. /* Print Buffer Size */
  289. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  290. sizeof(CONFIG_SYS_PROMPT) + 16)
  291. /* max number of command args */
  292. #define CONFIG_SYS_MAXARGS 32
  293. /* Boot Argument Buffer Size */
  294. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  295. #define CONFIG_SYS_HZ 1000
  296. /*
  297. * For booting Linux, the board info and command line data
  298. * have to be in the first 8 MB of memory, since this is
  299. * the maximum mapped by the Linux kernel during initialization.
  300. */
  301. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */
  302. /* Cache Configuration */
  303. #define CONFIG_SYS_DCACHE_SIZE 32768
  304. #define CONFIG_SYS_CACHELINE_SIZE 32
  305. #ifdef CONFIG_CMD_KGDB
  306. #define CONFIG_SYS_CACHELINE_SHIFT 5
  307. #endif
  308. #define CONFIG_SYS_HID0_INIT 0x000000000
  309. #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
  310. #define CONFIG_SYS_HID2 HID2_HBE
  311. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  312. /*
  313. * Internal Definitions
  314. *
  315. * Boot Flags
  316. */
  317. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  318. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  319. #ifdef CONFIG_CMD_KGDB
  320. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  321. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  322. #endif
  323. /*
  324. * Environment Configuration
  325. */
  326. #define CONFIG_TIMESTAMP
  327. #define CONFIG_HOSTNAME mecp512x
  328. #define CONFIG_BOOTFILE /tftpboot/mecp512x/uImage
  329. #define CONFIG_ROOTPATH /tftpboot/mecp512x/target_root
  330. #define CONFIG_LOADADDR 400000 /* def. location for tftp and bootm */
  331. #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
  332. #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
  333. #define CONFIG_PREBOOT "echo;" \
  334. "echo Welcome to MECP5123" \
  335. "echo"
  336. #define CONFIG_EXTRA_ENV_SETTINGS \
  337. "u-boot_addr_r=200000\0" \
  338. "kernel_addr_r=600000\0" \
  339. "fdt_addr_r=880000\0" \
  340. "ramdisk_addr_r=900000\0" \
  341. "u-boot_addr=FFF00000\0" \
  342. "kernel_addr=FFC40000\0" \
  343. "fdt_addr=FFEC0000\0" \
  344. "ramdisk_addr=FC040000\0" \
  345. "ramdiskfile=/tftpboot/mecp512x/uRamdisk\0" \
  346. "u-boot=/tftpboot/mecp512x/u-boot.bin\0" \
  347. "bootfile=/tftpboot/mecp512x/uImage\0" \
  348. "fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0" \
  349. "rootpath=/tftpboot/mecp512x/target_root\n" \
  350. "netdev=eth0\0" \
  351. "consdev=ttyPSC0\0" \
  352. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  353. "nfsroot=${serverip}:${rootpath}\0" \
  354. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  355. "addip=setenv bootargs ${bootargs} " \
  356. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  357. ":${hostname}:${netdev}:off panic=1\0" \
  358. "addtty=setenv bootargs ${bootargs} " \
  359. "console=${consdev},${baudrate}\0" \
  360. "flash_nfs=run nfsargs addip addtty;" \
  361. "bootm ${kernel_addr} - ${fdt_addr}\0" \
  362. "flash_self=run ramargs addip addtty;" \
  363. "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
  364. "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
  365. "tftp ${fdt_addr_r} ${fdtfile};" \
  366. "run nfsargs addip addtty;" \
  367. "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  368. "net_self=tftp ${kernel_addr_r} ${bootfile};" \
  369. "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
  370. "tftp ${fdt_addr_r} ${fdtfile};" \
  371. "run ramargs addip addtty;" \
  372. "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
  373. "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
  374. "update=protect off ${u-boot_addr} +${filesize};" \
  375. "era ${u-boot_addr} +${filesize};" \
  376. "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
  377. "upd=run load update\0" \
  378. ""
  379. #define CONFIG_BOOTCOMMAND "run flash_self"
  380. #define CONFIG_OF_LIBFDT
  381. #define CONFIG_OF_BOARD_SETUP
  382. #define OF_CPU "PowerPC,5121@0"
  383. #define OF_SOC_COMPAT "fsl,mpc5121-immr"
  384. #define OF_TBCLK (bd->bi_busfreq / 4)
  385. #define OF_STDOUT_PATH "/soc@80000000/serial@11300"
  386. #endif /* __CONFIG_H */