kilauea.h 26 KB

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  1. /*
  2. * Copyright (c) 2008 Nuovation System Designs, LLC
  3. * Grant Erickson <gerickson@nuovations.com>
  4. *
  5. * (C) Copyright 2007
  6. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. /************************************************************************
  27. * kilauea.h - configuration for AMCC Kilauea (405EX)
  28. ***********************************************************************/
  29. #ifndef __CONFIG_H
  30. #define __CONFIG_H
  31. /*-----------------------------------------------------------------------
  32. * High Level Configuration Options
  33. *----------------------------------------------------------------------*/
  34. #define CONFIG_KILAUEA 1 /* Board is Kilauea */
  35. #define CONFIG_4xx 1 /* ... PPC4xx family */
  36. #define CONFIG_405EX 1 /* Specifc 405EX support*/
  37. #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
  38. /*
  39. * Include common defines/options for all AMCC eval boards
  40. */
  41. #define CONFIG_HOSTNAME kilauea
  42. #include "amcc-common.h"
  43. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  44. #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
  45. #define CONFIG_BOARD_EMAC_COUNT
  46. /*-----------------------------------------------------------------------
  47. * Base addresses -- Note these are effective addresses where the
  48. * actual resources get mapped (not physical addresses)
  49. *----------------------------------------------------------------------*/
  50. #define CONFIG_SYS_FLASH_BASE 0xFC000000
  51. #define CONFIG_SYS_NAND_ADDR 0xF8000000
  52. #define CONFIG_SYS_FPGA_BASE 0xF0000000
  53. #define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
  54. /*-----------------------------------------------------------------------
  55. * Initial RAM & Stack Pointer Configuration Options
  56. *
  57. * There are traditionally three options for the primordial
  58. * (i.e. initial) stack usage on the 405-series:
  59. *
  60. * 1) On-chip Memory (OCM) (i.e. SRAM)
  61. * 2) Data cache
  62. * 3) SDRAM
  63. *
  64. * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
  65. * the latter of which is less than desireable since it requires
  66. * setting up the SDRAM and ECC in assembly code.
  67. *
  68. * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
  69. * select on the External Bus Controller (EBC) and then select a
  70. * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
  71. * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
  72. * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
  73. * physical SDRAM to use (3).
  74. *-----------------------------------------------------------------------*/
  75. #define CONFIG_SYS_INIT_DCACHE_CS 4
  76. #if defined(CONFIG_SYS_INIT_DCACHE_CS)
  77. #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
  78. #else
  79. #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
  80. #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
  81. #define CONFIG_SYS_INIT_RAM_END (4 << 10) /* 4 KiB */
  82. #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
  83. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  84. /*
  85. * If the data cache is being used for the primordial stack and global
  86. * data area, the POST word must be placed somewhere else. The General
  87. * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
  88. * its compare and mask register contents across reset, so it is used
  89. * for the POST word.
  90. */
  91. #if defined(CONFIG_SYS_INIT_DCACHE_CS)
  92. # define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  93. # define CONFIG_SYS_POST_ALT_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
  94. #else
  95. # define CONFIG_SYS_INIT_EXTRA_SIZE 16
  96. # define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
  97. # define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 4)
  98. # define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
  99. #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
  100. /*-----------------------------------------------------------------------
  101. * Serial Port
  102. *----------------------------------------------------------------------*/
  103. #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
  104. /* define this if you want console on UART1 */
  105. #undef CONFIG_UART1_CONSOLE
  106. /*-----------------------------------------------------------------------
  107. * Environment
  108. *----------------------------------------------------------------------*/
  109. #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  110. #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  111. #else
  112. #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
  113. #define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
  114. #endif
  115. /*-----------------------------------------------------------------------
  116. * FLASH related
  117. *----------------------------------------------------------------------*/
  118. #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  119. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  120. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
  121. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  122. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
  123. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  124. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  125. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
  126. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  127. #ifdef CONFIG_ENV_IS_IN_FLASH
  128. #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
  129. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
  130. #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  131. /* Address and size of Redundant Environment Sector */
  132. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
  133. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  134. #endif /* CONFIG_ENV_IS_IN_FLASH */
  135. /*
  136. * IPL (Initial Program Loader, integrated inside CPU)
  137. * Will load first 4k from NAND (SPL) into cache and execute it from there.
  138. *
  139. * SPL (Secondary Program Loader)
  140. * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
  141. * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
  142. * controller and the NAND controller so that the special U-Boot image can be
  143. * loaded from NAND to SDRAM.
  144. *
  145. * NUB (NAND U-Boot)
  146. * This NAND U-Boot (NUB) is a special U-Boot version which can be started
  147. * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
  148. *
  149. * On 405EX the SPL is copied to SDRAM before the NAND controller is
  150. * set up. While still running from location 0xfffff000...0xffffffff the
  151. * NAND controller cannot be accessed since it is attached to CS0 too.
  152. */
  153. #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
  154. #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
  155. #define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
  156. #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
  157. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
  158. #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
  159. /*
  160. * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
  161. */
  162. #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
  163. #define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
  164. /*
  165. * Now the NAND chip has to be defined (no autodetection used!)
  166. */
  167. #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
  168. #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
  169. #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
  170. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
  171. #define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
  172. #define CONFIG_SYS_NAND_ECCSIZE 256
  173. #define CONFIG_SYS_NAND_ECCBYTES 3
  174. #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
  175. #define CONFIG_SYS_NAND_OOBSIZE 16
  176. #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
  177. #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
  178. #ifdef CONFIG_ENV_IS_IN_NAND
  179. /*
  180. * For NAND booting the environment is embedded in the U-Boot image. Please take
  181. * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
  182. */
  183. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  184. #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
  185. #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
  186. #endif
  187. /*-----------------------------------------------------------------------
  188. * NAND FLASH
  189. *----------------------------------------------------------------------*/
  190. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  191. #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
  192. #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
  193. /*-----------------------------------------------------------------------
  194. * DDR SDRAM
  195. *----------------------------------------------------------------------*/
  196. #define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
  197. /*
  198. * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
  199. *
  200. * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
  201. * SDRAM Controller DDR autocalibration values and takes a lot longer
  202. * to run than Method_B.
  203. * (See the Method_A and Method_B algorithm discription in the file:
  204. * cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
  205. * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
  206. *
  207. * DDR Autocalibration Method_B is the default.
  208. */
  209. #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  210. #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
  211. #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
  212. #undef CONFIG_PPC4xx_DDR_METHOD_A
  213. #endif
  214. #define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
  215. /* DDR1/2 SDRAM Device Control Register Data Values */
  216. #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
  217. SDRAM_RXBAS_SDSZ_256MB | \
  218. SDRAM_RXBAS_SDAM_MODE7 | \
  219. SDRAM_RXBAS_SDBE_ENABLE)
  220. #define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
  221. #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
  222. #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
  223. #define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
  224. SDRAM_MCOPT1_8_BANKS | \
  225. SDRAM_MCOPT1_DDR2_TYPE | \
  226. SDRAM_MCOPT1_QDEP | \
  227. SDRAM_MCOPT1_DCOO_DISABLED)
  228. #define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
  229. #define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
  230. SDRAM_MODT_EB0R_ENABLE)
  231. #define CONFIG_SYS_SDRAM0_MODT1 0x00000000
  232. #define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
  233. SDRAM_CODT_CKLZ_36OHM | \
  234. SDRAM_CODT_DQS_1_8_V_DDR2 | \
  235. SDRAM_CODT_IO_NMODE)
  236. #define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
  237. #define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
  238. SDRAM_INITPLR_IMWT_ENCODE(80) | \
  239. SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
  240. #define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
  241. SDRAM_INITPLR_IMWT_ENCODE(3) | \
  242. SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
  243. SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
  244. SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
  245. #define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
  246. SDRAM_INITPLR_IMWT_ENCODE(2) | \
  247. SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
  248. SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
  249. SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
  250. #define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
  251. SDRAM_INITPLR_IMWT_ENCODE(2) | \
  252. SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
  253. SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
  254. SDRAM_INITPLR_IMA_ENCODE(0))
  255. #define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
  256. SDRAM_INITPLR_IMWT_ENCODE(2) | \
  257. SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
  258. SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
  259. SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
  260. JEDEC_MA_EMR_RTT_75OHM))
  261. #define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
  262. SDRAM_INITPLR_IMWT_ENCODE(2) | \
  263. SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
  264. SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
  265. SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
  266. JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
  267. JEDEC_MA_MR_BLEN_4 | \
  268. JEDEC_MA_MR_DLL_RESET))
  269. #define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
  270. SDRAM_INITPLR_IMWT_ENCODE(3) | \
  271. SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
  272. SDRAM_INITPLR_IBA_ENCODE(0x0) | \
  273. SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
  274. #define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
  275. SDRAM_INITPLR_IMWT_ENCODE(26) | \
  276. SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
  277. #define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
  278. SDRAM_INITPLR_IMWT_ENCODE(26) | \
  279. SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
  280. #define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
  281. SDRAM_INITPLR_IMWT_ENCODE(26) | \
  282. SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
  283. #define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
  284. SDRAM_INITPLR_IMWT_ENCODE(26) | \
  285. SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
  286. #define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
  287. SDRAM_INITPLR_IMWT_ENCODE(2) | \
  288. SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
  289. SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
  290. SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
  291. JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
  292. JEDEC_MA_MR_BLEN_4))
  293. #define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
  294. SDRAM_INITPLR_IMWT_ENCODE(2) | \
  295. SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
  296. SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
  297. SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
  298. JEDEC_MA_EMR_RDQS_DISABLE | \
  299. JEDEC_MA_EMR_DQS_DISABLE | \
  300. JEDEC_MA_EMR_RTT_DISABLED | \
  301. JEDEC_MA_EMR_ODS_NORMAL))
  302. #define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
  303. SDRAM_INITPLR_IMWT_ENCODE(2) | \
  304. SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
  305. SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
  306. SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
  307. JEDEC_MA_EMR_RDQS_DISABLE | \
  308. JEDEC_MA_EMR_DQS_DISABLE | \
  309. JEDEC_MA_EMR_RTT_DISABLED | \
  310. JEDEC_MA_EMR_ODS_NORMAL))
  311. #define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
  312. #define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
  313. #define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
  314. SDRAM_RQDC_RQFD_ENCODE(56))
  315. #define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
  316. #define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
  317. #define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
  318. SDRAM_DLCR_DLCS_CONT_DONE | \
  319. SDRAM_DLCR_DLCV_ENCODE(165))
  320. #define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
  321. #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
  322. #define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
  323. SDRAM_SDTR1_RTW_2_CLK | \
  324. SDRAM_SDTR1_RTRO_1_CLK)
  325. #define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
  326. SDRAM_SDTR2_WTR_2_CLK | \
  327. SDRAM_SDTR2_XSNR_32_CLK | \
  328. SDRAM_SDTR2_WPC_4_CLK | \
  329. SDRAM_SDTR2_RPC_2_CLK | \
  330. SDRAM_SDTR2_RP_3_CLK | \
  331. SDRAM_SDTR2_RRD_2_CLK)
  332. #define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \
  333. SDRAM_SDTR3_RC_ENCODE(11) | \
  334. SDRAM_SDTR3_XCS | \
  335. SDRAM_SDTR3_RFC_ENCODE(26))
  336. #define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
  337. SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
  338. SDRAM_MMODE_BLEN_4)
  339. #define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
  340. SDRAM_MEMODE_RTT_75OHM)
  341. /*-----------------------------------------------------------------------
  342. * I2C
  343. *----------------------------------------------------------------------*/
  344. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  345. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
  346. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  347. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  348. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  349. /* I2C bootstrap EEPROM */
  350. #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
  351. #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
  352. #define CONFIG_4xx_CONFIG_BLOCKSIZE 16
  353. /* Standard DTT sensor configuration */
  354. #define CONFIG_DTT_DS1775 1
  355. #define CONFIG_DTT_SENSORS { 0 }
  356. #define CONFIG_SYS_I2C_DTT_ADDR 0x48
  357. /* RTC configuration */
  358. #define CONFIG_RTC_DS1338 1
  359. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  360. /*-----------------------------------------------------------------------
  361. * Ethernet
  362. *----------------------------------------------------------------------*/
  363. #define CONFIG_M88E1111_PHY 1
  364. #define CONFIG_IBM_EMAC4_V4 1
  365. #define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
  366. #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
  367. #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
  368. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  369. #define CONFIG_HAS_ETH0 1
  370. #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
  371. #define CONFIG_PHY1_ADDR 2
  372. /* Debug messages for the DDR autocalibration */
  373. #define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
  374. /*
  375. * Default environment variables
  376. */
  377. #define CONFIG_EXTRA_ENV_SETTINGS \
  378. CONFIG_AMCC_DEF_ENV \
  379. CONFIG_AMCC_DEF_ENV_POWERPC \
  380. CONFIG_AMCC_DEF_ENV_PPC_OLD \
  381. CONFIG_AMCC_DEF_ENV_NOR_UPD \
  382. CONFIG_AMCC_DEF_ENV_NAND_UPD \
  383. "logversion=2\0" \
  384. "kernel_addr=fc000000\0" \
  385. "fdt_addr=fc1e0000\0" \
  386. "ramdisk_addr=fc200000\0" \
  387. "pciconfighost=1\0" \
  388. "pcie_mode=RP:RP\0" \
  389. ""
  390. /*
  391. * Commands additional to the ones defined in amcc-common.h
  392. */
  393. #define CONFIG_CMD_CHIP_CONFIG
  394. #define CONFIG_CMD_DATE
  395. #define CONFIG_CMD_LOG
  396. #define CONFIG_CMD_NAND
  397. #define CONFIG_CMD_PCI
  398. #define CONFIG_CMD_SNTP
  399. /*
  400. * Don't run the memory POST on the NAND-booting version. It will
  401. * overwrite part of the U-Boot image which is already loaded from NAND
  402. * to SDRAM.
  403. */
  404. #if defined(CONFIG_NAND_U_BOOT)
  405. #define CONFIG_SYS_POST_MEMORY_ON 0
  406. #else
  407. #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
  408. #endif
  409. /* POST support */
  410. #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
  411. CONFIG_SYS_POST_CPU | \
  412. CONFIG_SYS_POST_ETHER | \
  413. CONFIG_SYS_POST_I2C | \
  414. CONFIG_SYS_POST_MEMORY_ON | \
  415. CONFIG_SYS_POST_UART)
  416. /* Define here the base-addresses of the UARTs to test in POST */
  417. #define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE}
  418. #define CONFIG_LOGBUFFER
  419. #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
  420. #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
  421. /*-----------------------------------------------------------------------
  422. * PCI stuff
  423. *----------------------------------------------------------------------*/
  424. #define CONFIG_PCI /* include pci support */
  425. #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
  426. #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
  427. #define CONFIG_PCI_CONFIG_HOST_BRIDGE
  428. /*-----------------------------------------------------------------------
  429. * PCIe stuff
  430. *----------------------------------------------------------------------*/
  431. #define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
  432. #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
  433. #define CONFIG_SYS_PCIE0_CFGBASE 0xa0000000 /* remote access */
  434. #define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000 /* local access */
  435. #define CONFIG_SYS_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
  436. #define CONFIG_SYS_PCIE1_CFGBASE 0xc0000000 /* remote access */
  437. #define CONFIG_SYS_PCIE1_XCFGBASE 0xd0000000 /* local access */
  438. #define CONFIG_SYS_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
  439. #define CONFIG_SYS_PCIE0_UTLBASE 0xef502000
  440. #define CONFIG_SYS_PCIE1_UTLBASE 0xef503000
  441. /* base address of inbound PCIe window */
  442. #define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
  443. /*-----------------------------------------------------------------------
  444. * External Bus Controller (EBC) Setup
  445. *----------------------------------------------------------------------*/
  446. #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  447. /* booting from NAND, so NAND chips select has to be on CS 0 */
  448. #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
  449. /* Memory Bank 1 (NOR-FLASH) initialization */
  450. #define CONFIG_SYS_EBC_PB1AP 0x05806500
  451. #define CONFIG_SYS_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
  452. /* Memory Bank 0 (NAND-FLASH) initialization */
  453. #define CONFIG_SYS_EBC_PB0AP 0x018003c0
  454. #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1e000)
  455. #else
  456. #define CONFIG_SYS_NAND_CS 1 /* NAND chip connected to CSx */
  457. /* Memory Bank 0 (NOR-FLASH) initialization */
  458. #define CONFIG_SYS_EBC_PB0AP 0x05806500
  459. #define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
  460. /* Memory Bank 1 (NAND-FLASH) initialization */
  461. #define CONFIG_SYS_EBC_PB1AP 0x018003c0
  462. #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_ADDR | 0x1e000)
  463. #endif
  464. /* Memory Bank 2 (FPGA) initialization */
  465. #define CONFIG_SYS_EBC_PB2AP 0x9400C800
  466. #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x18000)
  467. #define CONFIG_SYS_EBC_CFG 0x7FC00000 /* EBC0_CFG */
  468. /*-----------------------------------------------------------------------
  469. * GPIO Setup
  470. *----------------------------------------------------------------------*/
  471. #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
  472. { \
  473. /* GPIO Core 0 */ \
  474. {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
  475. {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
  476. {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
  477. {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
  478. {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
  479. {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
  480. {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
  481. {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
  482. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
  483. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
  484. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
  485. {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
  486. {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
  487. {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
  488. {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
  489. {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
  490. {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
  491. {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
  492. {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
  493. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
  494. {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
  495. {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
  496. {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
  497. {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
  498. {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
  499. {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
  500. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
  501. {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
  502. {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO28 */ \
  503. {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \
  504. {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \
  505. {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \
  506. } \
  507. }
  508. /*-----------------------------------------------------------------------
  509. * Some Kilauea stuff..., mainly fpga registers
  510. */
  511. #define CONFIG_SYS_FPGA_REG_BASE CONFIG_SYS_FPGA_BASE
  512. #define CONFIG_SYS_FPGA_FIFO_BASE (in32(CONFIG_SYS_FPGA_BASE) | (1 << 10))
  513. /* interrupt */
  514. #define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT 0x80000000
  515. #define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT 0x40000000
  516. #define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT 0x20000000
  517. #define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT 0x10000000
  518. #define CONFIG_SYS_FPGA_PHY0_INT 0x08000000
  519. #define CONFIG_SYS_FPGA_PHY1_INT 0x04000000
  520. #define CONFIG_SYS_FPGA_SLIC0_INT 0x02000000
  521. #define CONFIG_SYS_FPGA_SLIC1_INT 0x01000000
  522. /* DPRAM setting */
  523. /* 00: 32B; 01: 64B; 10: 128B; 11: 256B */
  524. #define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE 0x00400000 /* 64 B */
  525. #define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE 0x00100000 /* 64 B */
  526. #define CONFIG_SYS_FPGA_DPRAM_RW_TYPE 0x00080000
  527. #define CONFIG_SYS_FPGA_DPRAM_RST 0x00040000
  528. #define CONFIG_SYS_FPGA_UART0_FO 0x00020000
  529. #define CONFIG_SYS_FPGA_UART1_FO 0x00010000
  530. /* loopback */
  531. #define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK 0x00004000
  532. #define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK 0x00008000
  533. #define CONFIG_SYS_FPGA_SLIC0_ENABLE 0x00002000
  534. #define CONFIG_SYS_FPGA_SLIC1_ENABLE 0x00001000
  535. #define CONFIG_SYS_FPGA_SLIC0_CS 0x00000800
  536. #define CONFIG_SYS_FPGA_SLIC1_CS 0x00000400
  537. #define CONFIG_SYS_FPGA_USER_LED0 0x00000200
  538. #define CONFIG_SYS_FPGA_USER_LED1 0x00000100
  539. #endif /* __CONFIG_H */