devkit8000.h 9.5 KB

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  1. /*
  2. * (C) Copyright 2006-2008
  3. * Texas Instruments.
  4. * Richard Woodruff <r-woodruff2@ti.com>
  5. * Syed Mohammed Khasim <x0khasim@ti.com>
  6. *
  7. * (C) Copyright 2009
  8. * Frederik Kriewitz <frederik@kriewitz.eu>
  9. *
  10. * Configuration settings for the DevKit8000 board.
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. #ifndef __CONFIG_H
  31. #define __CONFIG_H
  32. /* High Level Configuration Options */
  33. #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
  34. #define CONFIG_OMAP 1 /* in a TI OMAP core */
  35. #define CONFIG_OMAP34XX 1 /* which is a 34XX */
  36. #define CONFIG_OMAP3430 1 /* which is in a 3430 */
  37. #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
  38. #include <asm/arch/cpu.h> /* get chip and board defs */
  39. #include <asm/arch/omap3.h>
  40. /* Display CPU and Board information */
  41. #define CONFIG_DISPLAY_CPUINFO 1
  42. #define CONFIG_DISPLAY_BOARDINFO 1
  43. /* Clock Defines */
  44. #define V_OSCK 26000000 /* Clock output from T2 */
  45. #define V_SCLK (V_OSCK >> 1)
  46. #undef CONFIG_USE_IRQ /* no support for IRQs */
  47. #define CONFIG_MISC_INIT_R
  48. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  49. #define CONFIG_SETUP_MEMORY_TAGS 1
  50. #define CONFIG_INITRD_TAG 1
  51. #define CONFIG_REVISION_TAG 1
  52. /* Size of malloc() pool */
  53. #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
  54. /* Sector */
  55. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
  56. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
  57. /* initial data */
  58. /* Hardware drivers */
  59. /* DDR - I use Micron DDR */
  60. #define CONFIG_OMAP3_MICRON_DDR 1
  61. /* DM9000 */
  62. #define CONFIG_NET_MULTI 1
  63. #define CONFIG_NET_RETRY_COUNT 20
  64. #define CONFIG_DRIVER_DM9000 1
  65. #define CONFIG_DM9000_BASE 0x2c000000
  66. #define DM9000_IO CONFIG_DM9000_BASE
  67. #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
  68. #define CONFIG_DM9000_USE_16BIT 1
  69. #define CONFIG_DM9000_NO_SROM 1
  70. #undef CONFIG_DM9000_DEBUG
  71. /* NS16550 Configuration */
  72. #define CONFIG_SYS_NS16550
  73. #define CONFIG_SYS_NS16550_SERIAL
  74. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  75. #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  76. /* select serial console configuration */
  77. #define CONFIG_CONS_INDEX 3
  78. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  79. #define CONFIG_SERIAL3 3
  80. #define CONFIG_BAUDRATE 115200
  81. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  82. 115200}
  83. /* MMC */
  84. #define CONFIG_MMC 1
  85. #define CONFIG_OMAP3_MMC 1
  86. #define CONFIG_DOS_PARTITION 1
  87. /* I2C */
  88. #define CONFIG_HARD_I2C 1
  89. #define CONFIG_SYS_I2C_SPEED 100000
  90. #define CONFIG_SYS_I2C_SLAVE 1
  91. #define CONFIG_SYS_I2C_BUS 0
  92. #define CONFIG_SYS_I2C_BUS_SELECT 1
  93. #define CONFIG_DRIVER_OMAP34XX_I2C 1
  94. /* TWL4030 */
  95. #define CONFIG_TWL4030_POWER 1
  96. #define CONFIG_TWL4030_LED 1
  97. /* Board NAND Info */
  98. #define CONFIG_SYS_NO_FLASH /* no NOR flash */
  99. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  100. #define MTDIDS_DEFAULT "nand0=nand"
  101. #define MTDPARTS_DEFAULT "mtdparts=nand:" \
  102. "512k(x-loader)," \
  103. "1920k(u-boot)," \
  104. "128k(u-boot-env)," \
  105. "4m(kernel)," \
  106. "-(fs)"
  107. #define CONFIG_NAND_OMAP_GPMC
  108. #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  109. /* to access nand */
  110. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  111. /* to access nand at */
  112. /* CS0 */
  113. #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
  114. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  115. /* devices */
  116. #define CONFIG_JFFS2_NAND
  117. /* nand device jffs2 lives on */
  118. #define CONFIG_JFFS2_DEV "nand0"
  119. /* start of jffs2 partition */
  120. #define CONFIG_JFFS2_PART_OFFSET 0x680000
  121. #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
  122. /* partition */
  123. /* commands to include */
  124. #include <config_cmd_default.h>
  125. #define CONFIG_CMD_DHCP /* DHCP support */
  126. #define CONFIG_CMD_EXT2 /* EXT2 Support */
  127. #define CONFIG_CMD_FAT /* FAT support */
  128. #define CONFIG_CMD_I2C /* I2C serial bus support */
  129. #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
  130. #define CONFIG_CMD_MMC /* MMC support */
  131. #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
  132. #define CONFIG_CMD_NAND /* NAND support */
  133. #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
  134. #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
  135. #undef CONFIG_CMD_IMI /* iminfo */
  136. /* BOOTP/DHCP options */
  137. #define CONFIG_BOOTP_SUBNETMASK
  138. #define CONFIG_BOOTP_GATEWAY
  139. #define CONFIG_BOOTP_HOSTNAME
  140. #define CONFIG_BOOTP_NISDOMAIN
  141. #define CONFIG_BOOTP_BOOTPATH
  142. #define CONFIG_BOOTP_BOOTFILESIZE
  143. #define CONFIG_BOOTP_DNS
  144. #define CONFIG_BOOTP_DNS2
  145. #define CONFIG_BOOTP_SEND_HOSTNAME
  146. #define CONFIG_BOOTP_NTPSERVER
  147. #define CONFIG_BOOTP_TIMEOFFSET
  148. #undef CONFIG_BOOTP_VENDOREX
  149. /* Environment information */
  150. #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
  151. #define CONFIG_BOOTDELAY 3
  152. #define CONFIG_EXTRA_ENV_SETTINGS \
  153. "loadaddr=0x82000000\0" \
  154. "console=ttyS2,115200n8\0" \
  155. "vram=12M\0" \
  156. "dvimode=1024x768MR-16@60\0" \
  157. "defaultdisplay=dvi\0" \
  158. "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
  159. "kernelopts=rw\0" \
  160. "commonargs=" \
  161. "setenv bootargs console=${console} " \
  162. "vram=${vram} " \
  163. "omapfb.mode=dvi:${dvimode} " \
  164. "omapdss.def_disp=${defaultdisplay}\0" \
  165. "mmcargs=" \
  166. "run commonargs; " \
  167. "setenv bootargs ${bootargs} " \
  168. "root=/dev/mmcblk0p2 " \
  169. "${kernelopts}\0" \
  170. "nandargs=" \
  171. "run commonargs; " \
  172. "setenv bootargs ${bootargs} " \
  173. "omapfb.mode=dvi:${dvimode} " \
  174. "omapdss.def_disp=${defaultdisplay} " \
  175. "root=/dev/mtdblock4 " \
  176. "rootfstype=jffs2 " \
  177. "${kernelopts}\0" \
  178. "netargs=" \
  179. "run commonargs; " \
  180. "setenv bootargs ${bootargs} " \
  181. "root=/dev/nfs " \
  182. "nfsroot=${serverip}:${rootpath},${nfsopts} " \
  183. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
  184. "${kernelopts} " \
  185. "dnsip1=${dnsip} " \
  186. "dnsip2=${dnsip2}\0" \
  187. "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
  188. "bootscript=echo Running bootscript from mmc ...; " \
  189. "source ${loadaddr}\0" \
  190. "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
  191. "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
  192. "mmcboot=echo Booting from mmc ...; " \
  193. "run mmcargs; " \
  194. "bootm ${loadaddr}\0" \
  195. "nandboot=echo Booting from nand ...; " \
  196. "run nandargs; " \
  197. "nand read ${loadaddr} 280000 400000; " \
  198. "bootm ${loadaddr}\0" \
  199. "netboot=echo Booting from network ...; " \
  200. "dhcp ${loadaddr}; " \
  201. "run netargs; " \
  202. "bootm ${loadaddr}\0" \
  203. "autoboot=if mmc init 0; then " \
  204. "if run loadbootscript; then " \
  205. "run bootscript; " \
  206. "else " \
  207. "if run loaduimage; then " \
  208. "run mmcboot; " \
  209. "else run nandboot; " \
  210. "fi; " \
  211. "fi; " \
  212. "else run nandboot; fi\0"
  213. #define CONFIG_BOOTCOMMAND "run autoboot"
  214. /* Miscellaneous configurable options */
  215. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  216. #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  217. #define CONFIG_AUTO_COMPLETE 1
  218. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  219. #define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
  220. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  221. /* Print Buffer Size */
  222. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  223. sizeof(CONFIG_SYS_PROMPT) + 16)
  224. #define CONFIG_SYS_MAXARGS 128 /* max number of command args */
  225. /* Boot Argument Buffer Size */
  226. #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
  227. #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
  228. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
  229. 0x01000000) /* 16MB */
  230. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
  231. /*
  232. * OMAP3 has 12 GP timers, they can be driven by the system clock
  233. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  234. * This rate is divided by a local divisor.
  235. */
  236. #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  237. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  238. #define CONFIG_SYS_HZ 1000
  239. /* The stack sizes are set up in start.S using the settings below */
  240. #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
  241. #ifdef CONFIG_USE_IRQ
  242. #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
  243. #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
  244. #endif
  245. /* Physical Memory Map */
  246. #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  247. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  248. #define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */
  249. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  250. /* SDRAM Bank Allocation method */
  251. #define SDRC_R_B_C 1
  252. /* NAND and environment organization */
  253. #define PISMO1_NAND_SIZE GPMC_SIZE_128M
  254. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  255. #define CONFIG_ENV_IS_IN_NAND 1
  256. #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
  257. #define CONFIG_ENV_OFFSET boot_flash_off
  258. #ifndef __ASSEMBLY__
  259. extern struct gpmc *gpmc_cfg;
  260. extern unsigned int boot_flash_base;
  261. extern volatile unsigned int boot_flash_env_addr;
  262. extern unsigned int boot_flash_off;
  263. extern unsigned int boot_flash_sec;
  264. extern unsigned int boot_flash_type;
  265. #endif
  266. #endif /* __CONFIG_H */