davinci_sonata.h 8.7 KB

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  1. /*
  2. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation; either version 2 of
  7. * the License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17. * MA 02111-1307 USA
  18. */
  19. #ifndef __CONFIG_H
  20. #define __CONFIG_H
  21. /*
  22. * Define this to make U-Boot skip low level initialization when loaded
  23. * by initial bootloader. Not required by NAND U-Boot version but IS
  24. * required for a NOR version used to burn the real NOR U-Boot into
  25. * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
  26. * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
  27. * NOR U-Boot is loaded directly from Flash so it must perform all the
  28. * low level initialization itself. NAND version is loaded by an initial
  29. * bootloader (UBL in TI-ese) that performs such an initialization so it's
  30. * skipped in NAND version. The third DaVinci boot mode loads a bootloader
  31. * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
  32. * performing low level init prior to loading. All that means we can NOT use
  33. * NAND version to put U-Boot into NOR because it doesn't have NOR support and
  34. * we can NOT use NOR version because it performs low level initialization
  35. * effectively destroying itself in DDR memory. That's why a separate NOR
  36. * version with this define is needed. It is loaded via UART, then one uses
  37. * it to somehow download a proper NOR version built WITHOUT this define to
  38. * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
  39. * NOR support into the initial bootloader so it won't be needed but DaVinci
  40. * static RAM might be too small for this (I have something like 2Kbytes left
  41. * as of now, without NOR support) so this might've not happened...
  42. *
  43. #define CONFIG_NOR_UART_BOOT
  44. */
  45. /*=======*/
  46. /* Board */
  47. /*=======*/
  48. #define SONATA_BOARD
  49. #define CONFIG_SYS_NAND_SMALLPAGE
  50. #define CONFIG_SYS_USE_NOR
  51. #define CONFIG_DISPLAY_CPUINFO
  52. /*===================*/
  53. /* SoC Configuration */
  54. /*===================*/
  55. #define CONFIG_ARM926EJS /* arm926ejs CPU core */
  56. #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
  57. #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
  58. #define CONFIG_SYS_HZ 1000
  59. #define CONFIG_SOC_DM644X
  60. /*====================================================*/
  61. /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
  62. /* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
  63. /*====================================================*/
  64. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  65. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  66. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
  67. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
  68. /*=============*/
  69. /* Memory Info */
  70. /*=============*/
  71. #define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
  72. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
  73. #define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
  74. #define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
  75. #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  76. #define CONFIG_STACKSIZE (256*1024) /* regular stack */
  77. #define PHYS_SDRAM_1 0x80000000 /* DDR Start */
  78. #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
  79. #define DDR_4BANKS /* 4-bank DDR2 (128MB) */
  80. /*====================*/
  81. /* Serial Driver info */
  82. /*====================*/
  83. #define CONFIG_SYS_NS16550
  84. #define CONFIG_SYS_NS16550_SERIAL
  85. #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
  86. #define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
  87. #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
  88. #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
  89. #define CONFIG_BAUDRATE 115200 /* Default baud rate */
  90. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  91. /*===================*/
  92. /* I2C Configuration */
  93. /*===================*/
  94. #define CONFIG_HARD_I2C
  95. #define CONFIG_DRIVER_DAVINCI_I2C
  96. #define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
  97. #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
  98. /*==================================*/
  99. /* Network & Ethernet Configuration */
  100. /*==================================*/
  101. #define CONFIG_DRIVER_TI_EMAC
  102. #define CONFIG_MII
  103. #define CONFIG_BOOTP_DEFAULT
  104. #define CONFIG_BOOTP_DNS
  105. #define CONFIG_BOOTP_DNS2
  106. #define CONFIG_BOOTP_SEND_HOSTNAME
  107. #define CONFIG_NET_RETRY_COUNT 10
  108. #define CONFIG_NET_MULTI
  109. /*=====================*/
  110. /* Flash & Environment */
  111. /*=====================*/
  112. #ifdef CONFIG_SYS_USE_NAND
  113. #define CONFIG_NAND_DAVINCI
  114. #undef CONFIG_ENV_IS_IN_FLASH
  115. #define CONFIG_SYS_NO_FLASH
  116. #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
  117. #define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */
  118. #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
  119. #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
  120. #define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
  121. #define CONFIG_SYS_NAND_BASE 0x02000000
  122. #define CONFIG_SYS_NAND_HW_ECC
  123. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  124. #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
  125. #define DEF_BOOTM ""
  126. #elif defined(CONFIG_SYS_USE_NOR)
  127. #ifdef CONFIG_NOR_UART_BOOT
  128. #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
  129. #define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
  130. #else
  131. #undef CONFIG_SKIP_LOWLEVEL_INIT
  132. #undef CONFIG_SKIP_RELOCATE_UBOOT
  133. #endif
  134. #define CONFIG_ENV_IS_IN_FLASH
  135. #undef CONFIG_SYS_NO_FLASH
  136. #define CONFIG_FLASH_CFI_DRIVER
  137. #define CONFIG_SYS_FLASH_CFI
  138. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
  139. #define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */
  140. #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*2)
  141. #define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
  142. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
  143. #define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
  144. #define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
  145. #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */
  146. #endif
  147. /*==============================*/
  148. /* U-Boot general configuration */
  149. /*==============================*/
  150. #undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
  151. #define CONFIG_MISC_INIT_R
  152. #undef CONFIG_BOOTDELAY
  153. #define CONFIG_BOOTFILE "uImage" /* Boot file name */
  154. #define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
  155. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  156. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
  157. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  158. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  159. #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
  160. #define CONFIG_VERSION_VARIABLE
  161. #define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
  162. #define CONFIG_SYS_HUSH_PARSER
  163. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  164. #define CONFIG_CMDLINE_EDITING
  165. #define CONFIG_SYS_LONGHELP
  166. #define CONFIG_CRC32_VERIFY
  167. #define CONFIG_MX_CYCLIC
  168. /*===================*/
  169. /* Linux Information */
  170. /*===================*/
  171. #define LINUX_BOOT_PARAM_ADDR 0x80000100
  172. #define CONFIG_CMDLINE_TAG
  173. #define CONFIG_SETUP_MEMORY_TAGS
  174. #define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
  175. #define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000"
  176. /*=================*/
  177. /* U-Boot commands */
  178. /*=================*/
  179. #include <config_cmd_default.h>
  180. #define CONFIG_CMD_ASKENV
  181. #define CONFIG_CMD_DHCP
  182. #define CONFIG_CMD_DIAG
  183. #define CONFIG_CMD_I2C
  184. #define CONFIG_CMD_MII
  185. #define CONFIG_CMD_PING
  186. #define CONFIG_CMD_SAVES
  187. #define CONFIG_CMD_EEPROM
  188. #undef CONFIG_CMD_BDI
  189. #undef CONFIG_CMD_FPGA
  190. #undef CONFIG_CMD_SETGETDCR
  191. #ifdef CONFIG_SYS_USE_NAND
  192. #undef CONFIG_CMD_FLASH
  193. #undef CONFIG_CMD_IMLS
  194. #define CONFIG_CMD_NAND
  195. #elif defined(CONFIG_SYS_USE_NOR)
  196. #define CONFIG_CMD_JFFS2
  197. #else
  198. #error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
  199. #endif
  200. /*=======================*/
  201. /* KGDB support (if any) */
  202. /*=======================*/
  203. #ifdef CONFIG_CMD_KGDB
  204. #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
  205. #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
  206. #endif
  207. #endif /* __CONFIG_H */