cpu9260.h 14 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stelian Pop <stelian.pop@leadtechdesign.com>
  4. * Lead Tech Design <www.leadtechdesign.com>
  5. * Ilko Iliev <www.ronetix.at>
  6. *
  7. * (C) Copyright 2009
  8. * Eric Benard <eric@eukrea.com>
  9. *
  10. * Configuration settings for the Eukrea CPU9260 board.
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. #ifndef __CONFIG_H
  31. #define __CONFIG_H
  32. #define CONFIG_DISPLAY_CPUINFO 1
  33. #define AT91_MAIN_CLOCK 18432000
  34. #define CONFIG_SYS_HZ 1000
  35. #define CONFIG_ARM926EJS 1
  36. #if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9260)
  37. #define CONFIG_CPU9260 1
  38. #elif defined(CONFIG_CPU9G20_128M) || defined(CONFIG_CPU9G20)
  39. #define CONFIG_CPU9G20 1
  40. #endif
  41. #if defined(CONFIG_CPU9G20)
  42. #define CONFIG_AT91SAM9G20 1
  43. #elif defined(CONFIG_CPU9260)
  44. #define CONFIG_AT91SAM9260 1
  45. #else
  46. #error "Unknown board"
  47. #endif
  48. #define CONFIG_ARCH_CPU_INIT
  49. #undef CONFIG_USE_IRQ
  50. #define CONFIG_CMDLINE_TAG 1
  51. #define CONFIG_SETUP_MEMORY_TAGS 1
  52. #define CONFIG_INITRD_TAG 1
  53. /* clocks */
  54. #if defined(CONFIG_CPU9G20)
  55. #define MASTER_PLL_DIV 0x01
  56. #define MASTER_PLL_MUL 0x2B
  57. #elif defined(CONFIG_CPU9260)
  58. #define MASTER_PLL_DIV 0x09
  59. #define MASTER_PLL_MUL 0x61
  60. #endif
  61. /* CKGR_MOR - enable main osc. */
  62. #define CONFIG_SYS_MOR_VAL \
  63. (AT91_PMC_MOSCEN | \
  64. (255 << 8)) /* Main Oscillator Start-up Time */
  65. #if defined(CONFIG_CPU9G20)
  66. #define CONFIG_SYS_PLLAR_VAL \
  67. (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
  68. ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  69. #elif defined(CONFIG_CPU9260)
  70. #define CONFIG_SYS_PLLAR_VAL \
  71. (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
  72. AT91_PMC_OUT | \
  73. ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  74. #endif
  75. #if defined(CONFIG_CPU9G20)
  76. #define CONFIG_SYS_MCKR1_VAL \
  77. (AT91_PMC_CSS_PLLA | \
  78. AT91_PMC_PRES_1 | \
  79. AT91SAM9_PMC_MDIV_6 | \
  80. AT91_PMC_PDIV_2)
  81. #define CONFIG_SYS_MCKR2_VAL \
  82. CONFIG_SYS_MCKR1_VAL
  83. #elif defined(CONFIG_CPU9260)
  84. #define CONFIG_SYS_MCKR1_VAL \
  85. (AT91_PMC_CSS_SLOW | \
  86. AT91_PMC_PRES_1 | \
  87. AT91SAM9_PMC_MDIV_2 | \
  88. AT91_PMC_PDIV_1)
  89. #define CONFIG_SYS_MCKR2_VAL \
  90. (AT91_PMC_CSS_PLLA | \
  91. AT91_PMC_PRES_1 | \
  92. AT91SAM9_PMC_MDIV_2 | \
  93. AT91_PMC_PDIV_1)
  94. #endif
  95. /* define PDC[31:16] as DATA[31:16] */
  96. #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
  97. /* no pull-up for D[31:16] */
  98. #define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
  99. /* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
  100. #define CONFIG_SYS_MATRIX_EBICSA_VAL \
  101. (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC |\
  102. AT91_MATRIX_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_VDDIOMSEL)
  103. /* SDRAM */
  104. /* SDRAMC_MR Mode register */
  105. #define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
  106. /* SDRAMC_TR - Refresh Timer register */
  107. #define CONFIG_SYS_SDRC_TR_VAL1 0x287
  108. /* SDRAMC_CR - Configuration register*/
  109. #if defined(CONFIG_CPU9G20)
  110. #define CONFIG_SYS_SDRC_CR_VAL_64MB \
  111. (AT91_SDRAMC_NC_9 | \
  112. AT91_SDRAMC_NR_13 | \
  113. AT91_SDRAMC_NB_4 | \
  114. AT91_SDRAMC_CAS_2 | \
  115. AT91_SDRAMC_DBW_32 | \
  116. (2 << 8) | /* Write Recovery Delay */ \
  117. (9 << 12) | /* Row Cycle Delay */ \
  118. (3 << 16) | /* Row Precharge Delay */ \
  119. (3 << 20) | /* Row to Column Delay */ \
  120. (6 << 24) | /* Active to Precharge Delay */ \
  121. (10 << 28)) /* Exit Self Refresh to Active Delay */
  122. #define CONFIG_SYS_SDRC_CR_VAL_128MB \
  123. (AT91_SDRAMC_NC_10 | \
  124. AT91_SDRAMC_NR_13 | \
  125. AT91_SDRAMC_NB_4 | \
  126. AT91_SDRAMC_CAS_2 | \
  127. AT91_SDRAMC_DBW_32 | \
  128. (2 << 8) | /* Write Recovery Delay */ \
  129. (9 << 12) | /* Row Cycle Delay */ \
  130. (3 << 16) | /* Row Precharge Delay */ \
  131. (3 << 20) | /* Row to Column Delay */ \
  132. (6 << 24) | /* Active to Precharge Delay */ \
  133. (10 << 28)) /* Exit Self Refresh to Active Delay */
  134. #elif defined(CONFIG_CPU9260)
  135. #define CONFIG_SYS_SDRC_CR_VAL_64MB \
  136. (AT91_SDRAMC_NC_9 | \
  137. AT91_SDRAMC_NR_13 | \
  138. AT91_SDRAMC_NB_4 | \
  139. AT91_SDRAMC_CAS_2 | \
  140. AT91_SDRAMC_DBW_32 | \
  141. (2 << 8) | /* Write Recovery Delay */ \
  142. (7 << 12) | /* Row Cycle Delay */ \
  143. (2 << 16) | /* Row Precharge Delay */ \
  144. (2 << 20) | /* Row to Column Delay */ \
  145. (5 << 24) | /* Active to Precharge Delay */ \
  146. (8 << 28)) /* Exit Self Refresh to Active Delay */
  147. #define CONFIG_SYS_SDRC_CR_VAL_128MB \
  148. (AT91_SDRAMC_NC_10 | \
  149. AT91_SDRAMC_NR_13 | \
  150. AT91_SDRAMC_NB_4 | \
  151. AT91_SDRAMC_CAS_2 | \
  152. AT91_SDRAMC_DBW_32 | \
  153. (2 << 8) | /* Write Recovery Delay */ \
  154. (7 << 12) | /* Row Cycle Delay */ \
  155. (2 << 16) | /* Row Precharge Delay */ \
  156. (2 << 20) | /* Row to Column Delay */ \
  157. (5 << 24) | /* Active to Precharge Delay */ \
  158. (8 << 28)) /* Exit Self Refresh to Active Delay */
  159. #endif
  160. /* Memory Device Register -> SDRAM */
  161. #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
  162. #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
  163. #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
  164. #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
  165. #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
  166. #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
  167. #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
  168. #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
  169. #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
  170. #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
  171. #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
  172. #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
  173. #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
  174. #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
  175. #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
  176. #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
  177. #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
  178. #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
  179. /* setup SMC0, CS0 (NOR Flash) - 16-bit */
  180. #if defined(CONFIG_CPU9G20)
  181. #define CONFIG_SYS_SMC0_SETUP0_VAL \
  182. (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
  183. AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
  184. #define CONFIG_SYS_SMC0_PULSE0_VAL \
  185. (AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(8) | \
  186. AT91_SMC_NRDPULSE_(14) | AT91_SMC_NCS_RDPULSE_(14))
  187. #define CONFIG_SYS_SMC0_CYCLE0_VAL \
  188. (AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(14))
  189. #define CONFIG_SYS_SMC0_MODE0_VAL \
  190. (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
  191. AT91_SMC_DBW_16 | \
  192. AT91_SMC_TDFMODE | \
  193. AT91_SMC_TDF_(3))
  194. #elif defined(CONFIG_CPU9260)
  195. #define CONFIG_SYS_SMC0_SETUP0_VAL \
  196. (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
  197. AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
  198. #define CONFIG_SYS_SMC0_PULSE0_VAL \
  199. (AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(6) | \
  200. AT91_SMC_NRDPULSE_(10) | AT91_SMC_NCS_RDPULSE_(10))
  201. #define CONFIG_SYS_SMC0_CYCLE0_VAL \
  202. (AT91_SMC_NWECYCLE_(6) | AT91_SMC_NRDCYCLE_(10))
  203. #define CONFIG_SYS_SMC0_MODE0_VAL \
  204. (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
  205. AT91_SMC_DBW_16 | \
  206. AT91_SMC_TDFMODE | \
  207. AT91_SMC_TDF_(2))
  208. #endif
  209. /* user reset enable */
  210. #define CONFIG_SYS_RSTC_RMR_VAL \
  211. (AT91_RSTC_KEY | \
  212. AT91_RSTC_PROCRST | \
  213. AT91_RSTC_RSTTYP_WAKEUP | \
  214. AT91_RSTC_RSTTYP_WATCHDOG)
  215. /* Disable Watchdog */
  216. #define CONFIG_SYS_WDTC_WDMR_VAL \
  217. (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
  218. AT91_WDT_WDV | \
  219. AT91_WDT_WDDIS | \
  220. AT91_WDT_WDD)
  221. /*
  222. * Hardware drivers
  223. */
  224. #define CONFIG_ATMEL_USART 1
  225. #undef CONFIG_USART0
  226. #undef CONFIG_USART1
  227. #undef CONFIG_USART2
  228. #define CONFIG_USART3 1 /* USART 3 is DBGU */
  229. #define CONFIG_BOOTDELAY 3
  230. /*
  231. * BOOTP options
  232. */
  233. #define CONFIG_BOOTP_BOOTFILESIZE 1
  234. #define CONFIG_BOOTP_BOOTPATH 1
  235. #define CONFIG_BOOTP_GATEWAY 1
  236. #define CONFIG_BOOTP_HOSTNAME 1
  237. /*
  238. * Command line configuration.
  239. */
  240. #include <config_cmd_default.h>
  241. #undef CONFIG_CMD_BDI
  242. #undef CONFIG_CMD_IMI
  243. #undef CONFIG_CMD_FPGA
  244. #undef CONFIG_CMD_LOADS
  245. #undef CONFIG_CMD_IMLS
  246. #define CONFIG_CMD_PING 1
  247. #define CONFIG_CMD_DHCP 1
  248. #define CONFIG_CMD_NAND 1
  249. #define CONFIG_CMD_USB 1
  250. #define CONFIG_CMD_FAT 1
  251. /* SDRAM */
  252. #define CONFIG_NR_DRAM_BANKS 1
  253. #define PHYS_SDRAM 0x20000000
  254. #if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
  255. #define PHYS_SDRAM_SIZE 0x08000000 /* 128 MB */
  256. #define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
  257. #else
  258. #define PHYS_SDRAM_SIZE 0x04000000 /* 64 MB */
  259. #define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
  260. #endif
  261. /* NAND flash */
  262. #define CONFIG_NAND_ATMEL 1
  263. #define NAND_MAX_CHIPS 1
  264. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  265. #define CONFIG_SYS_NAND_BASE 0x40000000
  266. #define CONFIG_SYS_NAND_DBW_8 1
  267. #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
  268. #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
  269. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  270. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  271. /* NOR flash */
  272. #define CONFIG_SYS_FLASH_CFI 1
  273. #define CONFIG_FLASH_CFI_DRIVER 1
  274. #define PHYS_FLASH_1 0x10000000
  275. #define PHYS_FLASH_2 0x12000000
  276. #define CONFIG_SYS_FLASH_BANKS_LIST \
  277. { PHYS_FLASH_1, PHYS_FLASH_2 }
  278. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  279. #define CONFIG_SYS_MAX_FLASH_SECT (255+4)
  280. #define CONFIG_SYS_MAX_FLASH_BANKS 2
  281. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  282. #define CONFIG_SYS_FLASH_EMPTY_INFO 1
  283. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
  284. #define CONFIG_SYS_FLASH_PROTECTION 1
  285. #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
  286. /* Ethernet */
  287. #define CONFIG_MACB 1
  288. #define CONFIG_RMII 1
  289. #define CONFIG_RESET_PHY_R 1
  290. #define CONFIG_NET_MULTI 1
  291. #define CONFIG_NET_RETRY_COUNT 20
  292. #define CONFIG_MACB_SEARCH_PHY 1
  293. /* LEDS */
  294. /* Status LED */
  295. #define CONFIG_STATUS_LED 1 /* Status LED enabled */
  296. #define CONFIG_BOARD_SPECIFIC_LED 1
  297. #define STATUS_LED_RED 0
  298. #define STATUS_LED_GREEN 1
  299. #define STATUS_LED_YELLOW 2
  300. #define STATUS_LED_BLUE 3
  301. /* Red */
  302. #define STATUS_LED_BIT STATUS_LED_RED
  303. #define STATUS_LED_STATE STATUS_LED_OFF
  304. #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
  305. /* Green */
  306. #define STATUS_LED_BIT1 STATUS_LED_GREEN
  307. #define STATUS_LED_STATE1 STATUS_LED_OFF
  308. #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
  309. /* Yellow */
  310. #define STATUS_LED_BIT2 STATUS_LED_YELLOW
  311. #define STATUS_LED_STATE2 STATUS_LED_OFF
  312. #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
  313. /* Blue */
  314. #define STATUS_LED_BIT3 STATUS_LED_BLUE
  315. #define STATUS_LED_STATE3 STATUS_LED_ON
  316. #define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
  317. /* Optional value */
  318. #define STATUS_LED_BOOT STATUS_LED_BIT
  319. #define CONFIG_RED_LED AT91_PIN_PC11
  320. #define CONFIG_GREEN_LED AT91_PIN_PC12
  321. #define CONFIG_YELLOW_LED AT91_PIN_PC7
  322. #define CONFIG_BLUE_LED AT91_PIN_PC9
  323. /* USB */
  324. #define CONFIG_USB_ATMEL 1
  325. #define CONFIG_USB_OHCI_NEW 1
  326. #define CONFIG_DOS_PARTITION 1
  327. #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
  328. #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
  329. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
  330. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  331. #define CONFIG_USB_STORAGE 1
  332. #define CONFIG_SYS_LOAD_ADDR 0x21000000
  333. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  334. #define CONFIG_SYS_MEMTEST_END 0x21e00000
  335. #undef CONFIG_SYS_USE_NANDFLASH
  336. #define CONFIG_SYS_USE_FLASH 1
  337. #if defined(CONFIG_SYS_USE_FLASH)
  338. #define CONFIG_ENV_IS_IN_FLASH 1
  339. #define CONFIG_ENV_OFFSET 0x40000
  340. #define CONFIG_ENV_SECT_SIZE 0x20000
  341. #define CONFIG_ENV_SIZE 0x20000
  342. #define CONFIG_ENV_OVERWRITE 1
  343. #define CONFIG_BOOTCOMMAND "run flashboot"
  344. #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
  345. #define MTDPARTS_DEFAULT \
  346. "mtdparts=physmap-flash.0:" \
  347. "256k(u-boot)ro," \
  348. "128k(u-boot-env)ro," \
  349. "1792k(kernel)," \
  350. "-(rootfs);" \
  351. "atmel_nand:-(nand)"
  352. #define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
  353. #if defined(CONFIG_CPU9G20)
  354. #define CONFIG_SYS_BASEDIR "cpu9G20"
  355. #elif defined(CONFIG_CPU9260)
  356. #define CONFIG_SYS_BASEDIR "cpu9260"
  357. #endif
  358. #define CONFIG_EXTRA_ENV_SETTINGS \
  359. "mtdids=" MTDIDS_DEFAULT "\0" \
  360. "mtdparts=" MTDPARTS_DEFAULT "\0" \
  361. "partition=nand0,0\0" \
  362. "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
  363. "ramboot=tftpboot 0x22000000 cpu9260/uImage;" \
  364. "run ramargs;bootm 22000000\0" \
  365. "flashboot=run ramargs;bootm 0x10060000\0" \
  366. "basedir=" CONFIG_SYS_BASEDIR "\0" \
  367. "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
  368. "off 0x10000000 0x1003ffff;erase 0x10000000 " \
  369. "0x1003ffff;cp.b 0x24000000 0x10000000 " \
  370. "$(filesize)\0" \
  371. "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
  372. " 0x10060000 0x1021ffff;erase 0x10060000 " \
  373. "0x1021ffff;cp.b 0x24000000 0x10060000 " \
  374. "$(filesize)\0" \
  375. "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
  376. "protect off 0x10220000 0x13ffffff;erase " \
  377. "0x10220000 0x13ffffff;cp.b 0x24000000 " \
  378. "0x10220000 $(filesize)\0" \
  379. ""
  380. #endif
  381. #define CONFIG_BAUDRATE 115200
  382. #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
  383. #if defined(CONFIG_CPU9G20)
  384. #define CONFIG_SYS_PROMPT "CPU9G20=> "
  385. #elif defined(CONFIG_CPU9260)
  386. #define CONFIG_SYS_PROMPT "CPU9260=> "
  387. #endif
  388. #define CONFIG_SYS_CBSIZE 256
  389. #define CONFIG_SYS_MAXARGS 16
  390. #define CONFIG_SYS_PBSIZE \
  391. (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  392. #define CONFIG_SYS_LONGHELP 1
  393. #define CONFIG_CMDLINE_EDITING 1
  394. #define CONFIG_SILENT_CONSOLE 1
  395. #define CONFIG_NETCONSOLE 1
  396. /*
  397. * Size of malloc() pool
  398. */
  399. #define CONFIG_SYS_MALLOC_LEN \
  400. ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
  401. #define CONFIG_SYS_GBL_DATA_SIZE 128
  402. #define CONFIG_STACKSIZE (32 * 1024)
  403. #if defined(CONFIG_USE_IRQ)
  404. #error CONFIG_USE_IRQ not supported
  405. #endif
  406. #endif