at91sam9263ek.h 11 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stelian Pop <stelian.pop@leadtechdesign.com>
  4. * Lead Tech Design <www.leadtechdesign.com>
  5. *
  6. * Configuation settings for the AT91SAM9263EK board.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /* ARM asynchronous clock */
  29. #define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
  30. #define CONFIG_SYS_HZ 1000
  31. #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
  32. #define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
  33. #define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */
  34. #define CONFIG_ARCH_CPU_INIT
  35. #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
  36. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  37. #define CONFIG_SETUP_MEMORY_TAGS 1
  38. #define CONFIG_INITRD_TAG 1
  39. #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
  40. #define CONFIG_SKIP_LOWLEVEL_INIT
  41. #define CONFIG_SKIP_RELOCATE_UBOOT
  42. #endif
  43. /*
  44. * Hardware drivers
  45. */
  46. #define CONFIG_ATMEL_USART 1
  47. #undef CONFIG_USART0
  48. #undef CONFIG_USART1
  49. #undef CONFIG_USART2
  50. #define CONFIG_USART3 1 /* USART 3 is DBGU */
  51. /* LCD */
  52. #define CONFIG_LCD 1
  53. #define LCD_BPP LCD_COLOR8
  54. #define CONFIG_LCD_LOGO 1
  55. #undef LCD_TEST_PATTERN
  56. #define CONFIG_LCD_INFO 1
  57. #define CONFIG_LCD_INFO_BELOW_LOGO 1
  58. #define CONFIG_SYS_WHITE_ON_BLACK 1
  59. #define CONFIG_ATMEL_LCD 1
  60. #define CONFIG_ATMEL_LCD_BGR555 1
  61. #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
  62. /* LED */
  63. #define CONFIG_AT91_LED
  64. #define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */
  65. #define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
  66. #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* this is the user2 led */
  67. #define CONFIG_BOOTDELAY 3
  68. /*
  69. * BOOTP options
  70. */
  71. #define CONFIG_BOOTP_BOOTFILESIZE 1
  72. #define CONFIG_BOOTP_BOOTPATH 1
  73. #define CONFIG_BOOTP_GATEWAY 1
  74. #define CONFIG_BOOTP_HOSTNAME 1
  75. /*
  76. * Command line configuration.
  77. */
  78. #include <config_cmd_default.h>
  79. #undef CONFIG_CMD_BDI
  80. #undef CONFIG_CMD_FPGA
  81. #undef CONFIG_CMD_IMI
  82. #undef CONFIG_CMD_IMLS
  83. #undef CONFIG_CMD_LOADS
  84. #undef CONFIG_CMD_SOURCE
  85. #define CONFIG_CMD_PING 1
  86. #define CONFIG_CMD_DHCP 1
  87. #define CONFIG_CMD_NAND 1
  88. #define CONFIG_CMD_USB 1
  89. /* SDRAM */
  90. #define CONFIG_NR_DRAM_BANKS 1
  91. #define PHYS_SDRAM 0x20000000
  92. #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
  93. /* DataFlash */
  94. #define CONFIG_ATMEL_DATAFLASH_SPI
  95. #define CONFIG_HAS_DATAFLASH 1
  96. #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
  97. #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
  98. #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
  99. #define AT91_SPI_CLK 15000000
  100. #define DATAFLASH_TCSS (0x1a << 16)
  101. #define DATAFLASH_TCHS (0x1 << 24)
  102. /* NOR flash, if populated */
  103. #ifdef CONFIG_SYS_USE_NORFLASH
  104. #define CONFIG_SYS_FLASH_CFI 1
  105. #define CONFIG_FLASH_CFI_DRIVER 1
  106. #define PHYS_FLASH_1 0x10000000
  107. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  108. #define CONFIG_SYS_MAX_FLASH_SECT 256
  109. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  110. #define CONFIG_SYS_MONITOR_SEC 1:0-3
  111. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  112. #define CONFIG_SYS_MONITOR_LEN (256 << 10)
  113. #define CONFIG_ENV_IS_IN_FLASH 1
  114. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007FE000)
  115. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
  116. /* Address and size of Primary Environment Sector */
  117. #define CONFIG_ENV_SIZE 0x2000
  118. #define xstr(s) str(s)
  119. #define str(s) #s
  120. #define CONFIG_EXTRA_ENV_SETTINGS \
  121. "monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
  122. "update=" \
  123. "protect off ${monitor_base} +${filesize};" \
  124. "erase ${monitor_base} +${filesize};" \
  125. "cp.b ${load_addr} ${monitor_base} ${filesize};" \
  126. "protect on ${monitor_base} +${filesize}\0"
  127. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  128. #define MASTER_PLL_MUL 171
  129. #define MASTER_PLL_DIV 14
  130. /* clocks */
  131. #define CONFIG_SYS_MOR_VAL \
  132. (AT91_PMC_MOSCEN | \
  133. (255 << 8)) /* Main Oscillator Start-up Time */
  134. #define CONFIG_SYS_PLLAR_VAL \
  135. (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
  136. AT91_PMC_OUT | \
  137. AT91_PMC_PLLCOUNT | /* PLL Counter */ \
  138. (2 << 28) | /* PLL Clock Frequency Range */ \
  139. ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  140. /* PCK/2 = MCK Master Clock from PLLA */
  141. #define CONFIG_SYS_MCKR1_VAL \
  142. (AT91_PMC_CSS_SLOW | \
  143. AT91_PMC_PRES_1 | \
  144. AT91SAM9_PMC_MDIV_2 | \
  145. AT91_PMC_PDIV_1)
  146. /* PCK/2 = MCK Master Clock from PLLA */
  147. #define CONFIG_SYS_MCKR2_VAL \
  148. (AT91_PMC_CSS_PLLA | \
  149. AT91_PMC_PRES_1 | \
  150. AT91SAM9_PMC_MDIV_2 | \
  151. AT91_PMC_PDIV_1)
  152. /* define PDC[31:16] as DATA[31:16] */
  153. #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
  154. /* no pull-up for D[31:16] */
  155. #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
  156. /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
  157. #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
  158. (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
  159. AT91_MATRIX_EBI0_CS1A_SDRAMC)
  160. /* SDRAM */
  161. /* SDRAMC_MR Mode register */
  162. #define CONFIG_SYS_SDRC_MR_VAL1 0
  163. /* SDRAMC_TR - Refresh Timer register */
  164. #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
  165. /* SDRAMC_CR - Configuration register*/
  166. #define CONFIG_SYS_SDRC_CR_VAL \
  167. (AT91_SDRAMC_NC_9 | \
  168. AT91_SDRAMC_NR_13 | \
  169. AT91_SDRAMC_NB_4 | \
  170. AT91_SDRAMC_CAS_3 | \
  171. AT91_SDRAMC_DBW_32 | \
  172. (1 << 8) | /* Write Recovery Delay */ \
  173. (7 << 12) | /* Row Cycle Delay */ \
  174. (2 << 16) | /* Row Precharge Delay */ \
  175. (2 << 20) | /* Row to Column Delay */ \
  176. (5 << 24) | /* Active to Precharge Delay */ \
  177. (1 << 28)) /* Exit Self Refresh to Active Delay */
  178. /* Memory Device Register -> SDRAM */
  179. #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
  180. #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
  181. #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
  182. #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
  183. #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
  184. #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
  185. #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
  186. #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
  187. #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
  188. #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
  189. #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
  190. #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
  191. #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
  192. #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
  193. #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
  194. #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
  195. #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
  196. #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
  197. /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
  198. #define CONFIG_SYS_SMC0_SETUP0_VAL \
  199. (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
  200. AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
  201. #define CONFIG_SYS_SMC0_PULSE0_VAL \
  202. (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
  203. AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
  204. #define CONFIG_SYS_SMC0_CYCLE0_VAL \
  205. (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
  206. #define CONFIG_SYS_SMC0_MODE0_VAL \
  207. (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
  208. AT91_SMC_DBW_16 | \
  209. AT91_SMC_TDFMODE | \
  210. AT91_SMC_TDF_(6))
  211. /* user reset enable */
  212. #define CONFIG_SYS_RSTC_RMR_VAL \
  213. (AT91_RSTC_KEY | \
  214. AT91_RSTC_PROCRST | \
  215. AT91_RSTC_RSTTYP_WAKEUP | \
  216. AT91_RSTC_RSTTYP_WATCHDOG)
  217. /* Disable Watchdog */
  218. #define CONFIG_SYS_WDTC_WDMR_VAL \
  219. (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
  220. AT91_WDT_WDV | \
  221. AT91_WDT_WDDIS | \
  222. AT91_WDT_WDD)
  223. #endif
  224. #else
  225. #define CONFIG_SYS_NO_FLASH 1
  226. #endif
  227. /* NAND flash */
  228. #ifdef CONFIG_CMD_NAND
  229. #define CONFIG_NAND_ATMEL
  230. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  231. #define CONFIG_SYS_NAND_BASE 0x40000000
  232. #define CONFIG_SYS_NAND_DBW_8 1
  233. /* our ALE is AD21 */
  234. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  235. /* our CLE is AD22 */
  236. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  237. #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
  238. #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
  239. #endif
  240. /* Ethernet */
  241. #define CONFIG_MACB 1
  242. #define CONFIG_RMII 1
  243. #define CONFIG_NET_MULTI 1
  244. #define CONFIG_NET_RETRY_COUNT 20
  245. #define CONFIG_RESET_PHY_R 1
  246. /* USB */
  247. #define CONFIG_USB_ATMEL
  248. #define CONFIG_USB_OHCI_NEW 1
  249. #define CONFIG_DOS_PARTITION 1
  250. #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
  251. #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
  252. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
  253. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  254. #define CONFIG_USB_STORAGE 1
  255. #define CONFIG_CMD_FAT 1
  256. #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  257. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  258. #define CONFIG_SYS_MEMTEST_END 0x23e00000
  259. #ifdef CONFIG_SYS_USE_DATAFLASH
  260. /* bootstrap + u-boot + env + linux in dataflash on CS0 */
  261. #define CONFIG_ENV_IS_IN_DATAFLASH 1
  262. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
  263. #define CONFIG_ENV_OFFSET 0x4200
  264. #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
  265. #define CONFIG_ENV_SIZE 0x4200
  266. #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
  267. #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
  268. "root=/dev/mtdblock0 " \
  269. "mtdparts=atmel_nand:-(root) "\
  270. "rw rootfstype=jffs2"
  271. #elif CONFIG_SYS_USE_NANDFLASH
  272. /* bootstrap + u-boot + env + linux in nandflash */
  273. #define CONFIG_ENV_IS_IN_NAND 1
  274. #define CONFIG_ENV_OFFSET 0x60000
  275. #define CONFIG_ENV_OFFSET_REDUND 0x80000
  276. #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
  277. #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
  278. #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
  279. "root=/dev/mtdblock5 " \
  280. "mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
  281. "rw rootfstype=jffs2"
  282. #endif
  283. #define CONFIG_BAUDRATE 115200
  284. #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
  285. #define CONFIG_SYS_PROMPT "U-Boot> "
  286. #define CONFIG_SYS_CBSIZE 256
  287. #define CONFIG_SYS_MAXARGS 16
  288. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  289. #define CONFIG_SYS_LONGHELP 1
  290. #define CONFIG_CMDLINE_EDITING 1
  291. #define CONFIG_AUTO_COMPLETE
  292. #define CONFIG_SYS_HUSH_PARSER
  293. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  294. /*
  295. * Size of malloc() pool
  296. */
  297. #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
  298. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
  299. #define CONFIG_STACKSIZE (32*1024) /* regular stack */
  300. #ifdef CONFIG_USE_IRQ
  301. #error CONFIG_USE_IRQ not supported
  302. #endif
  303. #endif