aria.h 20 KB

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  1. /*
  2. * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
  3. * (C) Copyright 2009, DAVE Srl <www.dave.eu>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * Aria board configuration file
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. #define CONFIG_ARIA 1
  29. /*
  30. * Memory map for the ARIA board:
  31. *
  32. * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB)
  33. * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB)
  34. * 0x3010_0000-0x3011_FFFF On Board SRAM (128 KB) - CS6
  35. * 0x3020_0000-0x3021_FFFF FPGA (128 KB) - CS2
  36. * 0x8000_0000-0x803F_FFFF IMMR (4 MB)
  37. * 0x8400_0000-0x82FF_FFFF PCI I/O space (16 MB)
  38. * 0xA000_0000-0xAFFF_FFFF PCI memory space (256 MB)
  39. * 0xB000_0000-0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
  40. * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB)
  41. */
  42. /*
  43. * High Level Configuration Options
  44. */
  45. #define CONFIG_E300 1 /* E300 Family */
  46. #define CONFIG_MPC512X 1 /* MPC512X family */
  47. #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
  48. #define CONFIG_FSL_DIU_LOGO_BMP 1 /* Don't include FSL DIU binary bmp */
  49. /* video */
  50. #undef CONFIG_VIDEO
  51. #if defined(CONFIG_VIDEO)
  52. #define CONFIG_CFB_CONSOLE
  53. #define CONFIG_VGA_AS_SINGLE_DEVICE
  54. #endif
  55. /* CONFIG_PCI is defined at config time */
  56. #define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */
  57. #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
  58. #define CONFIG_MISC_INIT_R
  59. #define CONFIG_SYS_IMMR 0x80000000
  60. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
  61. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
  62. #define CONFIG_SYS_MEMTEST_END 0x00400000
  63. /*
  64. * DDR Setup - manually set all parameters as there's no SPD etc.
  65. */
  66. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  67. #define CONFIG_SYS_DDR_BASE 0x00000000
  68. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  69. /* DDR Controller Configuration
  70. *
  71. * SYS_CFG:
  72. * [31:31] MDDRC Soft Reset: Diabled
  73. * [30:30] DRAM CKE pin: Enabled
  74. * [29:29] DRAM CLK: Enabled
  75. * [28:28] Command Mode: Enabled (For initialization only)
  76. * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
  77. * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
  78. * [20:19] Read Test: DON'T USE
  79. * [18:18] Self Refresh: Enabled
  80. * [17:17] 16bit Mode: Disabled
  81. * [16:13] Ready Delay: 2
  82. * [12:12] Half DQS Delay: Disabled
  83. * [11:11] Quarter DQS Delay: Disabled
  84. * [10:08] Write Delay: 2
  85. * [07:07] Early ODT: Disabled
  86. * [06:06] On DIE Termination: Disabled
  87. * [05:05] FIFO Overflow Clear: DON'T USE here
  88. * [04:04] FIFO Underflow Clear: DON'T USE here
  89. * [03:03] FIFO Overflow Pending: DON'T USE here
  90. * [02:02] FIFO Underlfow Pending: DON'T USE here
  91. * [01:01] FIFO Overlfow Enabled: Enabled
  92. * [00:00] FIFO Underflow Enabled: Enabled
  93. * TIME_CFG0
  94. * [31:16] DRAM Refresh Time: 0 CSB clocks
  95. * [15:8] DRAM Command Time: 0 CSB clocks
  96. * [07:00] DRAM Precharge Time: 0 CSB clocks
  97. * TIME_CFG1
  98. * [31:26] DRAM tRFC:
  99. * [25:21] DRAM tWR1:
  100. * [20:17] DRAM tWRT1:
  101. * [16:11] DRAM tDRR:
  102. * [10:05] DRAM tRC:
  103. * [04:00] DRAM tRAS:
  104. * TIME_CFG2
  105. * [31:28] DRAM tRCD:
  106. * [27:23] DRAM tFAW:
  107. * [22:19] DRAM tRTW1:
  108. * [18:15] DRAM tCCD:
  109. * [14:10] DRAM tRTP:
  110. * [09:05] DRAM tRP:
  111. * [04:00] DRAM tRPA
  112. */
  113. #define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \
  114. (1 << 30) | /* CKE */ \
  115. (1 << 29) | /* CLK_ON */ \
  116. (0 << 28) | /* CMD_MODE */ \
  117. (4 << 25) | /* DRAM_ROW_SELECT */ \
  118. (3 << 21) | /* DRAM_BANK_SELECT */ \
  119. (0 << 18) | /* SELF_REF_EN */ \
  120. (0 << 17) | /* 16BIT_MODE */ \
  121. (2 << 13) | /* RDLY */ \
  122. (0 << 12) | /* HALF_DQS_DLY */ \
  123. (1 << 11) | /* QUART_DQS_DLY */ \
  124. (2 << 8) | /* WDLY */ \
  125. (0 << 7) | /* EARLY_ODT */ \
  126. (1 << 6) | /* ON_DIE_TERMINATE */ \
  127. (0 << 5) | /* FIFO_OV_CLEAR */ \
  128. (0 << 4) | /* FIFO_UV_CLEAR */ \
  129. (0 << 1) | /* FIFO_OV_EN */ \
  130. (0 << 0) /* FIFO_UV_EN */ \
  131. )
  132. #define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
  133. #define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189
  134. #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863
  135. #define CONFIG_SYS_DDRCMD_NOP 0x01380000
  136. #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
  137. #define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \
  138. (0 << 22) | /* DRAM_CS */ \
  139. (0 << 21) | /* DRAM_RAS */ \
  140. (0 << 20) | /* DRAM_CAS */ \
  141. (0 << 19) | /* DRAM_WEB */ \
  142. (1 << 16) | /* DRAM_BS[2:0] */ \
  143. (0 << 15) | /* */ \
  144. (0 << 12) | /* A12->out */ \
  145. (0 << 11) | /* A11->RDQS */ \
  146. (0 << 10) | /* A10->DQS# */ \
  147. (0 << 7) | /* OCD program */ \
  148. (0 << 6) | /* Rtt1 */ \
  149. (0 << 3) | /* posted CAS# */ \
  150. (0 << 2) | /* Rtt0 */ \
  151. (1 << 1) | /* ODS */ \
  152. (0 << 0) /* DLL */ \
  153. )
  154. #define CONFIG_SYS_MICRON_EMR2 0x01020000
  155. #define CONFIG_SYS_MICRON_EMR3 0x01030000
  156. #define CONFIG_SYS_DDRCMD_RFSH 0x01080000
  157. #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
  158. #define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \
  159. (0 << 22) | /* DRAM_CS */ \
  160. (0 << 21) | /* DRAM_RAS */ \
  161. (0 << 20) | /* DRAM_CAS */ \
  162. (0 << 19) | /* DRAM_WEB */ \
  163. (1 << 16) | /* DRAM_BS[2:0] */ \
  164. (0 << 15) | /* */ \
  165. (0 << 12) | /* A12->out */ \
  166. (0 << 11) | /* A11->RDQS */ \
  167. (1 << 10) | /* A10->DQS# */ \
  168. (7 << 7) | /* OCD program */ \
  169. (0 << 6) | /* Rtt1 */ \
  170. (0 << 3) | /* posted CAS# */ \
  171. (1 << 2) | /* Rtt0 */ \
  172. (0 << 1) | /* ODS (Output Drive Strength) */ \
  173. (0 << 0) /* DLL */ \
  174. )
  175. /*
  176. * Backward compatible definitions,
  177. * so we do not have to change cpu/mpc512x/fixed_sdram.c
  178. */
  179. #define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
  180. #define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
  181. #define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
  182. #define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
  183. /* DDR Priority Manager Configuration */
  184. #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
  185. #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
  186. #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
  187. #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
  188. #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
  189. #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
  190. #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
  191. #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
  192. #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
  193. #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
  194. #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
  195. #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
  196. #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
  197. #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
  198. #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
  199. #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
  200. #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
  201. #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
  202. #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
  203. #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
  204. #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
  205. #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
  206. #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
  207. /*
  208. * NOR FLASH on the Local Bus
  209. */
  210. #define CONFIG_SYS_FLASH_CFI /* use the CFI code */
  211. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  212. #define CONFIG_SYS_FLASH_BASE 0xF8000000 /* start of FLASH */
  213. #define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max flash size */
  214. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  215. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  216. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
  217. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max sectors */
  218. #undef CONFIG_SYS_FLASH_CHECKSUM
  219. /*
  220. * NAND FLASH support
  221. * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
  222. */
  223. #define CONFIG_CMD_NAND /* enable NAND support */
  224. #define CONFIG_JFFS2_NAND /* with JFFS2 on it */
  225. #define CONFIG_NAND_MPC5121_NFC
  226. #define CONFIG_SYS_NAND_BASE 0x40000000
  227. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  228. #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
  229. /*
  230. * Configuration parameters for MPC5121 NAND driver
  231. */
  232. #define CONFIG_FSL_NFC_WIDTH 1
  233. #define CONFIG_FSL_NFC_WRITE_SIZE 2048
  234. #define CONFIG_FSL_NFC_SPARE_SIZE 64
  235. #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
  236. #define CONFIG_SYS_SRAM_BASE 0x30000000
  237. #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
  238. /* Make two SRAM regions contiguous */
  239. #define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \
  240. CONFIG_SYS_SRAM_SIZE)
  241. #define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */
  242. #define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \
  243. CONFIG_SYS_ARIA_SRAM_SIZE)
  244. #define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */
  245. #define CONFIG_SYS_CS0_CFG 0x05059150
  246. #define CONFIG_SYS_CS2_CFG ( (5 << 24) | \
  247. (5 << 16) | \
  248. (1 << 15) | \
  249. (0 << 14) | \
  250. (0 << 13) | \
  251. (1 << 12) | \
  252. (0 << 10) | \
  253. (3 << 8) | /* 32 bit */ \
  254. (0 << 7) | \
  255. (1 << 6) | \
  256. (1 << 4) | \
  257. (0 << 3) | \
  258. (0 << 2) | \
  259. (0 << 1) | \
  260. (0 << 0) \
  261. )
  262. #define CONFIG_SYS_CS6_CFG 0x05059150
  263. /* Use alternative CS timing for CS0 and CS2 */
  264. #define CONFIG_SYS_CS_ALETIMING 0x00000005
  265. /* Use SRAM for initial stack */
  266. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
  267. #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
  268. #define CONFIG_SYS_GBL_DATA_SIZE 0x100
  269. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
  270. CONFIG_SYS_GBL_DATA_SIZE)
  271. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  272. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
  273. #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
  274. #ifdef CONFIG_FSL_DIU_FB
  275. #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
  276. #else
  277. #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
  278. #endif
  279. /* FPGA */
  280. #define CONFIG_ARIA_FPGA 1
  281. /*
  282. * Serial Port
  283. */
  284. #define CONFIG_CONS_INDEX 1
  285. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  286. /*
  287. * Serial console configuration
  288. */
  289. #define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
  290. #if CONFIG_PSC_CONSOLE != 3
  291. #error CONFIG_PSC_CONSOLE must be 3
  292. #endif
  293. #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
  294. #define CONFIG_SYS_BAUDRATE_TABLE \
  295. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  296. #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
  297. #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
  298. #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
  299. #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
  300. #define CONFIG_CMDLINE_EDITING 1 /* command line history */
  301. /* Use the HUSH parser */
  302. #define CONFIG_SYS_HUSH_PARSER
  303. #ifdef CONFIG_SYS_HUSH_PARSER
  304. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  305. #endif
  306. /*
  307. * PCI
  308. */
  309. #ifdef CONFIG_PCI
  310. #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
  311. #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
  312. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
  313. #define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \
  314. CONFIG_SYS_PCI_MEM_SIZE)
  315. #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
  316. #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
  317. #define CONFIG_SYS_PCI_IO_BASE 0x00000000
  318. #define CONFIG_SYS_PCI_IO_PHYS 0x84000000
  319. #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
  320. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  321. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  322. #endif
  323. /* I2C */
  324. #define CONFIG_HARD_I2C /* I2C with hardware support */
  325. #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
  326. #define CONFIG_I2C_MULTI_BUS
  327. /* I2C speed and slave address */
  328. #define CONFIG_SYS_I2C_SPEED 100000
  329. #define CONFIG_SYS_I2C_SLAVE 0x7F
  330. #if 0
  331. #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
  332. #endif
  333. /*
  334. * IIM - IC Identification Module
  335. */
  336. #undef CONFIG_IIM
  337. /*
  338. * EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
  339. * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode
  340. */
  341. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  342. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  343. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  344. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
  345. /*
  346. * Ethernet configuration
  347. */
  348. #define CONFIG_MPC512x_FEC 1
  349. #define CONFIG_NET_MULTI
  350. #define CONFIG_PHY_ADDR 0x17
  351. #define CONFIG_MII 1 /* MII PHY management */
  352. #define CONFIG_FEC_AN_TIMEOUT 1
  353. #define CONFIG_HAS_ETH0
  354. /*
  355. * Environment
  356. */
  357. #define CONFIG_ENV_IS_IN_FLASH 1
  358. /* This has to be a multiple of the flash sector size */
  359. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
  360. CONFIG_SYS_MONITOR_LEN)
  361. #define CONFIG_ENV_SIZE 0x2000
  362. #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) */
  363. /* Address and size of Redundant Environment Sector */
  364. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
  365. CONFIG_ENV_SECT_SIZE)
  366. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  367. #define CONFIG_LOADS_ECHO 1
  368. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1
  369. #include <config_cmd_default.h>
  370. #define CONFIG_CMD_ASKENV
  371. #define CONFIG_CMD_DHCP
  372. #define CONFIG_CMD_EEPROM
  373. #undef CONFIG_CMD_FUSE
  374. #define CONFIG_CMD_I2C
  375. #undef CONFIG_CMD_IDE
  376. #define CONFIG_CMD_JFFS2
  377. #define CONFIG_CMD_MII
  378. #define CONFIG_CMD_NFS
  379. #define CONFIG_CMD_PING
  380. #define CONFIG_CMD_REGINFO
  381. #if defined(CONFIG_PCI)
  382. #define CONFIG_CMD_PCI
  383. #endif
  384. #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
  385. #define CONFIG_DOS_PARTITION
  386. #define CONFIG_MAC_PARTITION
  387. #define CONFIG_ISO_PARTITION
  388. #endif /* defined(CONFIG_CMD_IDE) */
  389. /*
  390. * Dynamic MTD partition support
  391. */
  392. #define CONFIG_CMD_MTDPARTS
  393. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  394. #define CONFIG_FLASH_CFI_MTD
  395. #define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand"
  396. /*
  397. * NOR flash layout:
  398. *
  399. * F8000000 - FEAFFFFF 107 MiB User Data
  400. * FEB00000 - FFAFFFFF 16 MiB Root File System
  401. * FFB00000 - FFFEFFFF 4 MiB Linux Kernel
  402. * FFF00000 - FFFBFFFF 768 KiB U-Boot (up to 512 KiB) and 2 x * env
  403. * FFFC0000 - FFFFFFFF 256 KiB Device Tree
  404. *
  405. * NAND flash layout: one big partition
  406. */
  407. #define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \
  408. "16m(rootfs)," \
  409. "4m(kernel)," \
  410. "768k(u-boot)," \
  411. "256k(dtb);" \
  412. "mpc5121.nand:-(data)"
  413. /*
  414. * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
  415. * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
  416. * is set to 0xFFFF, watchdog timeouts after about 64s. For details
  417. * refer to chapter 36 of the MPC5121e Reference Manual.
  418. */
  419. /* #define CONFIG_WATCHDOG */ /* enable watchdog */
  420. #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
  421. /*
  422. * Miscellaneous configurable options
  423. */
  424. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  425. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  426. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  427. #ifdef CONFIG_CMD_KGDB
  428. # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  429. #else
  430. # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  431. #endif
  432. /* Print Buffer Size */
  433. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  434. sizeof(CONFIG_SYS_PROMPT) + 16)
  435. /* max number of command args */
  436. #define CONFIG_SYS_MAXARGS 32
  437. /* Boot Argument Buffer Size */
  438. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  439. #define CONFIG_SYS_HZ 1000
  440. /*
  441. * For booting Linux, the board info and command line data
  442. * have to be in the first 8 MB of memory, since this is
  443. * the maximum mapped by the Linux kernel during initialization.
  444. */
  445. #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
  446. /* Cache Configuration */
  447. #define CONFIG_SYS_DCACHE_SIZE 32768
  448. #define CONFIG_SYS_CACHELINE_SIZE 32
  449. #ifdef CONFIG_CMD_KGDB
  450. #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */
  451. #endif
  452. #define CONFIG_SYS_HID0_INIT 0x000000000
  453. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
  454. HID0_ICE)
  455. #define CONFIG_SYS_HID2 HID2_HBE
  456. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  457. /*
  458. * Internal Definitions
  459. *
  460. * Boot Flags
  461. */
  462. #define BOOTFLAG_COLD 0x01
  463. #define BOOTFLAG_WARM 0x02
  464. #ifdef CONFIG_CMD_KGDB
  465. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  466. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  467. #endif
  468. /*
  469. * Environment Configuration
  470. */
  471. #define CONFIG_ENV_OVERWRITE
  472. #define CONFIG_TIMESTAMP
  473. #define CONFIG_HOSTNAME aria
  474. #define CONFIG_BOOTFILE aria/uImage
  475. #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
  476. #define CONFIG_LOADADDR 400000 /* default load addr */
  477. #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
  478. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  479. #define CONFIG_BAUDRATE 115200
  480. #define CONFIG_PREBOOT "echo;" \
  481. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  482. "echo"
  483. #define CONFIG_EXTRA_ENV_SETTINGS \
  484. "u-boot_addr_r=200000\0" \
  485. "kernel_addr_r=600000\0" \
  486. "fdt_addr_r=880000\0" \
  487. "ramdisk_addr_r=900000\0" \
  488. "u-boot_addr=FFF00000\0" \
  489. "kernel_addr=FFB00000\0" \
  490. "fdt_addr=FFFC0000\0" \
  491. "ramdisk_addr=FEB00000\0" \
  492. "ramdiskfile=aria/uRamdisk\0" \
  493. "u-boot=aria/u-boot.bin\0" \
  494. "fdtfile=aria/aria.dtb\0" \
  495. "netdev=eth0\0" \
  496. "consdev=ttyPSC0\0" \
  497. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  498. "nfsroot=${serverip}:${rootpath}\0" \
  499. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  500. "addip=setenv bootargs ${bootargs} " \
  501. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  502. ":${hostname}:${netdev}:off panic=1\0" \
  503. "addtty=setenv bootargs ${bootargs} " \
  504. "console=${consdev},${baudrate}\0" \
  505. "flash_nfs=run nfsargs addip addtty;" \
  506. "bootm ${kernel_addr} - ${fdt_addr}\0" \
  507. "flash_self=run ramargs addip addtty;" \
  508. "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
  509. "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
  510. "tftp ${fdt_addr_r} ${fdtfile};" \
  511. "run nfsargs addip addtty;" \
  512. "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  513. "net_self=tftp ${kernel_addr_r} ${bootfile};" \
  514. "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
  515. "tftp ${fdt_addr_r} ${fdtfile};" \
  516. "run ramargs addip addtty;" \
  517. "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
  518. "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
  519. "update=protect off ${u-boot_addr} +${filesize};" \
  520. "era ${u-boot_addr} +${filesize};" \
  521. "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
  522. "upd=run load update\0" \
  523. ""
  524. #define CONFIG_BOOTCOMMAND "run flash_self"
  525. #define CONFIG_OF_LIBFDT 1
  526. #define CONFIG_OF_BOARD_SETUP 1
  527. #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
  528. #define OF_CPU "PowerPC,5121@0"
  529. #define OF_SOC_COMPAT "fsl,mpc5121-immr"
  530. #define OF_TBCLK (bd->bi_busfreq / 4)
  531. #define OF_STDOUT_PATH "/soc@80000000/serial@11300"
  532. /*-----------------------------------------------------------------------
  533. * IDE/ATA stuff
  534. *-----------------------------------------------------------------------
  535. */
  536. #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
  537. #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  538. #undef CONFIG_IDE_LED /* LED for IDE not supported */
  539. #define CONFIG_IDE_RESET /* reset for IDE supported */
  540. #define CONFIG_IDE_PREINIT
  541. #define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */
  542. #define CONFIG_SYS_IDE_MAXDEVICE 2 /* 1 drive per IDE bus */
  543. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  544. #define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
  545. /* Offset for data I/O RefMan MPC5121EE Table 28-10 */
  546. #define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
  547. /* Offset for normal register accesses */
  548. #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
  549. /* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
  550. #define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
  551. /* Interval between registers */
  552. #define CONFIG_SYS_ATA_STRIDE 4
  553. #define ATA_BASE_ADDR get_pata_base()
  554. /*
  555. * Control register bit definitions
  556. */
  557. #define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
  558. #define FSL_ATA_CTRL_ATA_RST_B 0x40000000
  559. #define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
  560. #define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
  561. #define FSL_ATA_CTRL_DMA_PENDING 0x08000000
  562. #define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
  563. #define FSL_ATA_CTRL_DMA_WRITE 0x02000000
  564. #define FSL_ATA_CTRL_IORDY_EN 0x01000000
  565. #endif /* __CONFIG_H */