acadia.h 15 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /************************************************************************
  24. * acadia.h - configuration for AMCC Acadia (405EZ)
  25. ***********************************************************************/
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*-----------------------------------------------------------------------
  29. * High Level Configuration Options
  30. *----------------------------------------------------------------------*/
  31. #define CONFIG_ACADIA 1 /* Board is Acadia */
  32. #define CONFIG_4xx 1 /* ... PPC4xx family */
  33. #define CONFIG_405EZ 1 /* Specifc 405EZ support*/
  34. /*
  35. * Include common defines/options for all AMCC eval boards
  36. */
  37. #define CONFIG_HOSTNAME acadia
  38. #include "amcc-common.h"
  39. /* Detect Acadia PLL input clock automatically via CPLD bit */
  40. #define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \
  41. 66666666 : 33333000)
  42. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  43. #define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
  44. #define CONFIG_NO_SERIAL_EEPROM
  45. /*#undef CONFIG_NO_SERIAL_EEPROM*/
  46. #ifdef CONFIG_NO_SERIAL_EEPROM
  47. /*----------------------------------------------------------------------------
  48. * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
  49. * assuming a 66MHz input clock to the 405EZ.
  50. *---------------------------------------------------------------------------*/
  51. /* #define PLLMR0_100_100_12 */
  52. #define PLLMR0_200_133_66
  53. /* #define PLLMR0_266_160_80 */
  54. /* #define PLLMR0_333_166_83 */
  55. #endif
  56. /*-----------------------------------------------------------------------
  57. * Base addresses -- Note these are effective addresses where the
  58. * actual resources get mapped (not physical addresses)
  59. *----------------------------------------------------------------------*/
  60. #define CONFIG_SYS_FLASH_BASE 0xfe000000
  61. #define CONFIG_SYS_CPLD_BASE 0x80000000
  62. #define CONFIG_SYS_NAND_ADDR 0xd0000000
  63. #define CONFIG_SYS_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
  64. /*-----------------------------------------------------------------------
  65. * Initial RAM & stack pointer
  66. *----------------------------------------------------------------------*/
  67. #define CONFIG_SYS_TEMP_STACK_OCM 1 /* OCM as init ram */
  68. /* On Chip Memory location */
  69. #define CONFIG_SYS_OCM_DATA_ADDR 0xf8000000
  70. #define CONFIG_SYS_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
  71. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SRAM */
  72. #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
  73. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size for initial data */
  74. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  75. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  76. /*-----------------------------------------------------------------------
  77. * Serial Port
  78. *----------------------------------------------------------------------*/
  79. #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
  80. #define CONFIG_SYS_BASE_BAUD 691200
  81. /*-----------------------------------------------------------------------
  82. * Environment
  83. *----------------------------------------------------------------------*/
  84. #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  85. #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  86. #else
  87. #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
  88. #define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
  89. #endif
  90. /*-----------------------------------------------------------------------
  91. * FLASH related
  92. *----------------------------------------------------------------------*/
  93. #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  94. #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  95. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  96. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
  97. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  98. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
  99. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  100. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  101. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
  102. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  103. #else
  104. #define CONFIG_SYS_NO_FLASH 1 /* No NOR on Acadia when NAND-booting */
  105. #endif
  106. #ifdef CONFIG_ENV_IS_IN_FLASH
  107. #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
  108. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
  109. #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  110. /* Address and size of Redundant Environment Sector */
  111. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
  112. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  113. #endif
  114. /*
  115. * IPL (Initial Program Loader, integrated inside CPU)
  116. * Will load first 4k from NAND (SPL) into cache and execute it from there.
  117. *
  118. * SPL (Secondary Program Loader)
  119. * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
  120. * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
  121. * controller and the NAND controller so that the special U-Boot image can be
  122. * loaded from NAND to SDRAM.
  123. *
  124. * NUB (NAND U-Boot)
  125. * This NAND U-Boot (NUB) is a special U-Boot version which can be started
  126. * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
  127. *
  128. * On 440EPx the SPL is copied to SDRAM before the NAND controller is
  129. * set up. While still running from cache, I experienced problems accessing
  130. * the NAND controller. sr - 2006-08-25
  131. */
  132. #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
  133. #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
  134. #define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
  135. #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
  136. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
  137. #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
  138. /*
  139. * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
  140. */
  141. #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
  142. #define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
  143. /*
  144. * Now the NAND chip has to be defined (no autodetection used!)
  145. */
  146. #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
  147. #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
  148. #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
  149. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
  150. #undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
  151. #define CONFIG_SYS_NAND_ECCSIZE 256
  152. #define CONFIG_SYS_NAND_ECCBYTES 3
  153. #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
  154. #define CONFIG_SYS_NAND_OOBSIZE 16
  155. #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
  156. #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
  157. #ifdef CONFIG_ENV_IS_IN_NAND
  158. /*
  159. * For NAND booting the environment is embedded in the U-Boot image. Please take
  160. * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
  161. */
  162. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  163. #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
  164. #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
  165. #endif
  166. /*-----------------------------------------------------------------------
  167. * RAM (CRAM)
  168. *----------------------------------------------------------------------*/
  169. #define CONFIG_SYS_MBYTES_RAM 64 /* 64MB */
  170. /*-----------------------------------------------------------------------
  171. * I2C
  172. *----------------------------------------------------------------------*/
  173. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  174. #define CONFIG_SYS_I2C_MULTI_EEPROMS
  175. #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
  176. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  177. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  178. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  179. /* I2C SYSMON (LM75, AD7414 is almost compatible) */
  180. #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
  181. #define CONFIG_DTT_AD7414 1 /* use AD7414 */
  182. #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
  183. #define CONFIG_SYS_DTT_MAX_TEMP 70
  184. #define CONFIG_SYS_DTT_LOW_TEMP -30
  185. #define CONFIG_SYS_DTT_HYSTERESIS 3
  186. /*-----------------------------------------------------------------------
  187. * Ethernet
  188. *----------------------------------------------------------------------*/
  189. #define CONFIG_PHY_ADDR 0 /* PHY address */
  190. #define CONFIG_HAS_ETH0 1
  191. /*
  192. * Default environment variables
  193. */
  194. #define CONFIG_EXTRA_ENV_SETTINGS \
  195. CONFIG_AMCC_DEF_ENV \
  196. CONFIG_AMCC_DEF_ENV_POWERPC \
  197. CONFIG_AMCC_DEF_ENV_PPC_OLD \
  198. CONFIG_AMCC_DEF_ENV_NOR_UPD \
  199. CONFIG_AMCC_DEF_ENV_NAND_UPD \
  200. "kernel_addr=fff10000\0" \
  201. "ramdisk_addr=fff20000\0" \
  202. "kozio=bootm ffc60000\0" \
  203. ""
  204. #define CONFIG_USB_OHCI
  205. #define CONFIG_USB_STORAGE
  206. /* Partitions */
  207. #define CONFIG_MAC_PARTITION
  208. #define CONFIG_DOS_PARTITION
  209. #define CONFIG_ISO_PARTITION
  210. #define CONFIG_SUPPORT_VFAT
  211. /*
  212. * Commands additional to the ones defined in amcc-common.h
  213. */
  214. #define CONFIG_CMD_DTT
  215. #define CONFIG_CMD_NAND
  216. #define CONFIG_CMD_USB
  217. /*
  218. * No NOR on Acadia when NAND-booting
  219. */
  220. #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  221. #undef CONFIG_CMD_FLASH
  222. #undef CONFIG_CMD_IMLS
  223. #endif
  224. /*-----------------------------------------------------------------------
  225. * NAND FLASH
  226. *----------------------------------------------------------------------*/
  227. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  228. #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
  229. #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
  230. /*-----------------------------------------------------------------------
  231. * External Bus Controller (EBC) Setup
  232. *----------------------------------------------------------------------*/
  233. #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  234. #define CONFIG_SYS_NAND_CS 3
  235. /* Memory Bank 0 (Flash) initialization */
  236. #define CONFIG_SYS_EBC_PB0AP 0x03337200
  237. #define CONFIG_SYS_EBC_PB0CR 0xfe0bc000
  238. /* Memory Bank 3 (NAND-FLASH) initialization */
  239. #define CONFIG_SYS_EBC_PB3AP 0x018003c0
  240. #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
  241. /* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
  242. /* Memory Bank 1 (CRAM) initialization */
  243. #define CONFIG_SYS_EBC_PB1AP 0x030400c0
  244. #define CONFIG_SYS_EBC_PB1CR 0x000bc000
  245. /* Memory Bank 2 (CRAM) initialization */
  246. #define CONFIG_SYS_EBC_PB2AP 0x030400c0
  247. #define CONFIG_SYS_EBC_PB2CR 0x020bc000
  248. #else
  249. #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
  250. /* Memory Bank 0 (NAND-FLASH) initialization */
  251. #define CONFIG_SYS_EBC_PB0AP 0x018003c0
  252. #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
  253. /*
  254. * When NAND-booting the CRAM EBC setup must be done in sync mode, since the
  255. * NAND-SPL already initialized the CRAM and EBC to sync mode.
  256. */
  257. /* Memory Bank 1 (CRAM) initialization */
  258. #define CONFIG_SYS_EBC_PB1AP 0x9C0201C0
  259. #define CONFIG_SYS_EBC_PB1CR 0x000bc000
  260. /* Memory Bank 2 (CRAM) initialization */
  261. #define CONFIG_SYS_EBC_PB2AP 0x9C0201C0
  262. #define CONFIG_SYS_EBC_PB2CR 0x020bc000
  263. #endif
  264. /* Memory Bank 4 (CPLD) initialization */
  265. #define CONFIG_SYS_EBC_PB4AP 0x04006000
  266. #define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CPLD_BASE | 0x18000)
  267. #define CONFIG_SYS_EBC_CFG 0xf8400000
  268. /*-----------------------------------------------------------------------
  269. * GPIO Setup
  270. *----------------------------------------------------------------------*/
  271. #define CONFIG_SYS_GPIO_CRAM_CLK 8
  272. #define CONFIG_SYS_GPIO_CRAM_WAIT 9 /* GPIO-In */
  273. #define CONFIG_SYS_GPIO_CRAM_ADV 10
  274. #define CONFIG_SYS_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */
  275. /*-----------------------------------------------------------------------
  276. * Definitions for GPIO_0 setup (PPC405EZ specific)
  277. *
  278. * GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs
  279. * GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output
  280. * GPIO0[4] - External Bus Controller Hold Input
  281. * GPIO0[5] - External Bus Controller Priority Input
  282. * GPIO0[6] - External Bus Controller HLDA Output
  283. * GPIO0[7] - External Bus Controller Bus Request Output
  284. * GPIO0[8] - CRAM Clk Output
  285. * GPIO0[9] - External Bus Controller Ready Input
  286. * GPIO0[10] - CRAM Adv Output
  287. * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
  288. * GPIO0[25] - External DMA Request Input
  289. * GPIO0[26] - External DMA EOT I/O
  290. * GPIO0[25] - External DMA Ack_n Output
  291. * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  292. * GPIO0[28-30] - Trace Outputs / PWM Inputs
  293. * GPIO0[31] - PWM_8 I/O
  294. */
  295. #define CONFIG_SYS_GPIO0_TCR 0xC0A00000
  296. #define CONFIG_SYS_GPIO0_OSRL 0x50004400
  297. #define CONFIG_SYS_GPIO0_OSRH 0x02000055
  298. #define CONFIG_SYS_GPIO0_ISR1L 0x00001000
  299. #define CONFIG_SYS_GPIO0_ISR1H 0x00000055
  300. #define CONFIG_SYS_GPIO0_TSRL 0x02000000
  301. #define CONFIG_SYS_GPIO0_TSRH 0x00000055
  302. /*-----------------------------------------------------------------------
  303. * Definitions for GPIO_1 setup (PPC405EZ specific)
  304. *
  305. * GPIO1[0-6] - PWM_9 to PWM_15 I/O
  306. * GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input
  307. * GPIO1[8] - TS5 Output / DAC_IP_TRIG Input
  308. * GPIO1[9] - TS6 Output / ADC_IP_TRIG Input
  309. * GPIO1[10-12] - UART0 Control Inputs
  310. * GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
  311. * GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output
  312. * GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input
  313. * GPIO1[16] - SPI_SS_1_N Output
  314. * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
  315. */
  316. #define CONFIG_SYS_GPIO1_TCR 0xFFFF8414
  317. #define CONFIG_SYS_GPIO1_OSRL 0x40000110
  318. #define CONFIG_SYS_GPIO1_OSRH 0x55455555
  319. #define CONFIG_SYS_GPIO1_ISR1L 0x15555445
  320. #define CONFIG_SYS_GPIO1_ISR1H 0x00000000
  321. #define CONFIG_SYS_GPIO1_TSRL 0x00000000
  322. #define CONFIG_SYS_GPIO1_TSRH 0x00000000
  323. #endif /* __CONFIG_H */