XPEDITE5370.h 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600
  1. /*
  2. * Copyright 2008 Extreme Engineering Solutions, Inc.
  3. * Copyright 2007-2008 Freescale Semiconductor, Inc.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * xpedite5370 board configuration file
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. */
  31. #define CONFIG_BOOKE 1 /* BOOKE */
  32. #define CONFIG_E500 1 /* BOOKE e500 family */
  33. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
  34. #define CONFIG_MPC8572 1
  35. #define CONFIG_XPEDITE5370 1
  36. #define CONFIG_SYS_BOARD_NAME "XPedite5370"
  37. #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
  38. #define CONFIG_PCI 1 /* Enable PCI/PCIE */
  39. #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
  40. #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
  41. #define CONFIG_PCIE1 1 /* PCIE controler 1 */
  42. #define CONFIG_PCIE2 1 /* PCIE controler 2 */
  43. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  44. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  45. #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
  46. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  47. /*
  48. * Multicore config
  49. */
  50. #define CONFIG_MP
  51. #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
  52. #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
  53. /*
  54. * DDR config
  55. */
  56. #define CONFIG_FSL_DDR2
  57. #undef CONFIG_FSL_DDR_INTERACTIVE
  58. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  59. #define CONFIG_DDR_SPD
  60. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  61. #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
  62. #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
  63. #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
  64. #define CONFIG_NUM_DDR_CONTROLLERS 2
  65. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  66. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  67. #define CONFIG_DDR_ECC
  68. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  69. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  70. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  71. #define CONFIG_VERY_BIG_RAM
  72. #ifndef __ASSEMBLY__
  73. extern unsigned long get_board_sys_clk(unsigned long dummy);
  74. extern unsigned long get_board_ddr_clk(unsigned long dummy);
  75. #endif
  76. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
  77. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  78. /*
  79. * These can be toggled for performance analysis, otherwise use default.
  80. */
  81. #define CONFIG_L2_CACHE /* toggle L2 cache */
  82. #define CONFIG_BTB /* toggle branch predition */
  83. #define CONFIG_ENABLE_36BIT_PHYS 1
  84. /*
  85. * Base addresses -- Note these are effective addresses where the
  86. * actual resources get mapped (not physical addresses)
  87. */
  88. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  89. #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
  90. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
  91. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  92. #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
  93. #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
  94. /*
  95. * Diagnostics
  96. */
  97. #define CONFIG_SYS_ALT_MEMTEST
  98. #define CONFIG_SYS_MEMTEST_START 0x10000000
  99. #define CONFIG_SYS_MEMTEST_END 0x20000000
  100. /*
  101. * Memory map
  102. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  103. * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
  104. * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
  105. * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
  106. * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
  107. * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
  108. * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
  109. * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
  110. * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
  111. * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
  112. * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
  113. */
  114. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
  115. /*
  116. * NAND flash configuration
  117. */
  118. #define CONFIG_SYS_NAND_BASE 0xef800000
  119. #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
  120. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
  121. CONFIG_SYS_NAND_BASE2}
  122. #define CONFIG_SYS_MAX_NAND_DEVICE 2
  123. #define CONFIG_MTD_NAND_VERIFY_WRITE
  124. #define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
  125. #define CONFIG_NAND_FSL_ELBC
  126. /*
  127. * NOR flash configuration
  128. */
  129. #define CONFIG_SYS_FLASH_BASE 0xf8000000
  130. #define CONFIG_SYS_FLASH_BASE2 0xf0000000
  131. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  132. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  133. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  134. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  135. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  136. #define CONFIG_FLASH_CFI_DRIVER
  137. #define CONFIG_SYS_FLASH_CFI
  138. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  139. #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
  140. {0xf7f40000, 0xc0000} }
  141. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  142. /*
  143. * Chip select configuration
  144. */
  145. /* NOR Flash 0 on CS0 */
  146. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
  147. BR_PS_16 | \
  148. BR_V)
  149. #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
  150. OR_GPCM_CSNT | \
  151. OR_GPCM_XACS | \
  152. OR_GPCM_ACS_DIV2 | \
  153. OR_GPCM_SCY_8 | \
  154. OR_GPCM_TRLX | \
  155. OR_GPCM_EHTR | \
  156. OR_GPCM_EAD)
  157. /* NOR Flash 1 on CS1 */
  158. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
  159. BR_PS_16 | \
  160. BR_V)
  161. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  162. /* NAND flash on CS2 */
  163. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
  164. (2<<BR_DECC_SHIFT) | \
  165. BR_PS_8 | \
  166. BR_MS_FCM | \
  167. BR_V)
  168. /* NAND flash on CS2 */
  169. #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
  170. OR_FCM_PGS | \
  171. OR_FCM_CSCT | \
  172. OR_FCM_CST | \
  173. OR_FCM_CHT | \
  174. OR_FCM_SCY_1 | \
  175. OR_FCM_TRLX | \
  176. OR_FCM_EHTR)
  177. /* NAND flash on CS3 */
  178. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
  179. (2<<BR_DECC_SHIFT) | \
  180. BR_PS_8 | \
  181. BR_MS_FCM | \
  182. BR_V)
  183. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  184. /*
  185. * Use L1 as initial stack
  186. */
  187. #define CONFIG_SYS_INIT_RAM_LOCK 1
  188. #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
  189. #define CONFIG_SYS_INIT_RAM_END 0x00004000
  190. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  191. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  192. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  193. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  194. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  195. /*
  196. * Serial Port
  197. */
  198. #define CONFIG_CONS_INDEX 1
  199. #define CONFIG_SYS_NS16550
  200. #define CONFIG_SYS_NS16550_SERIAL
  201. #define CONFIG_SYS_NS16550_REG_SIZE 1
  202. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  203. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  204. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  205. #define CONFIG_SYS_BAUDRATE_TABLE \
  206. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  207. #define CONFIG_BAUDRATE 115200
  208. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  209. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  210. /*
  211. * Use the HUSH parser
  212. */
  213. #define CONFIG_SYS_HUSH_PARSER
  214. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  215. /*
  216. * Pass open firmware flat tree
  217. */
  218. #define CONFIG_OF_LIBFDT 1
  219. #define CONFIG_OF_BOARD_SETUP 1
  220. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  221. /*
  222. * I2C
  223. */
  224. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  225. #define CONFIG_HARD_I2C /* I2C with hardware support */
  226. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  227. #define CONFIG_SYS_I2C_SLAVE 0x7F
  228. #define CONFIG_SYS_I2C_OFFSET 0x3000
  229. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  230. #define CONFIG_I2C_MULTI_BUS
  231. /* PEX8518 slave I2C interface */
  232. #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
  233. /* I2C DS1631 temperature sensor */
  234. #define CONFIG_SYS_I2C_DS1621_ADDR 0x48
  235. #define CONFIG_DTT_DS1621
  236. #define CONFIG_DTT_SENSORS { 0 }
  237. /* I2C EEPROM - AT24C128B */
  238. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
  239. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  240. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
  241. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
  242. /* I2C RTC */
  243. #define CONFIG_RTC_M41T11 1
  244. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  245. #define CONFIG_SYS_M41T11_BASE_YEAR 2000
  246. /* GPIO/EEPROM/SRAM */
  247. #define CONFIG_DS4510
  248. #define CONFIG_SYS_I2C_DS4510_ADDR 0x51
  249. /* GPIO */
  250. #define CONFIG_PCA953X
  251. #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
  252. #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
  253. #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
  254. #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
  255. #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
  256. /*
  257. * PU = pulled high, PD = pulled low
  258. * I = input, O = output, IO = input/output
  259. */
  260. /* PCA9557 @ 0x18*/
  261. #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
  262. #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
  263. #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
  264. #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
  265. #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
  266. #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
  267. #define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */
  268. #define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */
  269. /* PCA9557 @ 0x1c*/
  270. #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
  271. #define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */
  272. #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
  273. #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
  274. #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
  275. #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
  276. #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
  277. #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
  278. /* PCA9557 @ 0x1e*/
  279. #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
  280. #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
  281. #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
  282. #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
  283. #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
  284. #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */
  285. #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
  286. /* PCA9557 @ 0x1f */
  287. #define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */
  288. #define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */
  289. #define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */
  290. #define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */
  291. #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */
  292. /*
  293. * General PCI
  294. * Memory space is mapped 1-1, but I/O space must start from 0.
  295. */
  296. /* PCIE1 - VPX P1 */
  297. #define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
  298. #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
  299. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
  300. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  301. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
  302. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  303. /* PCIE2 - PEX8518 */
  304. #define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
  305. #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
  306. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  307. #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
  308. #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
  309. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
  310. /*
  311. * Networking options
  312. */
  313. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  314. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  315. #define CONFIG_NET_MULTI 1
  316. #define CONFIG_TSEC_TBI
  317. #define CONFIG_MII 1 /* MII PHY management */
  318. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  319. #define CONFIG_ETHPRIME "eTSEC2"
  320. #define CONFIG_TSEC1 1
  321. #define CONFIG_TSEC1_NAME "eTSEC1"
  322. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  323. #define TSEC1_PHY_ADDR 1
  324. #define TSEC1_PHYIDX 0
  325. #define CONFIG_HAS_ETH0
  326. #define CONFIG_TSEC2 1
  327. #define CONFIG_TSEC2_NAME "eTSEC2"
  328. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  329. #define TSEC2_PHY_ADDR 2
  330. #define TSEC2_PHYIDX 0
  331. #define CONFIG_HAS_ETH1
  332. /*
  333. * Command configuration.
  334. */
  335. #include <config_cmd_default.h>
  336. #define CONFIG_CMD_ASKENV
  337. #define CONFIG_CMD_DATE
  338. #define CONFIG_CMD_DHCP
  339. #define CONFIG_CMD_DS4510
  340. #define CONFIG_CMD_DS4510_INFO
  341. #define CONFIG_CMD_DTT
  342. #define CONFIG_CMD_EEPROM
  343. #define CONFIG_CMD_ELF
  344. #define CONFIG_CMD_FLASH
  345. #define CONFIG_CMD_I2C
  346. #define CONFIG_CMD_JFFS2
  347. #define CONFIG_CMD_MII
  348. #define CONFIG_CMD_NAND
  349. #define CONFIG_CMD_NET
  350. #define CONFIG_CMD_PCA953X
  351. #define CONFIG_CMD_PCA953X_INFO
  352. #define CONFIG_CMD_PCI
  353. #define CONFIG_CMD_PING
  354. #define CONFIG_CMD_SAVEENV
  355. #define CONFIG_CMD_SNTP
  356. /*
  357. * Miscellaneous configurable options
  358. */
  359. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  360. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  361. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  362. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  363. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  364. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  365. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  366. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  367. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  368. #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
  369. #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
  370. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  371. #define CONFIG_PREBOOT /* enable preboot variable */
  372. #define CONFIG_FIT 1
  373. #define CONFIG_FIT_VERBOSE 1
  374. #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
  375. /*
  376. * For booting Linux, the board info and command line data
  377. * have to be in the first 16 MB of memory, since this is
  378. * the maximum mapped by the Linux kernel during initialization.
  379. */
  380. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  381. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  382. /*
  383. * Boot Flags
  384. */
  385. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  386. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  387. /*
  388. * Environment Configuration
  389. */
  390. #define CONFIG_ENV_IS_IN_FLASH 1
  391. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
  392. #define CONFIG_ENV_SIZE 0x8000
  393. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
  394. /*
  395. * Flash memory map:
  396. * fff80000 - ffffffff Pri U-Boot (512 KB)
  397. * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
  398. * fff00000 - fff3ffff Pri FDT (256KB)
  399. * fef00000 - ffefffff Pri OS image (16MB)
  400. * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
  401. *
  402. * f7f80000 - f7ffffff Sec U-Boot (512 KB)
  403. * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
  404. * f7f00000 - f7f3ffff Sec FDT (256KB)
  405. * f6f00000 - f7efffff Sec OS image (16MB)
  406. * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
  407. */
  408. #define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
  409. #define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
  410. #define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
  411. #define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
  412. #define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
  413. #define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
  414. #define CONFIG_PROG_UBOOT1 \
  415. "$download_cmd $loadaddr $ubootfile; " \
  416. "if test $? -eq 0; then " \
  417. "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  418. "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  419. "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
  420. "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  421. "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
  422. "if test $? -ne 0; then " \
  423. "echo PROGRAM FAILED; " \
  424. "else; " \
  425. "echo PROGRAM SUCCEEDED; " \
  426. "fi; " \
  427. "else; " \
  428. "echo DOWNLOAD FAILED; " \
  429. "fi;"
  430. #define CONFIG_PROG_UBOOT2 \
  431. "$download_cmd $loadaddr $ubootfile; " \
  432. "if test $? -eq 0; then " \
  433. "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  434. "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  435. "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
  436. "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  437. "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
  438. "if test $? -ne 0; then " \
  439. "echo PROGRAM FAILED; " \
  440. "else; " \
  441. "echo PROGRAM SUCCEEDED; " \
  442. "fi; " \
  443. "else; " \
  444. "echo DOWNLOAD FAILED; " \
  445. "fi;"
  446. #define CONFIG_BOOT_OS_NET \
  447. "$download_cmd $osaddr $osfile; " \
  448. "if test $? -eq 0; then " \
  449. "if test -n $fdtaddr; then " \
  450. "$download_cmd $fdtaddr $fdtfile; " \
  451. "if test $? -eq 0; then " \
  452. "bootm $osaddr - $fdtaddr; " \
  453. "else; " \
  454. "echo FDT DOWNLOAD FAILED; " \
  455. "fi; " \
  456. "else; " \
  457. "bootm $osaddr; " \
  458. "fi; " \
  459. "else; " \
  460. "echo OS DOWNLOAD FAILED; " \
  461. "fi;"
  462. #define CONFIG_PROG_OS1 \
  463. "$download_cmd $osaddr $osfile; " \
  464. "if test $? -eq 0; then " \
  465. "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
  466. "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  467. "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  468. "if test $? -ne 0; then " \
  469. "echo OS PROGRAM FAILED; " \
  470. "else; " \
  471. "echo OS PROGRAM SUCCEEDED; " \
  472. "fi; " \
  473. "else; " \
  474. "echo OS DOWNLOAD FAILED; " \
  475. "fi;"
  476. #define CONFIG_PROG_OS2 \
  477. "$download_cmd $osaddr $osfile; " \
  478. "if test $? -eq 0; then " \
  479. "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
  480. "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  481. "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  482. "if test $? -ne 0; then " \
  483. "echo OS PROGRAM FAILED; " \
  484. "else; " \
  485. "echo OS PROGRAM SUCCEEDED; " \
  486. "fi; " \
  487. "else; " \
  488. "echo OS DOWNLOAD FAILED; " \
  489. "fi;"
  490. #define CONFIG_PROG_FDT1 \
  491. "$download_cmd $fdtaddr $fdtfile; " \
  492. "if test $? -eq 0; then " \
  493. "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
  494. "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  495. "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  496. "if test $? -ne 0; then " \
  497. "echo FDT PROGRAM FAILED; " \
  498. "else; " \
  499. "echo FDT PROGRAM SUCCEEDED; " \
  500. "fi; " \
  501. "else; " \
  502. "echo FDT DOWNLOAD FAILED; " \
  503. "fi;"
  504. #define CONFIG_PROG_FDT2 \
  505. "$download_cmd $fdtaddr $fdtfile; " \
  506. "if test $? -eq 0; then " \
  507. "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
  508. "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  509. "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  510. "if test $? -ne 0; then " \
  511. "echo FDT PROGRAM FAILED; " \
  512. "else; " \
  513. "echo FDT PROGRAM SUCCEEDED; " \
  514. "fi; " \
  515. "else; " \
  516. "echo FDT DOWNLOAD FAILED; " \
  517. "fi;"
  518. #define CONFIG_EXTRA_ENV_SETTINGS \
  519. "autoload=yes\0" \
  520. "download_cmd=tftp\0" \
  521. "console_args=console=ttyS0,115200\0" \
  522. "root_args=root=/dev/nfs rw\0" \
  523. "misc_args=ip=on\0" \
  524. "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
  525. "bootfile=/home/user/file\0" \
  526. "osfile=/home/user/uImage-XPedite5370\0" \
  527. "fdtfile=/home/user/xpedite5370.dtb\0" \
  528. "ubootfile=/home/user/u-boot.bin\0" \
  529. "fdtaddr=c00000\0" \
  530. "osaddr=0x1000000\0" \
  531. "loadaddr=0x1000000\0" \
  532. "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
  533. "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
  534. "prog_os1="CONFIG_PROG_OS1"\0" \
  535. "prog_os2="CONFIG_PROG_OS2"\0" \
  536. "prog_fdt1="CONFIG_PROG_FDT1"\0" \
  537. "prog_fdt2="CONFIG_PROG_FDT2"\0" \
  538. "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
  539. "bootcmd_flash1=run set_bootargs; " \
  540. "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
  541. "bootcmd_flash2=run set_bootargs; " \
  542. "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
  543. "bootcmd=run bootcmd_flash1\0"
  544. #endif /* __CONFIG_H */