XPEDITE5200.h 17 KB

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  1. /*
  2. * Copyright 2008 Extreme Engineering Solutions, Inc.
  3. * Copyright 2004-2008 Freescale Semiconductor, Inc.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * xpedite5200 board configuration file
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. */
  31. #define CONFIG_BOOKE 1 /* BOOKE */
  32. #define CONFIG_E500 1 /* BOOKE e500 family */
  33. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
  34. #define CONFIG_MPC8548 1
  35. #define CONFIG_XPEDITE5200 1
  36. #define CONFIG_SYS_BOARD_NAME "XPedite5200"
  37. #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
  38. #define CONFIG_PCI 1 /* Enable PCI/PCIE */
  39. #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
  40. #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
  41. #define CONFIG_PCI1 1 /* PCI controller 1 */
  42. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  43. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  44. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  45. /*
  46. * DDR config
  47. */
  48. #define CONFIG_FSL_DDR2
  49. #undef CONFIG_FSL_DDR_INTERACTIVE
  50. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  51. #define CONFIG_DDR_SPD
  52. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  53. #define SPD_EEPROM_ADDRESS 0x54
  54. #define CONFIG_NUM_DDR_CONTROLLERS 1
  55. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  56. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  57. #define CONFIG_DDR_ECC
  58. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  59. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  60. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  61. #define CONFIG_VERY_BIG_RAM
  62. #define CONFIG_SYS_CLK_FREQ 66666666
  63. /*
  64. * These can be toggled for performance analysis, otherwise use default.
  65. */
  66. #define CONFIG_L2_CACHE /* toggle L2 cache */
  67. #define CONFIG_BTB /* toggle branch predition */
  68. #define CONFIG_ENABLE_36BIT_PHYS 1
  69. /*
  70. * Base addresses -- Note these are effective addresses where the
  71. * actual resources get mapped (not physical addresses)
  72. */
  73. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  74. #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
  75. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
  76. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  77. #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
  78. /*
  79. * Diagnostics
  80. */
  81. #define CONFIG_SYS_ALT_MEMTEST
  82. #define CONFIG_SYS_MEMTEST_START 0x10000000
  83. #define CONFIG_SYS_MEMTEST_END 0x20000000
  84. /*
  85. * Memory map
  86. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  87. * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
  88. * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
  89. * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
  90. * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
  91. * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
  92. * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
  93. * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
  94. */
  95. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
  96. /*
  97. * NAND flash configuration
  98. */
  99. #define CONFIG_SYS_NAND_BASE 0xef800000
  100. #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
  101. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  102. #define CONFIG_NAND_ACTL
  103. #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
  104. #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
  105. #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
  106. #define CONFIG_SYS_NAND_ACTL_DELAY 25
  107. /*
  108. * NOR flash configuration
  109. */
  110. #define CONFIG_SYS_FLASH_BASE 0xfc000000
  111. #define CONFIG_SYS_FLASH_BASE2 0xf8000000
  112. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  113. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  114. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  115. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  116. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  117. #define CONFIG_FLASH_CFI_DRIVER
  118. #define CONFIG_SYS_FLASH_CFI
  119. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  120. #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
  121. {0xfbf40000, 0xc0000} }
  122. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  123. /*
  124. * Chip select configuration
  125. */
  126. /* NOR Flash 0 on CS0 */
  127. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
  128. BR_PS_16 | \
  129. BR_V)
  130. #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
  131. OR_GPCM_ACS_DIV4 | \
  132. OR_GPCM_SCY_8)
  133. /* NOR Flash 1 on CS1 */
  134. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
  135. BR_PS_16 | \
  136. BR_V)
  137. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  138. /* NAND flash on CS2 */
  139. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
  140. BR_PS_8 | \
  141. BR_V)
  142. /* NAND flash on CS2 */
  143. #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
  144. OR_GPCM_BCTLD | \
  145. OR_GPCM_CSNT | \
  146. OR_GPCM_ACS_DIV4 | \
  147. OR_GPCM_SCY_4 | \
  148. OR_GPCM_TRLX | \
  149. OR_GPCM_EHTR)
  150. /* NAND flash on CS3 */
  151. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
  152. BR_PS_8 | \
  153. BR_V)
  154. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  155. /*
  156. * Use L1 as initial stack
  157. */
  158. #define CONFIG_SYS_INIT_RAM_LOCK 1
  159. #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
  160. #define CONFIG_SYS_INIT_RAM_END 0x4000
  161. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  162. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  163. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  164. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  165. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  166. /*
  167. * Serial Port
  168. */
  169. #define CONFIG_CONS_INDEX 1
  170. #define CONFIG_SYS_NS16550
  171. #define CONFIG_SYS_NS16550_SERIAL
  172. #define CONFIG_SYS_NS16550_REG_SIZE 1
  173. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  174. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  175. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  176. #define CONFIG_SYS_BAUDRATE_TABLE \
  177. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  178. #define CONFIG_BAUDRATE 115200
  179. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  180. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  181. /*
  182. * Use the HUSH parser
  183. */
  184. #define CONFIG_SYS_HUSH_PARSER
  185. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  186. /*
  187. * Pass open firmware flat tree
  188. */
  189. #define CONFIG_OF_LIBFDT 1
  190. #define CONFIG_OF_BOARD_SETUP 1
  191. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  192. /*
  193. * I2C
  194. */
  195. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  196. #define CONFIG_HARD_I2C /* I2C with hardware support */
  197. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  198. #define CONFIG_SYS_I2C_SLAVE 0x7F
  199. #define CONFIG_SYS_I2C_OFFSET 0x3000
  200. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  201. #define CONFIG_I2C_MULTI_BUS
  202. /* I2C EEPROM */
  203. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  204. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  205. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
  206. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
  207. /* I2C RTC */
  208. #define CONFIG_RTC_M41T11 1
  209. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  210. #define CONFIG_SYS_M41T11_BASE_YEAR 2000
  211. /* GPIO */
  212. #define CONFIG_PCA953X
  213. #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
  214. #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
  215. #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
  216. /* PCA957 @ 0x18 */
  217. #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
  218. #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
  219. #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
  220. #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
  221. #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
  222. #define CONFIG_SYS_PCA953X_FLASH_WP 0x20
  223. #define CONFIG_SYS_PCA953X_MONARCH 0x40
  224. #define CONFIG_SYS_PCA953X_EREADY 0x80
  225. /* PCA957 @ 0x19 */
  226. #define CONFIG_SYS_PCA953X_P14_IO0 0x01
  227. #define CONFIG_SYS_PCA953X_P14_IO1 0x02
  228. #define CONFIG_SYS_PCA953X_P14_IO2 0x04
  229. #define CONFIG_SYS_PCA953X_P14_IO3 0x08
  230. #define CONFIG_SYS_PCA953X_P14_IO4 0x10
  231. #define CONFIG_SYS_PCA953X_P14_IO5 0x20
  232. #define CONFIG_SYS_PCA953X_P14_IO6 0x40
  233. #define CONFIG_SYS_PCA953X_P14_IO7 0x80
  234. /*
  235. * General PCI
  236. * Memory space is mapped 1-1, but I/O space must start from 0.
  237. */
  238. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  239. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  240. #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
  241. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  242. #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
  243. #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
  244. /*
  245. * Networking options
  246. */
  247. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  248. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  249. #define CONFIG_NET_MULTI 1
  250. #define CONFIG_MII 1 /* MII PHY management */
  251. #define CONFIG_ETHPRIME "eTSEC1"
  252. #define CONFIG_TSEC1 1
  253. #define CONFIG_TSEC1_NAME "eTSEC1"
  254. #define TSEC1_FLAGS TSEC_GIGABIT
  255. #define TSEC1_PHY_ADDR 1
  256. #define TSEC1_PHYIDX 0
  257. #define CONFIG_HAS_ETH0
  258. #define CONFIG_TSEC2 1
  259. #define CONFIG_TSEC2_NAME "eTSEC2"
  260. #define TSEC2_FLAGS TSEC_GIGABIT
  261. #define TSEC2_PHY_ADDR 2
  262. #define TSEC2_PHYIDX 0
  263. #define CONFIG_HAS_ETH1
  264. #define CONFIG_TSEC3 1
  265. #define CONFIG_TSEC3_NAME "eTSEC3"
  266. #define TSEC3_FLAGS TSEC_GIGABIT
  267. #define TSEC3_PHY_ADDR 3
  268. #define TSEC3_PHYIDX 0
  269. #define CONFIG_HAS_ETH2
  270. #define CONFIG_TSEC4 1
  271. #define CONFIG_TSEC4_NAME "eTSEC4"
  272. #define TSEC4_FLAGS TSEC_GIGABIT
  273. #define TSEC4_PHY_ADDR 4
  274. #define TSEC4_PHYIDX 0
  275. #define CONFIG_HAS_ETH3
  276. /*
  277. * BOOTP options
  278. */
  279. #define CONFIG_BOOTP_BOOTFILESIZE
  280. #define CONFIG_BOOTP_BOOTPATH
  281. #define CONFIG_BOOTP_GATEWAY
  282. /*
  283. * Command configuration.
  284. */
  285. #include <config_cmd_default.h>
  286. #define CONFIG_CMD_ASKENV
  287. #define CONFIG_CMD_DATE
  288. #define CONFIG_CMD_DHCP
  289. #define CONFIG_CMD_EEPROM
  290. #define CONFIG_CMD_ELF
  291. #define CONFIG_CMD_SAVEENV
  292. #define CONFIG_CMD_FLASH
  293. #define CONFIG_CMD_I2C
  294. #define CONFIG_CMD_JFFS2
  295. #define CONFIG_CMD_MII
  296. #define CONFIG_CMD_NAND
  297. #define CONFIG_CMD_NET
  298. #define CONFIG_CMD_PCA953X
  299. #define CONFIG_CMD_PCA953X_INFO
  300. #define CONFIG_CMD_PCI
  301. #define CONFIG_CMD_PING
  302. #define CONFIG_CMD_SNTP
  303. /*
  304. * Miscellaneous configurable options
  305. */
  306. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  307. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  308. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  309. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  310. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  311. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  312. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  313. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  314. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  315. #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
  316. #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
  317. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  318. #define CONFIG_PREBOOT /* enable preboot variable */
  319. #define CONFIG_FIT 1
  320. #define CONFIG_FIT_VERBOSE 1
  321. #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
  322. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  323. /*
  324. * For booting Linux, the board info and command line data
  325. * have to be in the first 16 MB of memory, since this is
  326. * the maximum mapped by the Linux kernel during initialization.
  327. */
  328. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  329. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  330. /*
  331. * Boot Flags
  332. */
  333. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  334. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  335. /*
  336. * Environment Configuration
  337. */
  338. #define CONFIG_ENV_IS_IN_FLASH 1
  339. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
  340. #define CONFIG_ENV_SIZE 0x8000
  341. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
  342. /*
  343. * Flash memory map:
  344. * fff80000 - ffffffff Pri U-Boot (512 KB)
  345. * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
  346. * fff00000 - fff3ffff Pri FDT (256KB)
  347. * fef00000 - ffefffff Pri OS image (16MB)
  348. * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
  349. *
  350. * fbf80000 - fbffffff Sec U-Boot (512 KB)
  351. * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
  352. * fbf00000 - fbf3ffff Sec FDT (256KB)
  353. * faf00000 - fbefffff Sec OS image (16MB)
  354. * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
  355. */
  356. #define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
  357. #define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000)
  358. #define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
  359. #define CONFIG_FDT2_ENV_ADDR MK_STR(0xfbf00000)
  360. #define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
  361. #define CONFIG_OS2_ENV_ADDR MK_STR(0xfaf00000)
  362. #define CONFIG_PROG_UBOOT1 \
  363. "$download_cmd $loadaddr $ubootfile; " \
  364. "if test $? -eq 0; then " \
  365. "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  366. "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  367. "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
  368. "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  369. "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
  370. "if test $? -ne 0; then " \
  371. "echo PROGRAM FAILED; " \
  372. "else; " \
  373. "echo PROGRAM SUCCEEDED; " \
  374. "fi; " \
  375. "else; " \
  376. "echo DOWNLOAD FAILED; " \
  377. "fi;"
  378. #define CONFIG_PROG_UBOOT2 \
  379. "$download_cmd $loadaddr $ubootfile; " \
  380. "if test $? -eq 0; then " \
  381. "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  382. "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  383. "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
  384. "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  385. "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
  386. "if test $? -ne 0; then " \
  387. "echo PROGRAM FAILED; " \
  388. "else; " \
  389. "echo PROGRAM SUCCEEDED; " \
  390. "fi; " \
  391. "else; " \
  392. "echo DOWNLOAD FAILED; " \
  393. "fi;"
  394. #define CONFIG_BOOT_OS_NET \
  395. "$download_cmd $osaddr $osfile; " \
  396. "if test $? -eq 0; then " \
  397. "if test -n $fdtaddr; then " \
  398. "$download_cmd $fdtaddr $fdtfile; " \
  399. "if test $? -eq 0; then " \
  400. "bootm $osaddr - $fdtaddr; " \
  401. "else; " \
  402. "echo FDT DOWNLOAD FAILED; " \
  403. "fi; " \
  404. "else; " \
  405. "bootm $osaddr; " \
  406. "fi; " \
  407. "else; " \
  408. "echo OS DOWNLOAD FAILED; " \
  409. "fi;"
  410. #define CONFIG_PROG_OS1 \
  411. "$download_cmd $osaddr $osfile; " \
  412. "if test $? -eq 0; then " \
  413. "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
  414. "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  415. "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  416. "if test $? -ne 0; then " \
  417. "echo OS PROGRAM FAILED; " \
  418. "else; " \
  419. "echo OS PROGRAM SUCCEEDED; " \
  420. "fi; " \
  421. "else; " \
  422. "echo OS DOWNLOAD FAILED; " \
  423. "fi;"
  424. #define CONFIG_PROG_OS2 \
  425. "$download_cmd $osaddr $osfile; " \
  426. "if test $? -eq 0; then " \
  427. "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
  428. "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  429. "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  430. "if test $? -ne 0; then " \
  431. "echo OS PROGRAM FAILED; " \
  432. "else; " \
  433. "echo OS PROGRAM SUCCEEDED; " \
  434. "fi; " \
  435. "else; " \
  436. "echo OS DOWNLOAD FAILED; " \
  437. "fi;"
  438. #define CONFIG_PROG_FDT1 \
  439. "$download_cmd $fdtaddr $fdtfile; " \
  440. "if test $? -eq 0; then " \
  441. "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
  442. "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  443. "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  444. "if test $? -ne 0; then " \
  445. "echo FDT PROGRAM FAILED; " \
  446. "else; " \
  447. "echo FDT PROGRAM SUCCEEDED; " \
  448. "fi; " \
  449. "else; " \
  450. "echo FDT DOWNLOAD FAILED; " \
  451. "fi;"
  452. #define CONFIG_PROG_FDT2 \
  453. "$download_cmd $fdtaddr $fdtfile; " \
  454. "if test $? -eq 0; then " \
  455. "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
  456. "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  457. "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  458. "if test $? -ne 0; then " \
  459. "echo FDT PROGRAM FAILED; " \
  460. "else; " \
  461. "echo FDT PROGRAM SUCCEEDED; " \
  462. "fi; " \
  463. "else; " \
  464. "echo FDT DOWNLOAD FAILED; " \
  465. "fi;"
  466. #define CONFIG_EXTRA_ENV_SETTINGS \
  467. "autoload=yes\0" \
  468. "download_cmd=tftp\0" \
  469. "console_args=console=ttyS0,115200\0" \
  470. "root_args=root=/dev/nfs rw\0" \
  471. "misc_args=ip=on\0" \
  472. "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
  473. "bootfile=/home/user/file\0" \
  474. "osfile=/home/user/uImage-XPedite5200\0" \
  475. "fdtfile=/home/user/xpedite5200.dtb\0" \
  476. "ubootfile=/home/user/u-boot.bin\0" \
  477. "fdtaddr=c00000\0" \
  478. "osaddr=0x1000000\0" \
  479. "loadaddr=0x1000000\0" \
  480. "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
  481. "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
  482. "prog_os1="CONFIG_PROG_OS1"\0" \
  483. "prog_os2="CONFIG_PROG_OS2"\0" \
  484. "prog_fdt1="CONFIG_PROG_FDT1"\0" \
  485. "prog_fdt2="CONFIG_PROG_FDT2"\0" \
  486. "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
  487. "bootcmd_flash1=run set_bootargs; " \
  488. "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
  489. "bootcmd_flash2=run set_bootargs; " \
  490. "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
  491. "bootcmd=run bootcmd_flash1\0"
  492. #endif /* __CONFIG_H */