XPEDITE5170.h 24 KB

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  1. /*
  2. * Copyright 2009 Extreme Engineering Solutions, Inc.
  3. * Copyright 2007-2008 Freescale Semiconductor, Inc.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * xpedite5170 board configuration file
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. */
  31. #define CONFIG_MPC86xx 1 /* MPC86xx */
  32. #define CONFIG_MPC8641 1 /* MPC8641 specific */
  33. #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
  34. #define CONFIG_SYS_BOARD_NAME "XPedite5170"
  35. #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
  36. #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
  37. #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
  38. #define CONFIG_ALTIVEC 1
  39. #define CONFIG_PCI 1 /* Enable PCI/PCIE */
  40. #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
  41. #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
  42. #define CONFIG_PCIE1 1 /* PCIE controler 1 */
  43. #define CONFIG_PCIE2 1 /* PCIE controler 2 */
  44. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  45. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  46. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  47. /*
  48. * DDR config
  49. */
  50. #define CONFIG_FSL_DDR2
  51. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  52. #define CONFIG_DDR_SPD
  53. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  54. #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
  55. #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
  56. #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
  57. #define CONFIG_NUM_DDR_CONTROLLERS 2
  58. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  59. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  60. #define CONFIG_DDR_ECC
  61. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  62. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  63. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  64. #define CONFIG_VERY_BIG_RAM
  65. #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
  66. /*
  67. * virtual address to be used for temporary mappings. There
  68. * should be 128k free at this VA.
  69. */
  70. #define CONFIG_SYS_SCRATCH_VA 0xe0000000
  71. #ifndef __ASSEMBLY__
  72. extern unsigned long get_board_sys_clk(unsigned long dummy);
  73. #endif
  74. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
  75. /*
  76. * L2CR setup
  77. */
  78. #define CONFIG_SYS_L2
  79. #define L2_INIT 0
  80. #define L2_ENABLE (L2CR_L2E)
  81. /*
  82. * Base addresses -- Note these are effective addresses where the
  83. * actual resources get mapped (not physical addresses)
  84. */
  85. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  86. #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
  87. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
  88. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  89. #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
  90. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
  91. #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
  92. #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
  93. /*
  94. * Diagnostics
  95. */
  96. #define CONFIG_SYS_ALT_MEMTEST
  97. #define CONFIG_SYS_MEMTEST_START 0x10000000
  98. #define CONFIG_SYS_MEMTEST_END 0x20000000
  99. /*
  100. * Memory map
  101. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  102. * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
  103. * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
  104. * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
  105. * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
  106. * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
  107. * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
  108. * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
  109. * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
  110. * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
  111. */
  112. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
  113. /*
  114. * NAND flash configuration
  115. */
  116. #define CONFIG_SYS_NAND_BASE 0xef800000
  117. #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
  118. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
  119. #define CONFIG_SYS_MAX_NAND_DEVICE 2
  120. #define CONFIG_NAND_ACTL
  121. #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
  122. #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
  123. #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
  124. #define CONFIG_SYS_NAND_ACTL_DELAY 25
  125. #define CONFIG_SYS_NAND_QUIET_TEST
  126. #define CONFIG_JFFS2_NAND
  127. /*
  128. * NOR flash configuration
  129. */
  130. #define CONFIG_SYS_FLASH_BASE 0xf8000000
  131. #define CONFIG_SYS_FLASH_BASE2 0xf0000000
  132. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  133. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  134. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  135. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  136. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  137. #define CONFIG_FLASH_CFI_DRIVER
  138. #define CONFIG_SYS_FLASH_CFI
  139. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  140. #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
  141. {0xf7f00000, 0xc0000} }
  142. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  143. #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
  144. /*
  145. * Chip select configuration
  146. */
  147. /* NOR Flash 0 on CS0 */
  148. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
  149. BR_PS_16 |\
  150. BR_V)
  151. #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
  152. OR_GPCM_CSNT |\
  153. OR_GPCM_XACS |\
  154. OR_GPCM_ACS_DIV2 |\
  155. OR_GPCM_SCY_8 |\
  156. OR_GPCM_TRLX |\
  157. OR_GPCM_EHTR |\
  158. OR_GPCM_EAD)
  159. /* NOR Flash 1 on CS1 */
  160. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
  161. BR_PS_16 |\
  162. BR_V)
  163. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  164. /* NAND flash on CS2 */
  165. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
  166. BR_PS_8 |\
  167. BR_V)
  168. #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
  169. OR_GPCM_BCTLD |\
  170. OR_GPCM_CSNT |\
  171. OR_GPCM_ACS_DIV4 |\
  172. OR_GPCM_SCY_4 |\
  173. OR_GPCM_TRLX |\
  174. OR_GPCM_EHTR)
  175. /* Optional NAND flash on CS3 */
  176. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
  177. BR_PS_8 |\
  178. BR_V)
  179. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  180. /*
  181. * Use L1 as initial stack
  182. */
  183. #define CONFIG_SYS_INIT_RAM_LOCK 1
  184. #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
  185. #define CONFIG_SYS_INIT_RAM_END 0x00004000
  186. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  187. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  188. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  189. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  190. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  191. /*
  192. * Serial Port
  193. */
  194. #define CONFIG_CONS_INDEX 1
  195. #define CONFIG_SYS_NS16550
  196. #define CONFIG_SYS_NS16550_SERIAL
  197. #define CONFIG_SYS_NS16550_REG_SIZE 1
  198. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  199. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  200. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  201. #define CONFIG_SYS_BAUDRATE_TABLE \
  202. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  203. #define CONFIG_BAUDRATE 115200
  204. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  205. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  206. /*
  207. * Use the HUSH parser
  208. */
  209. #define CONFIG_SYS_HUSH_PARSER
  210. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  211. /*
  212. * Pass open firmware flat tree
  213. */
  214. #define CONFIG_OF_LIBFDT 1
  215. #define CONFIG_OF_BOARD_SETUP 1
  216. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  217. /*
  218. * I2C
  219. */
  220. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  221. #define CONFIG_HARD_I2C /* I2C with hardware support */
  222. #define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */
  223. #define CONFIG_SYS_I2C_SLAVE 0x7F
  224. #define CONFIG_SYS_I2C_OFFSET 0x3000
  225. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  226. #define CONFIG_I2C_MULTI_BUS
  227. /* PEX8518 slave I2C interface */
  228. #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
  229. /* I2C DS1631 temperature sensor */
  230. #define CONFIG_SYS_I2C_DS1621_ADDR 0x48
  231. #define CONFIG_DTT_DS1621
  232. #define CONFIG_DTT_SENSORS { 0 }
  233. /* I2C EEPROM - AT24C128B */
  234. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
  235. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  236. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
  237. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
  238. /* I2C RTC */
  239. #define CONFIG_RTC_M41T11 1
  240. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  241. #define CONFIG_SYS_M41T11_BASE_YEAR 2000
  242. /* GPIO/EEPROM/SRAM */
  243. #define CONFIG_DS4510
  244. #define CONFIG_SYS_I2C_DS4510_ADDR 0x51
  245. /* GPIO */
  246. #define CONFIG_PCA953X
  247. #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
  248. #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
  249. #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
  250. #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
  251. #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
  252. /*
  253. * PU = pulled high, PD = pulled low
  254. * I = input, O = output, IO = input/output
  255. */
  256. /* PCA9557 @ 0x18*/
  257. #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
  258. #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
  259. #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
  260. #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
  261. #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
  262. #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
  263. /* PCA9557 @ 0x1c*/
  264. #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
  265. #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
  266. #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
  267. #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
  268. #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
  269. #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
  270. #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
  271. #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
  272. /* PCA9557 @ 0x1e*/
  273. #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
  274. #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
  275. #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
  276. #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
  277. #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
  278. #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
  279. #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
  280. /* PCA9557 @ 0x1f */
  281. #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
  282. #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
  283. #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
  284. #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
  285. /*
  286. * General PCI
  287. * Memory space is mapped 1-1, but I/O space must start from 0.
  288. */
  289. /* PCIE1 - PEX8518 */
  290. #define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
  291. #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
  292. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
  293. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  294. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
  295. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  296. /* PCIE2 - VPX P1 */
  297. #define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
  298. #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
  299. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  300. #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
  301. #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
  302. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
  303. /*
  304. * Networking options
  305. */
  306. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  307. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  308. #define CONFIG_NET_MULTI 1
  309. #define CONFIG_MII 1 /* MII PHY management */
  310. #define CONFIG_ETHPRIME "eTSEC1"
  311. #define CONFIG_TSEC1 1
  312. #define CONFIG_TSEC1_NAME "eTSEC1"
  313. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  314. #define TSEC1_PHY_ADDR 1
  315. #define TSEC1_PHYIDX 0
  316. #define CONFIG_HAS_ETH0
  317. #define CONFIG_TSEC2 1
  318. #define CONFIG_TSEC2_NAME "eTSEC2"
  319. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  320. #define TSEC2_PHY_ADDR 2
  321. #define TSEC2_PHYIDX 0
  322. #define CONFIG_HAS_ETH1
  323. /*
  324. * BAT mappings
  325. */
  326. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
  327. #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
  328. BATL_PP_RW |\
  329. BATL_CACHEINHIBIT |\
  330. BATL_GUARDEDSTORAGE)
  331. #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
  332. BATU_BL_1M |\
  333. BATU_VS |\
  334. BATU_VP)
  335. #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
  336. BATL_PP_RW |\
  337. BATL_CACHEINHIBIT)
  338. #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
  339. #endif
  340. /*
  341. * BAT0 2G Cacheable, non-guarded
  342. * 0x0000_0000 2G DDR
  343. */
  344. #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  345. #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
  346. #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  347. #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
  348. /*
  349. * BAT1 1G Cache-inhibited, guarded
  350. * 0x8000_0000 1G PCI-Express 1 Memory
  351. */
  352. #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
  353. BATL_PP_RW |\
  354. BATL_CACHEINHIBIT |\
  355. BATL_GUARDEDSTORAGE)
  356. #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
  357. BATU_BL_1G |\
  358. BATU_VS |\
  359. BATU_VP)
  360. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
  361. BATL_PP_RW |\
  362. BATL_CACHEINHIBIT)
  363. #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
  364. /*
  365. * BAT2 512M Cache-inhibited, guarded
  366. * 0xc000_0000 512M PCI-Express 2 Memory
  367. */
  368. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
  369. BATL_PP_RW |\
  370. BATL_CACHEINHIBIT |\
  371. BATL_GUARDEDSTORAGE)
  372. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
  373. BATU_BL_512M |\
  374. BATU_VS |\
  375. BATU_VP)
  376. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
  377. BATL_PP_RW |\
  378. BATL_CACHEINHIBIT)
  379. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  380. /*
  381. * BAT3 1M Cache-inhibited, guarded
  382. * 0xe000_0000 1M CCSR
  383. */
  384. #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
  385. BATL_PP_RW |\
  386. BATL_CACHEINHIBIT |\
  387. BATL_GUARDEDSTORAGE)
  388. #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
  389. BATU_BL_1M |\
  390. BATU_VS |\
  391. BATU_VP)
  392. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
  393. BATL_PP_RW |\
  394. BATL_CACHEINHIBIT)
  395. #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
  396. /*
  397. * BAT4 32M Cache-inhibited, guarded
  398. * 0xe200_0000 16M PCI-Express 1 I/O
  399. * 0xe300_0000 16M PCI-Express 2 I/0
  400. */
  401. #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
  402. BATL_PP_RW |\
  403. BATL_CACHEINHIBIT |\
  404. BATL_GUARDEDSTORAGE)
  405. #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
  406. BATU_BL_32M |\
  407. BATU_VS |\
  408. BATU_VP)
  409. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
  410. BATL_PP_RW |\
  411. BATL_CACHEINHIBIT)
  412. #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
  413. /*
  414. * BAT5 128K Cacheable, non-guarded
  415. * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
  416. */
  417. #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
  418. BATL_PP_RW |\
  419. BATL_MEMCOHERENCE)
  420. #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
  421. BATU_BL_128K |\
  422. BATU_VS |\
  423. BATU_VP)
  424. #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
  425. #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
  426. /*
  427. * BAT6 256M Cache-inhibited, guarded
  428. * 0xf000_0000 256M FLASH
  429. */
  430. #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
  431. BATL_PP_RW |\
  432. BATL_CACHEINHIBIT |\
  433. BATL_GUARDEDSTORAGE)
  434. #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
  435. BATU_BL_256M |\
  436. BATU_VS |\
  437. BATU_VP)
  438. #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
  439. BATL_PP_RW |\
  440. BATL_MEMCOHERENCE)
  441. #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
  442. /* Map the last 1M of flash where we're running from reset */
  443. #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
  444. BATL_PP_RW |\
  445. BATL_CACHEINHIBIT |\
  446. BATL_GUARDEDSTORAGE)
  447. #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE |\
  448. BATU_BL_1M |\
  449. BATU_VS |\
  450. BATU_VP)
  451. #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
  452. BATL_PP_RW |\
  453. BATL_MEMCOHERENCE)
  454. #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
  455. /*
  456. * BAT7 64M Cache-inhibited, guarded
  457. * 0xe800_0000 64K NAND FLASH
  458. * 0xe804_0000 128K DUART Registers
  459. */
  460. #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
  461. BATL_PP_RW |\
  462. BATL_CACHEINHIBIT |\
  463. BATL_GUARDEDSTORAGE)
  464. #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
  465. BATU_BL_512K |\
  466. BATU_VS |\
  467. BATU_VP)
  468. #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
  469. BATL_PP_RW |\
  470. BATL_CACHEINHIBIT)
  471. #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
  472. /*
  473. * Command configuration.
  474. */
  475. #include <config_cmd_default.h>
  476. #define CONFIG_CMD_ASKENV
  477. #define CONFIG_CMD_DATE
  478. #define CONFIG_CMD_DHCP
  479. #define CONFIG_CMD_DS4510
  480. #define CONFIG_CMD_DS4510_INFO
  481. #define CONFIG_CMD_DTT
  482. #define CONFIG_CMD_EEPROM
  483. #define CONFIG_CMD_ELF
  484. #define CONFIG_CMD_SAVEENV
  485. #define CONFIG_CMD_FLASH
  486. #define CONFIG_CMD_I2C
  487. #define CONFIG_CMD_IRQ
  488. #define CONFIG_CMD_JFFS2
  489. #define CONFIG_CMD_MII
  490. #define CONFIG_CMD_NAND
  491. #define CONFIG_CMD_NET
  492. #define CONFIG_CMD_PCA953X
  493. #define CONFIG_CMD_PCA953X_INFO
  494. #define CONFIG_CMD_PCI
  495. #define CONFIG_CMD_PING
  496. #define CONFIG_CMD_REGINFO
  497. #define CONFIG_CMD_SNTP
  498. /*
  499. * Miscellaneous configurable options
  500. */
  501. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  502. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  503. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  504. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  505. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  506. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  507. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  508. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  509. #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
  510. #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
  511. #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
  512. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  513. #define CONFIG_PREBOOT /* enable preboot variable */
  514. #define CONFIG_FIT 1
  515. #define CONFIG_FIT_VERBOSE 1
  516. #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
  517. /*
  518. * For booting Linux, the board info and command line data
  519. * have to be in the first 16 MB of memory, since this is
  520. * the maximum mapped by the Linux kernel during initialization.
  521. */
  522. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  523. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  524. /*
  525. * Boot Flags
  526. */
  527. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  528. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  529. /*
  530. * Environment Configuration
  531. */
  532. #define CONFIG_ENV_IS_IN_FLASH 1
  533. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
  534. #define CONFIG_ENV_SIZE 0x8000
  535. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  536. /*
  537. * Flash memory map:
  538. * fffc0000 - ffffffff Pri FDT (256KB)
  539. * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
  540. * fff00000 - fff7ffff Pri U-Boot (512 KB)
  541. * fef00000 - ffefffff Pri OS image (16MB)
  542. * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
  543. *
  544. * f7fc0000 - f7ffffff Sec FDT (256KB)
  545. * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
  546. * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
  547. * f6f00000 - f7efffff Sec OS image (16MB)
  548. * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
  549. */
  550. #define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff00000)
  551. #define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f00000)
  552. #define CONFIG_FDT1_ENV_ADDR MK_STR(0xfffc0000)
  553. #define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7fc0000)
  554. #define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
  555. #define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
  556. #define CONFIG_PROG_UBOOT1 \
  557. "$download_cmd $loadaddr $ubootfile; " \
  558. "if test $? -eq 0; then " \
  559. "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  560. "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  561. "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
  562. "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  563. "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
  564. "if test $? -ne 0; then " \
  565. "echo PROGRAM FAILED; " \
  566. "else; " \
  567. "echo PROGRAM SUCCEEDED; " \
  568. "fi; " \
  569. "else; " \
  570. "echo DOWNLOAD FAILED; " \
  571. "fi;"
  572. #define CONFIG_PROG_UBOOT2 \
  573. "$download_cmd $loadaddr $ubootfile; " \
  574. "if test $? -eq 0; then " \
  575. "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  576. "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  577. "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
  578. "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  579. "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
  580. "if test $? -ne 0; then " \
  581. "echo PROGRAM FAILED; " \
  582. "else; " \
  583. "echo PROGRAM SUCCEEDED; " \
  584. "fi; " \
  585. "else; " \
  586. "echo DOWNLOAD FAILED; " \
  587. "fi;"
  588. #define CONFIG_BOOT_OS_NET \
  589. "$download_cmd $osaddr $osfile; " \
  590. "if test $? -eq 0; then " \
  591. "if test -n $fdtaddr; then " \
  592. "$download_cmd $fdtaddr $fdtfile; " \
  593. "if test $? -eq 0; then " \
  594. "bootm $osaddr - $fdtaddr; " \
  595. "else; " \
  596. "echo FDT DOWNLOAD FAILED; " \
  597. "fi; " \
  598. "else; " \
  599. "bootm $osaddr; " \
  600. "fi; " \
  601. "else; " \
  602. "echo OS DOWNLOAD FAILED; " \
  603. "fi;"
  604. #define CONFIG_PROG_OS1 \
  605. "$download_cmd $osaddr $osfile; " \
  606. "if test $? -eq 0; then " \
  607. "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
  608. "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  609. "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  610. "if test $? -ne 0; then " \
  611. "echo OS PROGRAM FAILED; " \
  612. "else; " \
  613. "echo OS PROGRAM SUCCEEDED; " \
  614. "fi; " \
  615. "else; " \
  616. "echo OS DOWNLOAD FAILED; " \
  617. "fi;"
  618. #define CONFIG_PROG_OS2 \
  619. "$download_cmd $osaddr $osfile; " \
  620. "if test $? -eq 0; then " \
  621. "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
  622. "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  623. "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  624. "if test $? -ne 0; then " \
  625. "echo OS PROGRAM FAILED; " \
  626. "else; " \
  627. "echo OS PROGRAM SUCCEEDED; " \
  628. "fi; " \
  629. "else; " \
  630. "echo OS DOWNLOAD FAILED; " \
  631. "fi;"
  632. #define CONFIG_PROG_FDT1 \
  633. "$download_cmd $fdtaddr $fdtfile; " \
  634. "if test $? -eq 0; then " \
  635. "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
  636. "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  637. "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  638. "if test $? -ne 0; then " \
  639. "echo FDT PROGRAM FAILED; " \
  640. "else; " \
  641. "echo FDT PROGRAM SUCCEEDED; " \
  642. "fi; " \
  643. "else; " \
  644. "echo FDT DOWNLOAD FAILED; " \
  645. "fi;"
  646. #define CONFIG_PROG_FDT2 \
  647. "$download_cmd $fdtaddr $fdtfile; " \
  648. "if test $? -eq 0; then " \
  649. "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
  650. "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  651. "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  652. "if test $? -ne 0; then " \
  653. "echo FDT PROGRAM FAILED; " \
  654. "else; " \
  655. "echo FDT PROGRAM SUCCEEDED; " \
  656. "fi; " \
  657. "else; " \
  658. "echo FDT DOWNLOAD FAILED; " \
  659. "fi;"
  660. #define CONFIG_EXTRA_ENV_SETTINGS \
  661. "autoload=yes\0" \
  662. "download_cmd=tftp\0" \
  663. "console_args=console=ttyS0,115200\0" \
  664. "root_args=root=/dev/nfs rw\0" \
  665. "misc_args=ip=on\0" \
  666. "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
  667. "bootfile=/home/user/file\0" \
  668. "osfile=/home/user/uImage-XPedite5170\0" \
  669. "fdtfile=/home/user/xpedite5170.dtb\0" \
  670. "ubootfile=/home/user/u-boot.bin\0" \
  671. "fdtaddr=c00000\0" \
  672. "osaddr=0x1000000\0" \
  673. "loadaddr=0x1000000\0" \
  674. "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
  675. "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
  676. "prog_os1="CONFIG_PROG_OS1"\0" \
  677. "prog_os2="CONFIG_PROG_OS2"\0" \
  678. "prog_fdt1="CONFIG_PROG_FDT1"\0" \
  679. "prog_fdt2="CONFIG_PROG_FDT2"\0" \
  680. "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
  681. "bootcmd_flash1=run set_bootargs; " \
  682. "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
  683. "bootcmd_flash2=run set_bootargs; " \
  684. "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
  685. "bootcmd=run bootcmd_flash1\0"
  686. #endif /* __CONFIG_H */