WUH405.h 14 KB

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  1. /*
  2. * (C) Copyright 2004
  3. * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_IDENT_STRING " $Name: $"
  33. #define CONFIG_405EP 1 /* This is a PPC405 CPU */
  34. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  35. #define CONFIG_WUH405 1 /* ...on a WUH405 board */
  36. #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
  37. #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
  38. #define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
  39. #define CONFIG_BAUDRATE 9600
  40. #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
  41. #undef CONFIG_BOOTARGS
  42. #undef CONFIG_BOOTCOMMAND
  43. #define CONFIG_PREBOOT /* enable preboot variable */
  44. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  45. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  46. #define CONFIG_PPC4xx_EMAC
  47. #define CONFIG_MII 1 /* MII PHY management */
  48. #define CONFIG_PHY_ADDR 0 /* PHY address */
  49. #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
  50. #define CONFIG_NET_MULTI
  51. #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  52. /*
  53. * BOOTP options
  54. */
  55. #define CONFIG_BOOTP_BOOTFILESIZE
  56. #define CONFIG_BOOTP_BOOTPATH
  57. #define CONFIG_BOOTP_GATEWAY
  58. #define CONFIG_BOOTP_HOSTNAME
  59. /*
  60. * Command line configuration.
  61. */
  62. #include <config_cmd_default.h>
  63. #define CONFIG_CMD_DHCP
  64. #define CONFIG_CMD_IRQ
  65. #define CONFIG_CMD_ELF
  66. #define CONFIG_CMD_NAND
  67. #define CONFIG_CMD_DATE
  68. #define CONFIG_CMD_I2C
  69. #define CONFIG_CMD_MII
  70. #define CONFIG_CMD_PING
  71. #define CONFIG_CMD_EEPROM
  72. #undef CONFIG_WATCHDOG /* watchdog disabled */
  73. #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
  74. #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
  75. #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  76. /*
  77. * Miscellaneous configurable options
  78. */
  79. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  80. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  81. #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  82. #ifdef CONFIG_SYS_HUSH_PARSER
  83. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  84. #endif
  85. #if defined(CONFIG_CMD_KGDB)
  86. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  87. #else
  88. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  89. #endif
  90. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  91. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  92. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  93. #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
  94. #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
  95. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  96. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  97. #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
  98. #define CONFIG_SYS_BASE_BAUD 691200
  99. #define CONFIG_UART1_CONSOLE /* define for uart1 as console */
  100. /* The following table includes the supported baudrates */
  101. #define CONFIG_SYS_BAUDRATE_TABLE \
  102. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  103. 57600, 115200, 230400, 460800, 921600 }
  104. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  105. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  106. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  107. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  108. #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  109. #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
  110. /*-----------------------------------------------------------------------
  111. * NAND-FLASH stuff
  112. *-----------------------------------------------------------------------
  113. */
  114. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  115. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  116. #define NAND_BIG_DELAY_US 25
  117. #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
  118. #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
  119. #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
  120. #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
  121. #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
  122. /*-----------------------------------------------------------------------
  123. * PCI stuff
  124. *-----------------------------------------------------------------------
  125. */
  126. #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
  127. #define PCI_HOST_FORCE 1 /* configure as pci host */
  128. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  129. #define CONFIG_PCI /* include pci support */
  130. #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
  131. #undef CONFIG_PCI_PNP /* do pci plug-and-play */
  132. /* resource configuration */
  133. #undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
  134. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
  135. #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
  136. #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
  137. #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
  138. #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
  139. #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  140. #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
  141. #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
  142. #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
  143. /*-----------------------------------------------------------------------
  144. * Start addresses for the final memory configuration
  145. * (Set up by the startup code)
  146. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  147. */
  148. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  149. #define CONFIG_SYS_FLASH_BASE 0xFFFC0000
  150. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  151. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
  152. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
  153. /*
  154. * For booting Linux, the board info and command line data
  155. * have to be in the first 8 MB of memory, since this is
  156. * the maximum mapped by the Linux kernel during initialization.
  157. */
  158. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  159. /*-----------------------------------------------------------------------
  160. * FLASH organization
  161. */
  162. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  163. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  164. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  165. #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
  166. #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
  167. #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
  168. #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
  169. /*
  170. * The following defines are added for buggy IOP480 byte interface.
  171. * All other boards should use the standard values (CPCI405 etc.)
  172. */
  173. #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
  174. #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
  175. #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
  176. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  177. #if 0 /* test-only */
  178. #define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
  179. #define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
  180. #endif
  181. /*-----------------------------------------------------------------------
  182. * Environment Variable setup
  183. */
  184. #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
  185. #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
  186. #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
  187. /* total size of a CAT24WC16 is 2048 bytes */
  188. #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
  189. #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
  190. /*-----------------------------------------------------------------------
  191. * I2C EEPROM (CAT24WC16) for environment
  192. */
  193. #define CONFIG_HARD_I2C /* I2c with hardware support */
  194. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  195. #define CONFIG_SYS_I2C_SLAVE 0x7F
  196. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
  197. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  198. /* mask of address bits that overflow into the "EEPROM chip address" */
  199. #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
  200. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
  201. /* 16 byte page write mode using*/
  202. /* last 4 bits of the address */
  203. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  204. /*
  205. * Init Memory Controller:
  206. *
  207. * BR0/1 and OR0/1 (FLASH)
  208. */
  209. #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
  210. /*-----------------------------------------------------------------------
  211. * External Bus Controller (EBC) Setup
  212. */
  213. /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
  214. #define CONFIG_SYS_EBC_PB0AP 0x92015480
  215. /*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
  216. #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
  217. /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
  218. #define CONFIG_SYS_EBC_PB1AP 0x92015480
  219. #define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
  220. /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
  221. #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  222. #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
  223. /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
  224. #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  225. #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
  226. #define CAN_BA 0xF0000000 /* CAN Base Address */
  227. #define DUART0_BA 0xF0000400 /* DUART Base Address */
  228. #define DUART1_BA 0xF0000408 /* DUART Base Address */
  229. #define DUART2_BA 0xF0000410 /* DUART Base Address */
  230. #define DUART3_BA 0xF0000418 /* DUART Base Address */
  231. #define RTC_BA 0xF0000500 /* RTC Base Address */
  232. #define CONFIG_SYS_NAND_BASE 0xF4000000
  233. /*-----------------------------------------------------------------------
  234. * FPGA stuff
  235. */
  236. #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
  237. #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
  238. /* FPGA program pin configuration */
  239. #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
  240. #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
  241. #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
  242. #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
  243. #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
  244. /*-----------------------------------------------------------------------
  245. * Definitions for initial stack pointer and data area (in data cache)
  246. */
  247. /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
  248. #define CONFIG_SYS_TEMP_STACK_OCM 1
  249. /* On Chip Memory location */
  250. #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
  251. #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
  252. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
  253. #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
  254. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  255. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  256. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  257. /*-----------------------------------------------------------------------
  258. * Definitions for GPIO setup (PPC405EP specific)
  259. *
  260. * GPIO0[0] - External Bus Controller BLAST output
  261. * GPIO0[1-9] - Instruction trace outputs -> GPIO
  262. * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  263. * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  264. * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  265. * GPIO0[24-27] - UART0 control signal inputs/outputs
  266. * GPIO0[28-29] - UART1 data signal input/output
  267. * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  268. */
  269. #define CONFIG_SYS_GPIO0_OSRH 0x40000550
  270. #define CONFIG_SYS_GPIO0_OSRL 0x00000110
  271. #define CONFIG_SYS_GPIO0_ISR1H 0x00000000
  272. #define CONFIG_SYS_GPIO0_ISR1L 0x15555445
  273. #define CONFIG_SYS_GPIO0_TSRH 0x00000000
  274. #define CONFIG_SYS_GPIO0_TSRL 0x00000000
  275. #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
  276. #define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
  277. /*
  278. * Internal Definitions
  279. *
  280. * Boot Flags
  281. */
  282. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  283. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  284. /*
  285. * Default speed selection (cpu_plb_opb_ebc) in mhz.
  286. * This value will be set if iic boot eprom is disabled.
  287. */
  288. #if 0
  289. #define PLLMR0_DEFAULT PLLMR0_266_133_66_33
  290. #define PLLMR1_DEFAULT PLLMR1_266_133_66_33
  291. #endif
  292. #if 1
  293. #define PLLMR0_DEFAULT PLLMR0_200_100_50_33
  294. #define PLLMR1_DEFAULT PLLMR1_200_100_50_33
  295. #endif
  296. #if 0
  297. #define PLLMR0_DEFAULT PLLMR0_133_66_66_33
  298. #define PLLMR1_DEFAULT PLLMR1_133_66_66_33
  299. #endif
  300. #endif /* __CONFIG_H */