TQM85xx.h 23 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
  4. *
  5. * (C) Copyright 2005
  6. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  7. *
  8. * Wolfgang Denk <wd@denx.de>
  9. * Copyright 2004 Freescale Semiconductor.
  10. * (C) Copyright 2002,2003 Motorola,Inc.
  11. * Xianghua Xiao <X.Xiao@motorola.com>
  12. *
  13. * See file CREDITS for list of people who contributed to this
  14. * project.
  15. *
  16. * This program is free software; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License as
  18. * published by the Free Software Foundation; either version 2 of
  19. * the License, or (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software
  28. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29. * MA 02111-1307 USA
  30. */
  31. /*
  32. * TQM85xx (8560/40/55/41/48) board configuration file
  33. */
  34. #ifndef __CONFIG_H
  35. #define __CONFIG_H
  36. /* High Level Configuration Options */
  37. #define CONFIG_BOOKE 1 /* BOOKE */
  38. #define CONFIG_E500 1 /* BOOKE e500 family */
  39. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
  40. #if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
  41. #define CONFIG_TQM8548
  42. #endif
  43. #define CONFIG_PCI
  44. #ifndef CONFIG_TQM8548_AG
  45. #define CONFIG_PCI1 /* PCI/PCI-X controller */
  46. #endif
  47. #ifdef CONFIG_TQM8548
  48. #define CONFIG_PCIE1 /* PCI Express interface */
  49. #endif
  50. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  51. #define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */
  52. #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
  53. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  54. #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
  55. /*
  56. * Configuration for big NOR Flashes
  57. *
  58. * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
  59. * Please be aware, that this changes the whole memory map (new CCSRBAR
  60. * address, etc). You have to use an adapted Linux kernel or FDT blob
  61. * if this option is set.
  62. */
  63. #undef CONFIG_TQM_BIGFLASH
  64. /*
  65. * NAND flash support (disabled by default)
  66. *
  67. * Warning: NAND support will likely increase the U-Boot image size
  68. * to more than 256 KB. Please adjust TEXT_BASE if necessary.
  69. */
  70. #ifdef CONFIG_TQM8548_BE
  71. #define CONFIG_NAND
  72. #endif
  73. /*
  74. * MPC8540 and MPC8548 don't have CPM module
  75. */
  76. #if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
  77. #define CONFIG_CPM2 1 /* has CPM2 */
  78. #endif
  79. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  80. #if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
  81. #define CONFIG_CAN_DRIVER /* CAN Driver support */
  82. #endif
  83. /*
  84. * sysclk for MPC85xx
  85. *
  86. * Two valid values are:
  87. * 33333333
  88. * 66666666
  89. *
  90. * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  91. * is likely the desired value here, so that is now the default.
  92. * The board, however, can run at 66MHz. In any event, this value
  93. * must match the settings of some switches. Details can be found
  94. * in the README.mpc85xxads.
  95. */
  96. #ifndef CONFIG_SYS_CLK_FREQ
  97. #define CONFIG_SYS_CLK_FREQ 33333333
  98. #endif
  99. /*
  100. * These can be toggled for performance analysis, otherwise use default.
  101. */
  102. #define CONFIG_L2_CACHE /* toggle L2 cache */
  103. #define CONFIG_BTB /* toggle branch predition */
  104. #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
  105. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  106. #define CONFIG_SYS_MEMTEST_START 0x00000000
  107. #define CONFIG_SYS_MEMTEST_END 0x10000000
  108. /*
  109. * Base addresses -- Note these are effective addresses where the
  110. * actual resources get mapped (not physical addresses)
  111. */
  112. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
  113. #ifdef CONFIG_TQM_BIGFLASH
  114. #define CONFIG_SYS_CCSRBAR 0xA0000000 /* relocated CCSRBAR */
  115. #else /* !CONFIG_TQM_BIGFLASH */
  116. #define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
  117. #endif /* CONFIG_TQM_BIGFLASH */
  118. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
  119. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  120. #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
  121. #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
  122. #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
  123. /*
  124. * DDR Setup
  125. */
  126. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
  127. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  128. #ifdef CONFIG_TQM8548_AG
  129. #define CONFIG_VERY_BIG_RAM
  130. #endif
  131. #define CONFIG_NUM_DDR_CONTROLLERS 1
  132. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  133. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  134. #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
  135. /* TQM8540 & 8560 need DLL-override */
  136. #define CONFIG_DDR_DLL /* DLL fix needed */
  137. #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
  138. #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
  139. #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
  140. defined(CONFIG_TQM8548)
  141. #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
  142. #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
  143. /*
  144. * Flash on the Local Bus
  145. */
  146. #ifdef CONFIG_TQM_BIGFLASH
  147. #define CONFIG_SYS_FLASH0 0xE0000000
  148. #define CONFIG_SYS_FLASH1 0xC0000000
  149. #else /* !CONFIG_TQM_BIGFLASH */
  150. #define CONFIG_SYS_FLASH0 0xFC000000
  151. #define CONFIG_SYS_FLASH1 0xF8000000
  152. #endif /* CONFIG_TQM_BIGFLASH */
  153. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
  154. #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
  155. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
  156. /* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
  157. *
  158. * Note: According to timing specifications external addr latch delay
  159. * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
  160. *
  161. * For other Local Bus Clocks see following table:
  162. *
  163. * Clock/MHz CONFIG_SYS_ORx_PRELIM
  164. * 166 0x.....CA5
  165. * 133 0x.....C85
  166. * 100 0x.....C65
  167. * 83 0x.....FA2
  168. * 66 0x.....C82
  169. * 50 0x.....C60
  170. * 42 0x.....040
  171. * 33 0x.....030
  172. * 25 0x.....020
  173. *
  174. */
  175. #ifdef CONFIG_TQM_BIGFLASH
  176. #define CONFIG_SYS_BR0_PRELIM 0xE0001801 /* port size 32bit */
  177. #define CONFIG_SYS_OR0_PRELIM 0xE0000040 /* 512MB Flash */
  178. #define CONFIG_SYS_BR1_PRELIM 0xC0001801 /* port size 32bit */
  179. #define CONFIG_SYS_OR1_PRELIM 0xE0000040 /* 512MB Flash */
  180. #else /* !CONFIG_TQM_BIGFLASH */
  181. #define CONFIG_SYS_BR0_PRELIM 0xfc001801 /* port size 32bit */
  182. #define CONFIG_SYS_OR0_PRELIM 0xfc000040 /* 64MB Flash */
  183. #define CONFIG_SYS_BR1_PRELIM 0xf8001801 /* port size 32bit */
  184. #define CONFIG_SYS_OR1_PRELIM 0xfc000040 /* 64MB Flash */
  185. #endif /* CONFIG_TQM_BIGFLASH */
  186. #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
  187. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  188. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
  189. #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
  190. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */
  191. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  192. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
  193. #undef CONFIG_SYS_FLASH_CHECKSUM
  194. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  195. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  196. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  197. /*
  198. * Note: when changing the Local Bus clock divider you have to
  199. * change the timing values in CONFIG_SYS_ORx_PRELIM.
  200. *
  201. * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
  202. * LCRR[16:17] EADC : External address delay cycles. It should be set to 2
  203. * for Local Bus Clock > 83.3 MHz.
  204. */
  205. #define CONFIG_SYS_LBC_LCRR 0x00030008 /* LB clock ratio reg */
  206. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  207. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  208. #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
  209. #define CONFIG_SYS_INIT_RAM_LOCK 1
  210. #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_CCSRBAR \
  211. + 0x04010000) /* Initial RAM address */
  212. #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */
  213. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  214. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  215. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  216. #define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1)/* Reserved for Monitor */
  217. #define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserved for malloc */
  218. /* Serial Port */
  219. #if defined(CONFIG_TQM8560)
  220. #define CONFIG_CONS_ON_SCC /* define if console on SCC */
  221. #undef CONFIG_CONS_NONE /* define if console on something else */
  222. #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
  223. #else /* !CONFIG_TQM8560 */
  224. #define CONFIG_CONS_INDEX 1
  225. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  226. #define CONFIG_SYS_NS16550
  227. #define CONFIG_SYS_NS16550_SERIAL
  228. #define CONFIG_SYS_NS16550_REG_SIZE 1
  229. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  230. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  231. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  232. /* PS/2 Keyboard */
  233. #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
  234. #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
  235. #define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
  236. #define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
  237. #define CONFIG_BOARD_EARLY_INIT_R 1
  238. #endif /* CONFIG_TQM8560 */
  239. #define CONFIG_BAUDRATE 115200
  240. #define CONFIG_SYS_BAUDRATE_TABLE \
  241. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  242. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  243. #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
  244. #ifdef CONFIG_SYS_HUSH_PARSER
  245. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  246. #endif
  247. /* pass open firmware flat tree */
  248. #define CONFIG_OF_LIBFDT 1
  249. #define CONFIG_OF_BOARD_SETUP 1
  250. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  251. /* CAN */
  252. #define CONFIG_SYS_CAN_BASE (CONFIG_SYS_CCSRBAR \
  253. + 0x03000000) /* CAN base address */
  254. #ifdef CONFIG_CAN_DRIVER
  255. #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */
  256. #define CONFIG_SYS_OR2_CAN (CONFIG_SYS_CAN_OR_AM | OR_UPM_BI)
  257. #define CONFIG_SYS_BR2_CAN ((CONFIG_SYS_CAN_BASE & BR_BA) | \
  258. BR_PS_8 | BR_MS_UPMC | BR_V)
  259. #endif /* CONFIG_CAN_DRIVER */
  260. /*
  261. * I2C
  262. */
  263. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  264. #define CONFIG_HARD_I2C /* I2C with hardware support */
  265. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  266. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  267. #define CONFIG_SYS_I2C_SLAVE 0x7F
  268. #define CONFIG_SYS_I2C_NOPROBES {0x48} /* Don't probe these addrs */
  269. #define CONFIG_SYS_I2C_OFFSET 0x3000
  270. /* I2C RTC */
  271. #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
  272. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  273. /* I2C EEPROM */
  274. /*
  275. * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
  276. */
  277. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
  278. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  279. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
  280. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
  281. #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
  282. /* I2C SYSMON (LM75) */
  283. #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
  284. #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
  285. #define CONFIG_SYS_DTT_MAX_TEMP 70
  286. #define CONFIG_SYS_DTT_LOW_TEMP -30
  287. #define CONFIG_SYS_DTT_HYSTERESIS 3
  288. #ifndef CONFIG_PCIE1
  289. /* RapidIO MMU */
  290. #ifdef CONFIG_TQM_BIGFLASH
  291. #define CONFIG_SYS_RIO_MEM_BASE 0xb0000000 /* base address */
  292. #define CONFIG_SYS_RIO_MEM_SIZE 0x10000000 /* 256M */
  293. #else /* !CONFIG_TQM_BIGFLASH */
  294. #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
  295. #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
  296. #endif /* CONFIG_TQM_BIGFLASH */
  297. #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
  298. #endif /* CONFIG_PCIE1 */
  299. /* NAND FLASH */
  300. #ifdef CONFIG_NAND
  301. #define CONFIG_NAND_FSL_UPM 1
  302. #define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */
  303. /* address distance between chip selects */
  304. #define CONFIG_SYS_NAND_SELECT_DEVICE 1
  305. #define CONFIG_SYS_NAND_CS_DIST 0x200
  306. #define CONFIG_SYS_NAND_SIZE 0x8000
  307. #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_CCSRBAR + 0x03010000)
  308. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  309. #define CONFIG_SYS_NAND_MAX_CHIPS 2 /* Number of chips per device */
  310. /* CS3 for NAND Flash */
  311. #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA) | \
  312. BR_PS_8 | BR_MS_UPMB | BR_V)
  313. #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
  314. #define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
  315. #endif /* CONFIG_NAND */
  316. /*
  317. * General PCI
  318. * Addresses are mapped 1-1.
  319. */
  320. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  321. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  322. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  323. #define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000)
  324. #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
  325. #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
  326. #ifdef CONFIG_PCIE1
  327. /*
  328. * General PCI express
  329. * Addresses are mapped 1-1.
  330. */
  331. #ifdef CONFIG_TQM_BIGFLASH
  332. #define CONFIG_SYS_PCIE1_MEM_BASE 0xb0000000
  333. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */
  334. #define CONFIG_SYS_PCIE1_IO_BASE 0xaf000000
  335. #else /* !CONFIG_TQM_BIGFLASH */
  336. #define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000
  337. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  338. #define CONFIG_SYS_PCIE1_IO_BASE 0xef000000
  339. #endif /* CONFIG_TQM_BIGFLASH */
  340. #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
  341. #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BASE
  342. #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
  343. #endif /* CONFIG_PCIE1 */
  344. #if defined(CONFIG_PCI)
  345. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  346. #define CONFIG_EEPRO100
  347. #undef CONFIG_TULIP
  348. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  349. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  350. #endif /* CONFIG_PCI */
  351. #define CONFIG_NET_MULTI 1
  352. #define CONFIG_MII 1 /* MII PHY management */
  353. #define CONFIG_TSEC1 1
  354. #define CONFIG_TSEC1_NAME "TSEC0"
  355. #define CONFIG_TSEC2 1
  356. #define CONFIG_TSEC2_NAME "TSEC1"
  357. #define TSEC1_PHY_ADDR 2
  358. #define TSEC2_PHY_ADDR 1
  359. #define TSEC1_PHYIDX 0
  360. #define TSEC2_PHYIDX 0
  361. #define TSEC1_FLAGS TSEC_GIGABIT
  362. #define TSEC2_FLAGS TSEC_GIGABIT
  363. #define FEC_PHY_ADDR 3
  364. #define FEC_PHYIDX 0
  365. #define FEC_FLAGS 0
  366. #define CONFIG_HAS_ETH0
  367. #define CONFIG_HAS_ETH1
  368. #define CONFIG_HAS_ETH2
  369. #ifdef CONFIG_TQM8548
  370. /*
  371. * TQM8548 has 4 ethernet ports. 4 ETSEC's.
  372. *
  373. * On the STK85xx Starterkit the ETSEC3/4 ports are on an
  374. * additional adapter (AIO) between module and Starterkit.
  375. */
  376. #define CONFIG_TSEC3 1
  377. #define CONFIG_TSEC3_NAME "TSEC2"
  378. #define CONFIG_TSEC4 1
  379. #define CONFIG_TSEC4_NAME "TSEC3"
  380. #define TSEC3_PHY_ADDR 4
  381. #define TSEC4_PHY_ADDR 5
  382. #define TSEC3_PHYIDX 0
  383. #define TSEC4_PHYIDX 0
  384. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  385. #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  386. #define CONFIG_HAS_ETH3
  387. #define CONFIG_HAS_ETH4
  388. #endif /* CONFIG_TQM8548 */
  389. /* Options are TSEC[0-1], FEC */
  390. #define CONFIG_ETHPRIME "TSEC0"
  391. #if defined(CONFIG_TQM8540)
  392. /*
  393. * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
  394. * The FEC port is connected on the same signals as the FCC3 port
  395. * of the TQM8560 to the baseboard (STK85xx Starterkit).
  396. *
  397. * On the STK85xx Starterkit the X47/X50 jumper has to be set to
  398. * a - d (X50.2 - 3) to enable the FEC port.
  399. */
  400. #define CONFIG_MPC85XX_FEC 1
  401. #define CONFIG_MPC85XX_FEC_NAME "FEC"
  402. #endif
  403. #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
  404. /*
  405. * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
  406. * can be used at once, since only one FCC port is available on the STK85xx
  407. * Starterkit.
  408. *
  409. * To use this port you have to configure U-Boot to use the FCC port 1...2
  410. * and set the X47/X50 jumper to:
  411. * FCC1: a - b (X47.2 - X50.2)
  412. * FCC2: a - c (X50.2 - 1)
  413. */
  414. #define CONFIG_ETHER_ON_FCC
  415. #define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
  416. #endif
  417. #if defined(CONFIG_TQM8560)
  418. /*
  419. * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
  420. * can be used at once, since only one FCC port is available on the STK85xx
  421. * Starterkit.
  422. *
  423. * To use this port you have to configure U-Boot to use the FCC port 1...3
  424. * and set the X47/X50 jumper to:
  425. * FCC1: a - b (X47.2 - X50.2)
  426. * FCC2: a - c (X50.2 - 1)
  427. * FCC3: a - d (X50.2 - 3)
  428. */
  429. #define CONFIG_ETHER_ON_FCC
  430. #define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
  431. #endif
  432. #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
  433. #define CONFIG_ETHER_ON_FCC1
  434. #define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
  435. CMXFCR_TF1CS_MSK)
  436. #define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
  437. #define CONFIG_SYS_CPMFCR_RAMTYPE 0
  438. #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
  439. #endif
  440. #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  441. #define CONFIG_ETHER_ON_FCC2
  442. #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
  443. CMXFCR_TF2CS_MSK)
  444. #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
  445. #define CONFIG_SYS_CPMFCR_RAMTYPE 0
  446. #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
  447. #endif
  448. #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
  449. #define CONFIG_ETHER_ON_FCC3
  450. #define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
  451. CMXFCR_TF3CS_MSK)
  452. #define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
  453. #define CONFIG_SYS_CPMFCR_RAMTYPE 0
  454. #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
  455. #endif
  456. /*
  457. * Environment
  458. */
  459. #define CONFIG_ENV_IS_IN_FLASH 1
  460. #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */
  461. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  462. #define CONFIG_ENV_SIZE 0x2000
  463. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
  464. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  465. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  466. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  467. #define CONFIG_TIMESTAMP /* Print image info with ts */
  468. /*
  469. * BOOTP options
  470. */
  471. #define CONFIG_BOOTP_BOOTFILESIZE
  472. #define CONFIG_BOOTP_BOOTPATH
  473. #define CONFIG_BOOTP_GATEWAY
  474. #define CONFIG_BOOTP_HOSTNAME
  475. #ifdef CONFIG_NAND
  476. /*
  477. * Use NAND-FLash as JFFS2 device
  478. */
  479. #define CONFIG_CMD_NAND
  480. #define CONFIG_CMD_JFFS2
  481. #define CONFIG_JFFS2_NAND 1
  482. #ifdef CONFIG_CMD_MTDPARTS
  483. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  484. #define CONFIG_FLASH_CFI_MTD
  485. #define MTDIDS_DEFAULT "nand0=TQM85xx-nand"
  486. #define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-"
  487. #else
  488. #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
  489. #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
  490. #define CONFIG_JFFS2_PART_SIZE 0x200000 /* size of jffs2 partition */
  491. #endif /* CONFIG_CMD_MTDPARTS */
  492. #endif /* CONFIG_NAND */
  493. /*
  494. * Command line configuration.
  495. */
  496. #include <config_cmd_default.h>
  497. #define CONFIG_CMD_PING
  498. #define CONFIG_CMD_I2C
  499. #define CONFIG_CMD_DHCP
  500. #define CONFIG_CMD_NFS
  501. #define CONFIG_CMD_SNTP
  502. #ifndef CONFIG_TQM8548_AG
  503. #define CONFIG_CMD_DATE
  504. #endif
  505. #define CONFIG_CMD_EEPROM
  506. #define CONFIG_CMD_DTT
  507. #define CONFIG_CMD_MII
  508. #if defined(CONFIG_PCI)
  509. #define CONFIG_CMD_PCI
  510. #endif
  511. #undef CONFIG_WATCHDOG /* watchdog disabled */
  512. /*
  513. * Miscellaneous configurable options
  514. */
  515. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  516. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  517. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  518. #if defined(CONFIG_CMD_KGDB)
  519. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  520. #else
  521. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  522. #endif
  523. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  524. sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buf Size */
  525. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  526. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  527. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  528. /*
  529. * For booting Linux, the board info and command line data
  530. * have to be in the first 8 MB of memory, since this is
  531. * the maximum mapped by the Linux kernel during initialization.
  532. */
  533. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  534. /*
  535. * Internal Definitions
  536. *
  537. * Boot Flags
  538. */
  539. #define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
  540. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  541. #if defined(CONFIG_CMD_KGDB)
  542. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
  543. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  544. #endif
  545. #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
  546. #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
  547. #define CONFIG_PREBOOT "echo;" \
  548. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  549. "echo"
  550. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  551. /*
  552. * Setup some board specific values for the default environment variables
  553. */
  554. #ifdef CONFIG_CPM2
  555. #define CONFIG_ENV_CONSDEV "consdev=ttyCPM0\0"
  556. #else
  557. #define CONFIG_ENV_CONSDEV "consdev=ttyS0\0"
  558. #endif
  559. #define CONFIG_ENV_FDT_FILE "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
  560. MK_STR(CONFIG_HOSTNAME)".dtb\0"
  561. #define CONFIG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
  562. #define CONFIG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
  563. "uboot_addr="MK_STR(TEXT_BASE)"\0"
  564. #define CONFIG_EXTRA_ENV_SETTINGS \
  565. CONFIG_ENV_BOOTFILE \
  566. CONFIG_ENV_FDT_FILE \
  567. CONFIG_ENV_CONSDEV \
  568. "netdev=eth0\0" \
  569. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  570. "nfsroot=$serverip:$rootpath\0" \
  571. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  572. "addip=setenv bootargs $bootargs " \
  573. "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
  574. ":$hostname:$netdev:off panic=1\0" \
  575. "addcons=setenv bootargs $bootargs " \
  576. "console=$consdev,$baudrate\0" \
  577. "flash_nfs=run nfsargs addip addcons;" \
  578. "bootm $kernel_addr - $fdt_addr\0" \
  579. "flash_self=run ramargs addip addcons;" \
  580. "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
  581. "net_nfs=tftp $kernel_addr_r $bootfile;" \
  582. "tftp $fdt_addr_r $fdt_file;" \
  583. "run nfsargs addip addcons;" \
  584. "bootm $kernel_addr_r - $fdt_addr_r\0" \
  585. "rootpath=/opt/eldk/ppc_85xx\0" \
  586. "fdt_addr_r=900000\0" \
  587. "kernel_addr_r=1000000\0" \
  588. "fdt_addr=ffec0000\0" \
  589. "kernel_addr=ffd00000\0" \
  590. "ramdisk_addr=ff800000\0" \
  591. CONFIG_ENV_UBOOT \
  592. "load=tftp 100000 $uboot\0" \
  593. "update=protect off $uboot_addr +$filesize;" \
  594. "erase $uboot_addr +$filesize;" \
  595. "cp.b 100000 $uboot_addr $filesize" \
  596. "upd=run load update\0" \
  597. ""
  598. #define CONFIG_BOOTCOMMAND "run flash_self"
  599. #endif /* __CONFIG_H */