TQM8272.h 28 KB

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  1. /*
  2. * (C) Copyright 2006
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
  33. #define CONFIG_MPC8272_FAMILY 1
  34. #define CONFIG_TQM8272 1
  35. #define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */
  36. #define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */
  37. #define STK82xx_150 1 /* on a STK82xx.150 */
  38. #define CONFIG_CPM2 1 /* Has a CPM2 */
  39. #define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
  40. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  41. #define CONFIG_BOARD_EARLY_INIT_R 1
  42. #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  43. #define CONFIG_BAUDRATE 230400
  44. #else
  45. #define CONFIG_BAUDRATE 115200
  46. #endif
  47. #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  48. #undef CONFIG_BOOTARGS
  49. #define CONFIG_EXTRA_ENV_SETTINGS \
  50. "netdev=eth0\0" \
  51. "consdev=ttyCPM0\0" \
  52. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  53. "nfsroot=${serverip}:${rootpath}\0" \
  54. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  55. "hostname=tqm8272\0" \
  56. "addip=setenv bootargs ${bootargs} " \
  57. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  58. ":${hostname}:${netdev}:off panic=1\0" \
  59. "addcons=setenv bootargs ${bootargs} " \
  60. "console=$(consdev),$(baudrate)\0" \
  61. "flash_nfs=run nfsargs addip addcons;" \
  62. "bootm ${kernel_addr}\0" \
  63. "flash_self=run ramargs addip addcons;" \
  64. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  65. "net_nfs=tftp 300000 ${bootfile};" \
  66. "run nfsargs addip addcons;bootm\0" \
  67. "rootpath=/opt/eldk/ppc_82xx\0" \
  68. "bootfile=/tftpboot/tqm8272/uImage\0" \
  69. "kernel_addr=40080000\0" \
  70. "ramdisk_addr=40100000\0" \
  71. "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \
  72. "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \
  73. "cp.b 300000 40000000 40000;" \
  74. "setenv filesize;saveenv\0" \
  75. "cphwib=cp.b 4003fc00 33fc00 400\0" \
  76. "upd=run load cphwib update\0" \
  77. ""
  78. #define CONFIG_BOOTCOMMAND "run flash_self"
  79. #define CONFIG_I2C 1
  80. #if CONFIG_I2C
  81. /* enable I2C and select the hardware/software driver */
  82. #undef CONFIG_HARD_I2C /* I2C with hardware support */
  83. #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
  84. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  85. #define CONFIG_SYS_I2C_SLAVE 0x7F
  86. /*
  87. * Software (bit-bang) I2C driver configuration
  88. */
  89. #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
  90. #define I2C_ACTIVE (iop->pdir |= 0x00010000)
  91. #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
  92. #define I2C_READ ((iop->pdat & 0x00010000) != 0)
  93. #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
  94. else iop->pdat &= ~0x00010000
  95. #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
  96. else iop->pdat &= ~0x00020000
  97. #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
  98. #define CONFIG_I2C_X
  99. /* EEPROM */
  100. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  101. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
  102. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  103. #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
  104. /* I2C RTC */
  105. #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
  106. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  107. /* I2C SYSMON (LM75) */
  108. #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
  109. #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
  110. #define CONFIG_SYS_DTT_MAX_TEMP 70
  111. #define CONFIG_SYS_DTT_LOW_TEMP -30
  112. #define CONFIG_SYS_DTT_HYSTERESIS 3
  113. #else
  114. #undef CONFIG_HARD_I2C
  115. #undef CONFIG_SOFT_I2C
  116. #endif
  117. /*
  118. * select serial console configuration
  119. *
  120. * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  121. * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  122. * for SCC).
  123. *
  124. * if CONFIG_CONS_NONE is defined, then the serial console routines must
  125. * defined elsewhere (for example, on the cogent platform, there are serial
  126. * ports on the motherboard which are used for the serial console - see
  127. * cogent/cma101/serial.[ch]).
  128. */
  129. #define CONFIG_CONS_ON_SMC /* define if console on SMC */
  130. #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
  131. #undef CONFIG_CONS_NONE /* define if console on something else*/
  132. #ifdef CONFIG_82xx_CONS_SMC1
  133. #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
  134. #endif
  135. #ifdef CONFIG_82xx_CONS_SMC2
  136. #define CONFIG_CONS_INDEX 2 /* which serial channel for console */
  137. #endif
  138. #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
  139. #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
  140. #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
  141. /*
  142. * select ethernet configuration
  143. *
  144. * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  145. * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  146. * for FCC)
  147. *
  148. * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  149. * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  150. *
  151. * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
  152. * X.29 connector, and FCC2 is hardwired to the X.1 connector)
  153. */
  154. #define CONFIG_SYS_FCC_ETHERNET
  155. #if defined(CONFIG_SYS_FCC_ETHERNET)
  156. #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
  157. #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
  158. #undef CONFIG_ETHER_NONE /* define if ether on something else */
  159. #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
  160. #else
  161. #define CONFIG_ETHER_ON_SCC /* define if ether on SCC */
  162. #undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
  163. #undef CONFIG_ETHER_NONE /* define if ether on something else */
  164. #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
  165. #endif
  166. #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
  167. /*
  168. * - RX clk is CLK11
  169. * - TX clk is CLK12
  170. */
  171. # define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
  172. #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  173. /*
  174. * - Rx-CLK is CLK13
  175. * - Tx-CLK is CLK14
  176. * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  177. * - Enable Full Duplex in FSMR
  178. */
  179. # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  180. # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  181. # define CONFIG_SYS_CPMFCR_RAMTYPE 0
  182. # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
  183. #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  184. #define CONFIG_MII /* MII PHY management */
  185. #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  186. /*
  187. * GPIO pins used for bit-banged MII communications
  188. */
  189. #define MDIO_PORT 2 /* Port C */
  190. #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
  191. (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
  192. #define MDC_DECLARE MDIO_DECLARE
  193. #if STK82xx_150
  194. #define CONFIG_SYS_MDIO_PIN 0x00008000 /* PC16 */
  195. #define CONFIG_SYS_MDC_PIN 0x00004000 /* PC17 */
  196. #endif
  197. #if STK82xx_100
  198. #define CONFIG_SYS_MDIO_PIN 0x00000002 /* PC30 */
  199. #define CONFIG_SYS_MDC_PIN 0x00000001 /* PC31 */
  200. #endif
  201. #if 1
  202. #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
  203. #define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
  204. #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
  205. #define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
  206. else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
  207. #define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
  208. else iop->pdat &= ~CONFIG_SYS_MDC_PIN
  209. #else
  210. #define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
  211. #define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
  212. #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
  213. #define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\
  214. else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}
  215. #define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\
  216. else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}
  217. #endif
  218. #define MIIDELAY udelay(1)
  219. /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
  220. #define CONFIG_8260_CLKIN 66666666 /* in Hz */
  221. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  222. #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  223. #undef CONFIG_WATCHDOG /* watchdog disabled */
  224. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  225. /*
  226. * BOOTP options
  227. */
  228. #define CONFIG_BOOTP_SUBNETMASK
  229. #define CONFIG_BOOTP_GATEWAY
  230. #define CONFIG_BOOTP_HOSTNAME
  231. #define CONFIG_BOOTP_BOOTPATH
  232. #define CONFIG_BOOTP_BOOTFILESIZE
  233. /*
  234. * Command line configuration.
  235. */
  236. #include <config_cmd_default.h>
  237. #define CONFIG_CMD_I2C
  238. #define CONFIG_CMD_DHCP
  239. #define CONFIG_CMD_MII
  240. #define CONFIG_CMD_NAND
  241. #define CONFIG_CMD_NFS
  242. #define CONFIG_CMD_PCI
  243. #define CONFIG_CMD_PING
  244. #define CONFIG_CMD_SNTP
  245. #if CONFIG_I2C
  246. #define CONFIG_CMD_I2C
  247. #define CONFIG_CMD_DATE
  248. #define CONFIG_CMD_DTT
  249. #define CONFIG_CMD_EEPROM
  250. #endif
  251. /*
  252. * Miscellaneous configurable options
  253. */
  254. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  255. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  256. #if 0
  257. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  258. #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
  259. #ifdef CONFIG_SYS_HUSH_PARSER
  260. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  261. #endif
  262. #endif
  263. #if defined(CONFIG_CMD_KGDB)
  264. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  265. #else
  266. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  267. #endif
  268. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  269. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  270. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  271. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  272. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  273. #define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */
  274. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  275. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  276. #define CONFIG_SYS_RESET_ADDRESS 0x40000104 /* "bad" address */
  277. /*
  278. * For booting Linux, the board info and command line data
  279. * have to be in the first 8 MB of memory, since this is
  280. * the maximum mapped by the Linux kernel during initialization.
  281. */
  282. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  283. /*-----------------------------------------------------------------------
  284. * CAN stuff
  285. *-----------------------------------------------------------------------
  286. */
  287. #define CONFIG_SYS_CAN_BASE 0x51000000
  288. #define CONFIG_SYS_CAN_SIZE 1
  289. #define CONFIG_SYS_CAN_BR ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK) |\
  290. BRx_PS_8 |\
  291. BRx_MS_UPMC |\
  292. BRx_V)
  293. #define CONFIG_SYS_CAN_OR (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\
  294. ORxU_BI)
  295. /* What should the base address of the main FLASH be and how big is
  296. * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk
  297. * The main FLASH is whichever is connected to *CS0.
  298. */
  299. #define CONFIG_SYS_FLASH0_BASE 0x40000000
  300. #define CONFIG_SYS_FLASH0_SIZE 32 /* 32 MB */
  301. /* Flash bank size (for preliminary settings)
  302. */
  303. #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
  304. /*-----------------------------------------------------------------------
  305. * FLASH organization
  306. */
  307. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
  308. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
  309. #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
  310. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
  311. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
  312. #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
  313. #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
  314. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
  315. #define CONFIG_SYS_UPDATE_FLASH_SIZE
  316. #define CONFIG_ENV_IS_IN_FLASH 1
  317. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
  318. #define CONFIG_ENV_SIZE 0x20000
  319. #define CONFIG_ENV_SECT_SIZE 0x20000
  320. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
  321. #define CONFIG_ENV_SIZE_REDUND 0x20000
  322. /* Where is the Hardwareinformation Block (from Monitor Sources) */
  323. #define MON_RES_LENGTH (0x0003FC00)
  324. #define HWIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
  325. #define HWIB_INFO_LEN 512
  326. #define CIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
  327. #define CIB_INFO_LEN 512
  328. #define CONFIG_SYS_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */
  329. #define CONFIG_SYS_HWINFO_SIZE 0x00000060 /* size of HW Info block */
  330. #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
  331. /*-----------------------------------------------------------------------
  332. * NAND-FLASH stuff
  333. *-----------------------------------------------------------------------
  334. */
  335. #if defined(CONFIG_CMD_NAND)
  336. #define CONFIG_SYS_NAND_CS_DIST 0x80
  337. #define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS 0x20
  338. #define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x40
  339. #define CONFIG_SYS_NAND_BR ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK) |\
  340. BRx_PS_8 |\
  341. BRx_MS_UPMB |\
  342. BRx_V)
  343. #define CONFIG_SYS_NAND_OR (MEG_TO_AM(CONFIG_SYS_NAND_SIZE) |\
  344. ORxU_BI |\
  345. ORxU_EHTR_8IDLE)
  346. #define CONFIG_SYS_NAND_SIZE 1
  347. #define CONFIG_SYS_NAND0_BASE 0x50000000
  348. #define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
  349. #define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
  350. #define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
  351. #define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */
  352. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
  353. CONFIG_SYS_NAND1_BASE, \
  354. CONFIG_SYS_NAND2_BASE, \
  355. CONFIG_SYS_NAND3_BASE, \
  356. }
  357. #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
  358. #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
  359. #define WRITE_NAND_UPM(d, adr, off) do \
  360. { \
  361. volatile unsigned char *addr = (unsigned char *) (adr + off); \
  362. WRITE_NAND(d, addr); \
  363. } while(0)
  364. #endif /* CONFIG_CMD_NAND */
  365. #define CONFIG_PCI
  366. #ifdef CONFIG_PCI
  367. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  368. #define CONFIG_PCI_PNP
  369. #define CONFIG_EEPRO100
  370. #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
  371. #define CONFIG_PCI_SCAN_SHOW
  372. #endif
  373. /*-----------------------------------------------------------------------
  374. * Hard Reset Configuration Words
  375. *
  376. * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  377. * defines for the various registers affected by the HRCW e.g. changing
  378. * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  379. */
  380. #if 0
  381. #define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
  382. # define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
  383. #else
  384. #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
  385. #endif
  386. /* no slaves so just fill with zeros */
  387. #define CONFIG_SYS_HRCW_SLAVE1 0
  388. #define CONFIG_SYS_HRCW_SLAVE2 0
  389. #define CONFIG_SYS_HRCW_SLAVE3 0
  390. #define CONFIG_SYS_HRCW_SLAVE4 0
  391. #define CONFIG_SYS_HRCW_SLAVE5 0
  392. #define CONFIG_SYS_HRCW_SLAVE6 0
  393. #define CONFIG_SYS_HRCW_SLAVE7 0
  394. /*-----------------------------------------------------------------------
  395. * Internal Memory Mapped Register
  396. */
  397. #define CONFIG_SYS_IMMR 0xFFF00000
  398. /*-----------------------------------------------------------------------
  399. * Definitions for initial stack pointer and data area (in DPRAM)
  400. */
  401. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
  402. #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
  403. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
  404. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  405. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  406. /*-----------------------------------------------------------------------
  407. * Start addresses for the final memory configuration
  408. * (Set up by the startup code)
  409. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  410. */
  411. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  412. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
  413. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
  414. #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
  415. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
  416. /*
  417. * Internal Definitions
  418. *
  419. * Boot Flags
  420. */
  421. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
  422. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  423. /*-----------------------------------------------------------------------
  424. * Cache Configuration
  425. */
  426. #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
  427. #if defined(CONFIG_CMD_KGDB)
  428. # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  429. #endif
  430. /*-----------------------------------------------------------------------
  431. * HIDx - Hardware Implementation-dependent Registers 2-11
  432. *-----------------------------------------------------------------------
  433. * HID0 also contains cache control - initially enable both caches and
  434. * invalidate contents, then the final state leaves only the instruction
  435. * cache enabled. Note that Power-On and Hard reset invalidate the caches,
  436. * but Soft reset does not.
  437. *
  438. * HID1 has only read-only information - nothing to set.
  439. */
  440. #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
  441. HID0_IFEM|HID0_ABE)
  442. #define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
  443. #define CONFIG_SYS_HID2 0
  444. /*-----------------------------------------------------------------------
  445. * RMR - Reset Mode Register 5-5
  446. *-----------------------------------------------------------------------
  447. * turn on Checkstop Reset Enable
  448. */
  449. #define CONFIG_SYS_RMR RMR_CSRE
  450. /*-----------------------------------------------------------------------
  451. * BCR - Bus Configuration 4-25
  452. *-----------------------------------------------------------------------
  453. */
  454. #define CONFIG_SYS_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */
  455. #define BCR_APD01 0x10000000
  456. #define CONFIG_SYS_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */
  457. /*-----------------------------------------------------------------------
  458. * SIUMCR - SIU Module Configuration 4-31
  459. *-----------------------------------------------------------------------
  460. */
  461. #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
  462. #define CONFIG_SYS_SIUMCR_LOW (SIUMCR_DPPC00)
  463. #define CONFIG_SYS_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE)
  464. #else
  465. #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00)
  466. #endif
  467. /*-----------------------------------------------------------------------
  468. * SYPCR - System Protection Control 4-35
  469. * SYPCR can only be written once after reset!
  470. *-----------------------------------------------------------------------
  471. * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  472. */
  473. #if defined(CONFIG_WATCHDOG)
  474. #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
  475. SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
  476. #else
  477. #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
  478. SYPCR_SWRI|SYPCR_SWP)
  479. #endif /* CONFIG_WATCHDOG */
  480. /*-----------------------------------------------------------------------
  481. * TMCNTSC - Time Counter Status and Control 4-40
  482. *-----------------------------------------------------------------------
  483. * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  484. * and enable Time Counter
  485. */
  486. #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
  487. /*-----------------------------------------------------------------------
  488. * PISCR - Periodic Interrupt Status and Control 4-42
  489. *-----------------------------------------------------------------------
  490. * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  491. * Periodic timer
  492. */
  493. #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
  494. /*-----------------------------------------------------------------------
  495. * SCCR - System Clock Control 9-8
  496. *-----------------------------------------------------------------------
  497. * Ensure DFBRG is Divide by 16
  498. */
  499. #define CONFIG_SYS_SCCR SCCR_DFBRG01
  500. /*-----------------------------------------------------------------------
  501. * RCCR - RISC Controller Configuration 13-7
  502. *-----------------------------------------------------------------------
  503. */
  504. #define CONFIG_SYS_RCCR 0
  505. /*
  506. * Init Memory Controller:
  507. *
  508. * Bank Bus Machine PortSz Device
  509. * ---- --- ------- ------ ------
  510. * 0 60x GPCM 32 bit FLASH
  511. * 1 60x SDRAM 64 bit SDRAM
  512. * 2 60x UPMB 8 bit NAND
  513. * 3 60x UPMC 8 bit CAN
  514. *
  515. */
  516. /* Initialize SDRAM
  517. */
  518. #undef CONFIG_SYS_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */
  519. #define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */
  520. /* Minimum mask to separate preliminary
  521. * address ranges for CS[0:2]
  522. */
  523. #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
  524. #define CONFIG_SYS_MPTPR 0x4000
  525. /*-----------------------------------------------------------------------------
  526. * Address for Mode Register Set (MRS) command
  527. *-----------------------------------------------------------------------------
  528. * In fact, the address is rather configuration data presented to the SDRAM on
  529. * its address lines. Because the address lines may be mux'ed externally either
  530. * for 8 column or 9 column devices, some bits appear twice in the 8260's
  531. * address:
  532. *
  533. * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
  534. * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
  535. * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
  536. * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
  537. * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
  538. *-----------------------------------------------------------------------------
  539. */
  540. #define CONFIG_SYS_MRS_OFFS 0x00000110
  541. /* Bank 0 - FLASH
  542. */
  543. #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
  544. BRx_PS_32 |\
  545. BRx_MS_GPCM_P |\
  546. BRx_V)
  547. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
  548. ORxG_CSNT |\
  549. ORxG_ACS_DIV4 |\
  550. ORxG_SCY_8_CLK |\
  551. ORxG_TRLX)
  552. /* SDRAM on TQM8272 can have either 8 or 9 columns.
  553. * The number affects configuration values.
  554. */
  555. /* Bank 1 - 60x bus SDRAM
  556. */
  557. #define CONFIG_SYS_PSRT 0x20 /* Low Value */
  558. /* #define CONFIG_SYS_PSRT 0x10 Fast Value */
  559. #define CONFIG_SYS_LSRT 0x20 /* Local Bus */
  560. #ifndef CONFIG_SYS_RAMBOOT
  561. #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
  562. BRx_PS_64 |\
  563. BRx_MS_SDRAM_P |\
  564. BRx_V)
  565. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL
  566. /* SDRAM initialization values for 8-column chips
  567. */
  568. #define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
  569. ORxS_BPD_4 |\
  570. ORxS_ROWST_PBI1_A7 |\
  571. ORxS_NUMR_12)
  572. #define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
  573. PSDMR_SDAM_A15_IS_A5 |\
  574. PSDMR_BSMA_A12_A14 |\
  575. PSDMR_SDA10_PBI1_A8 |\
  576. PSDMR_RFRC_7_CLK |\
  577. PSDMR_PRETOACT_2W |\
  578. PSDMR_ACTTORW_2W |\
  579. PSDMR_LDOTOPRE_1C |\
  580. PSDMR_WRC_2C |\
  581. PSDMR_EAMUX |\
  582. PSDMR_BUFCMD |\
  583. PSDMR_CL_2)
  584. /* SDRAM initialization values for 9-column chips
  585. */
  586. #define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
  587. ORxS_BPD_4 |\
  588. ORxS_ROWST_PBI1_A5 |\
  589. ORxS_NUMR_13)
  590. #define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
  591. PSDMR_SDAM_A16_IS_A5 |\
  592. PSDMR_BSMA_A12_A14 |\
  593. PSDMR_SDA10_PBI1_A7 |\
  594. PSDMR_RFRC_7_CLK |\
  595. PSDMR_PRETOACT_2W |\
  596. PSDMR_ACTTORW_2W |\
  597. PSDMR_LDOTOPRE_1C |\
  598. PSDMR_WRC_2C |\
  599. PSDMR_EAMUX |\
  600. PSDMR_BUFCMD |\
  601. PSDMR_CL_2)
  602. #define CONFIG_SYS_OR1_10COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
  603. ORxS_BPD_4 |\
  604. ORxS_ROWST_PBI1_A4 |\
  605. ORxS_NUMR_13)
  606. #define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\
  607. PSDMR_SDAM_A17_IS_A5 |\
  608. PSDMR_BSMA_A12_A14 |\
  609. PSDMR_SDA10_PBI1_A4 |\
  610. PSDMR_RFRC_6_CLK |\
  611. PSDMR_PRETOACT_2W |\
  612. PSDMR_ACTTORW_2W |\
  613. PSDMR_LDOTOPRE_1C |\
  614. PSDMR_WRC_2C |\
  615. PSDMR_EAMUX |\
  616. PSDMR_BUFCMD |\
  617. PSDMR_CL_2)
  618. #define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */
  619. #define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */
  620. #define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */
  621. #define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */
  622. #define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */
  623. #define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */
  624. #define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */
  625. #define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */
  626. #define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */
  627. #define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */
  628. #define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */
  629. #define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */
  630. #define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */
  631. #define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */
  632. #define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */
  633. #define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */
  634. #define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */
  635. #define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */
  636. #define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */
  637. #define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */
  638. #define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */
  639. #define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */
  640. #define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */
  641. #define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */
  642. #endif /* CONFIG_SYS_RAMBOOT */
  643. #endif /* __CONFIG_H */