SIMPC8313.h 17 KB

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  1. /*
  2. * Copyright (C) Sheldon Instruments, Inc. 2008
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. /*
  23. * simpc8313 board configuration file
  24. */
  25. #ifndef __CONFIG_H
  26. #define __CONFIG_H
  27. /*
  28. * High Level Configuration Options
  29. */
  30. #define CONFIG_NAND_U_BOOT
  31. #define CONFIG_E300 1
  32. #define CONFIG_MPC83xx 1
  33. #define CONFIG_MPC831x 1
  34. #define CONFIG_MPC8313 1
  35. #define CONFIG_PCI
  36. #define CONFIG_MISC_INIT_R
  37. /*
  38. * On-board devices
  39. *
  40. * TSEC1 is Marvell PHY 88E1118
  41. */
  42. #define CONFIG_SYS_33MHZ
  43. #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
  44. #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
  45. #define CONFIG_SYS_IMMR 0xE0000000
  46. #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  47. #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
  48. #endif
  49. #define CONFIG_SYS_MEMTEST_START 0x00001000
  50. #define CONFIG_SYS_MEMTEST_END 0x07f00000
  51. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
  52. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
  53. /*
  54. * Device configurations
  55. */
  56. #define CONFIG_TSEC1
  57. /*
  58. * DDR Setup
  59. */
  60. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  61. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  62. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  63. #define CONFIG_VERY_BIG_RAM
  64. #define CONFIG_MAX_MEM_MAPPED (512 << 20)
  65. #define CONFIG_SYS_DDRCDR ( DDRCDR_EN \
  66. | DDRCDR_PZ_NOMZ \
  67. | DDRCDR_NZ_NOMZ \
  68. | DDRCDR_M_ODR )
  69. /* 0x73000002 TODO ODR & DRN ? */
  70. /*
  71. * FLASH on the Local Bus
  72. */
  73. #define CONFIG_SYS_NO_FLASH
  74. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  75. #if !defined(CONFIG_NAND_SPL)
  76. #define CONFIG_SYS_RAMBOOT
  77. #endif
  78. #define CONFIG_SYS_INIT_RAM_LOCK 1
  79. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
  80. #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
  81. #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
  82. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  83. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  84. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  85. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  86. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  87. /*
  88. * Local Bus LCRR and LBCR regs
  89. */
  90. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  91. #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
  92. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
  93. #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
  94. | (0xFF << LBCR_BMT_SHIFT) \
  95. | 0xF ) /* 0x0004ff0f */
  96. #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
  97. /* drivers/mtd/nand/nand.c */
  98. #ifdef CONFIG_NAND_SPL
  99. #define CONFIG_SYS_NAND_BASE 0xFFF00000
  100. #else
  101. #define CONFIG_SYS_NAND_BASE 0xE2800000
  102. #endif
  103. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  104. #define NAND_MAX_CHIPS 1
  105. #define CONFIG_MTD_NAND_VERIFY_WRITE
  106. #define CONFIG_CMD_NAND 1
  107. #define CONFIG_NAND_FSL_ELBC 1
  108. #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
  109. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
  110. #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  111. #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  112. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  113. #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
  114. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  115. | BR_PS_8 /* Port Size = 8 bit */ \
  116. | BR_MS_FCM /* MSEL = FCM */ \
  117. | BR_V ) /* valid */
  118. #ifdef CONFIG_NAND_SP
  119. #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \
  120. | OR_FCM_CSCT \
  121. | OR_FCM_CST \
  122. | OR_FCM_CHT \
  123. | OR_FCM_SCY_1 \
  124. | OR_FCM_TRLX \
  125. | OR_FCM_EHTR )
  126. #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */
  127. #define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
  128. #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
  129. #define NAND_CACHE_PAGES 32
  130. #elif defined(CONFIG_NAND_LP)
  131. #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \
  132. | OR_FCM_PGS \
  133. | OR_FCM_CSCT \
  134. | OR_FCM_CST \
  135. | OR_FCM_CHT \
  136. | OR_FCM_SCY_1 \
  137. | OR_FCM_TRLX \
  138. | OR_FCM_EHTR )
  139. #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */
  140. #define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */
  141. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
  142. #define NAND_CACHE_PAGES 64
  143. #else
  144. #error Page size of NAND not defined.
  145. #endif /* CONFIG_NAND_SP */
  146. #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE
  147. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
  148. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
  149. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
  150. #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
  151. #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
  152. /*
  153. * JFFS2 configuration
  154. */
  155. #define CONFIG_JFFS2_NAND
  156. #define CONFIG_JFFS2_DEV "nand0"
  157. /* mtdparts command line support */
  158. #define CONFIG_CMD_MTDPARTS
  159. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  160. #define MTDIDS_DEFAULT "nand0=nand0"
  161. #define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
  162. /* pass open firmware flat tree */
  163. #define CONFIG_OF_LIBFDT 1
  164. #define CONFIG_OF_BOARD_SETUP 1
  165. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  166. /*
  167. * Serial Port
  168. */
  169. #define CONFIG_CONS_INDEX 1
  170. #define CONFIG_SYS_NS16550
  171. #define CONFIG_SYS_NS16550_SERIAL
  172. #define CONFIG_SYS_NS16550_REG_SIZE 1
  173. #ifdef CONFIG_NAND_SPL
  174. #define CONFIG_NS16550_MIN_FUNCTIONS
  175. #endif
  176. #define CONFIG_SYS_BAUDRATE_TABLE \
  177. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  178. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  179. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  180. /* Use the HUSH parser */
  181. #define CONFIG_SYS_HUSH_PARSER
  182. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  183. /* I2C */
  184. #define CONFIG_HARD_I2C /* I2C with hardware support*/
  185. #define CONFIG_FSL_I2C
  186. #define CONFIG_I2C_MULTI_BUS
  187. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  188. #define CONFIG_SYS_I2C_SLAVE 0x7F
  189. #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
  190. #define CONFIG_SYS_I2C_OFFSET 0x3000
  191. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  192. /*
  193. * General PCI
  194. * Addresses are mapped 1-1.
  195. */
  196. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  197. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  198. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  199. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  200. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  201. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  202. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  203. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  204. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  205. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  206. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  207. /*
  208. * TSEC
  209. */
  210. #define CONFIG_TSEC_ENET /* TSEC ethernet support */
  211. #define CONFIG_NET_MULTI
  212. #define CONFIG_GMII /* MII PHY management */
  213. #ifdef CONFIG_TSEC1
  214. #define CONFIG_HAS_ETH0
  215. #define CONFIG_TSEC1_NAME "TSEC0"
  216. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  217. #define TSEC1_PHY_ADDR 0x0
  218. #define TSEC1_FLAGS TSEC_GIGABIT
  219. #define TSEC1_PHYIDX 0
  220. #endif
  221. #ifdef CONFIG_TSEC2
  222. #define CONFIG_HAS_ETH1
  223. #define CONFIG_TSEC2_NAME "TSEC1"
  224. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  225. #define TSEC2_PHY_ADDR 4
  226. #define TSEC2_FLAGS TSEC_GIGABIT
  227. #define TSEC2_PHYIDX 0
  228. #endif
  229. /* Options are: TSEC[0-1] */
  230. #define CONFIG_ETHPRIME "TSEC1"
  231. /*
  232. * Configure on-board RTC
  233. */
  234. #define CONFIG_RTC_DS1337
  235. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  236. /*
  237. * Environment
  238. */
  239. #if defined(CONFIG_NAND_U_BOOT)
  240. #define CONFIG_ENV_IS_IN_NAND 1
  241. #define CONFIG_ENV_OFFSET (768 * 1024)
  242. #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  243. #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  244. #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  245. #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
  246. #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
  247. #elif !defined(CONFIG_SYS_RAMBOOT)
  248. #define CONFIG_ENV_IS_IN_FLASH 1
  249. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  250. #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
  251. #define CONFIG_ENV_SIZE 0x2000
  252. /* Address and size of Redundant Environment Sector */
  253. #else
  254. #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  255. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  256. #define CONFIG_ENV_SIZE 0x2000
  257. #endif
  258. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  259. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  260. /*
  261. * BOOTP options
  262. */
  263. #define CONFIG_BOOTP_BOOTFILESIZE
  264. #define CONFIG_BOOTP_BOOTPATH
  265. #define CONFIG_BOOTP_GATEWAY
  266. #define CONFIG_BOOTP_HOSTNAME
  267. /*
  268. * Command line configuration.
  269. */
  270. #include <config_cmd_default.h>
  271. #undef CONFIG_CMD_IMLS
  272. #undef CONFIG_CMD_FLASH
  273. #define CONFIG_CMD_PING
  274. #define CONFIG_CMD_DHCP
  275. #define CONFIG_CMD_I2C
  276. #define CONFIG_CMD_MII
  277. #define CONFIG_CMD_DATE
  278. #define CONFIG_CMD_PCI
  279. #define CONFIG_CMD_JFFS2
  280. #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
  281. #undef CONFIG_CMD_SAVEENV
  282. #undef CONFIG_CMD_LOADS
  283. #endif
  284. #define CONFIG_CMDLINE_EDITING 1
  285. /*
  286. * Miscellaneous configurable options
  287. */
  288. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  289. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  290. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  291. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  292. #define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \
  293. + sizeof(CONFIG_SYS_PROMPT) \
  294. + 16 ) /* Print Buffer Size */
  295. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  296. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  297. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  298. /*
  299. * For booting Linux, the board info and command line data
  300. * have to be in the first 8 MB of memory, since this is
  301. * the maximum mapped by the Linux kernel during initialization.
  302. */
  303. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  304. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  305. #define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
  306. | 0x20000000 /* reserved */ \
  307. | HRCWL_DDR_TO_SCB_CLK_2X1 \
  308. | HRCWL_CSB_TO_CLKIN_4X1 \
  309. | HRCWL_CORE_TO_CSB_2_5X1 )
  310. #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
  311. #define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \
  312. | HRCWH_PCI1_ARBITER_ENABLE \
  313. | HRCWH_CORE_ENABLE \
  314. | HRCWH_BOOTSEQ_DISABLE \
  315. | HRCWH_SW_WATCHDOG_DISABLE \
  316. | HRCWH_TSEC1M_IN_RGMII \
  317. | HRCWH_TSEC2M_IN_RGMII \
  318. | HRCWH_BIG_ENDIAN \
  319. | HRCWH_LALE_NORMAL )
  320. #ifdef CONFIG_NAND_LP
  321. #define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
  322. | HRCWH_FROM_0XFFF00100 \
  323. | HRCWH_ROM_LOC_NAND_LP_8BIT \
  324. | HRCWH_RL_EXT_NAND)
  325. #else
  326. #define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
  327. | HRCWH_FROM_0XFFF00100 \
  328. | HRCWH_ROM_LOC_NAND_SP_8BIT \
  329. | HRCWH_RL_EXT_NAND )
  330. #endif
  331. /* System IO Config */
  332. #define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \
  333. | SICRH_ETSEC2_C \
  334. | SICRH_ETSEC2_D \
  335. | SICRH_ETSEC2_E \
  336. | SICRH_ETSEC2_F \
  337. | SICRH_ETSEC2_G \
  338. | SICRH_TSOBI1 \
  339. | SICRH_TSOBI2 )
  340. #define CONFIG_SYS_SICRL (SICRL_USBDR \
  341. | SICRL_ETSEC2_A )
  342. #define CONFIG_SYS_HID0_INIT 0x000000000
  343. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
  344. | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
  345. #define CONFIG_SYS_HID2 HID2_HBE
  346. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  347. /* DDR @ 0x00000000 */
  348. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
  349. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  350. #define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10)
  351. #define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)
  352. /* PCI @ 0x80000000 */
  353. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
  354. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  355. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  356. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  357. /* PCI2 not supported on 8313 */
  358. #define CONFIG_SYS_IBAT4L (0)
  359. #define CONFIG_SYS_IBAT4U (0)
  360. /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
  361. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  362. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
  363. /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
  364. #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
  365. #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  366. #define CONFIG_SYS_IBAT7L (0)
  367. #define CONFIG_SYS_IBAT7U (0)
  368. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  369. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  370. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  371. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  372. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  373. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  374. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  375. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  376. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  377. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  378. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  379. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  380. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  381. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  382. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  383. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  384. /*
  385. * Internal Definitions
  386. *
  387. * Boot Flags
  388. */
  389. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  390. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  391. /*
  392. * Environment Configuration
  393. */
  394. #define CONFIG_ENV_OVERWRITE
  395. #define CONFIG_NETDEV eth1
  396. #define CONFIG_HOSTNAME simpc8313
  397. #define CONFIG_ROOTPATH /tftpboot/
  398. #define CONFIG_BOOTFILE /tftpboot/uImage
  399. #define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */
  400. #define CONFIG_FDTFILE simpc8313.dtb
  401. #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
  402. #define CONFIG_BOOTDELAY 5 /* 5 second delay */
  403. #define CONFIG_BAUDRATE 115200
  404. #define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"
  405. #define XMK_STR(x) #x
  406. #define MK_STR(x) XMK_STR(x)
  407. #define CONFIG_EXTRA_ENV_SETTINGS \
  408. "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
  409. "ethprime=TSEC1\0" \
  410. "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
  411. "tftpflash=tftpboot $loadaddr $uboot; " \
  412. "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
  413. "erase " MK_STR(TEXT_BASE) " +$filesize; " \
  414. "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
  415. "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
  416. "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
  417. "fdtaddr=ae0000\0" \
  418. "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
  419. "console=ttyS0\0" \
  420. "setbootargs=setenv bootargs " \
  421. "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
  422. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  423. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  424. "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
  425. "load_uboot=tftp 100000 u-boot-nand.bin\0" \
  426. "burn_uboot=nand erase u-boot 80000; " \
  427. "nand write 100000 u-boot $filesize\0" \
  428. "update_uboot=run load_uboot;run burn_uboot\0" \
  429. "mtdids=nand0=nand0\0" \
  430. "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \
  431. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  432. "nfsroot=${serverip}:${rootpath}\0" \
  433. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  434. "addip=setenv bootargs ${bootargs} " \
  435. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  436. ":${hostname}:${netdev}:off panic=1\0" \
  437. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
  438. "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
  439. "console=ttyS0,115200\0" \
  440. ""
  441. #define CONFIG_NFSBOOTCOMMAND \
  442. "setenv rootdev /dev/nfs;" \
  443. "run setbootargs;" \
  444. "run setipargs;" \
  445. "tftp $loadaddr $bootfile;" \
  446. "tftp $fdtaddr $fdtfile;" \
  447. "bootm $loadaddr - $fdtaddr"
  448. #define CONFIG_RAMBOOTCOMMAND \
  449. "setenv rootdev /dev/ram;" \
  450. "run setbootargs;" \
  451. "tftp $ramdiskaddr $ramdiskfile;" \
  452. "tftp $loadaddr $bootfile;" \
  453. "tftp $fdtaddr $fdtfile;" \
  454. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  455. #undef MK_STR
  456. #undef XMK_STR
  457. #endif /* __CONFIG_H */