PPChameleonEVB.h 28 KB

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  1. /*
  2. * (C) Copyright 2003-2005
  3. * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
  4. *
  5. * (C) Copyright 2003
  6. * DAVE Srl
  7. *
  8. * http://www.dave-tech.it
  9. * http://www.wawnet.biz
  10. * mailto:info@wawnet.biz
  11. *
  12. * Credits: Stefan Roese, Wolfgang Denk
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. /*
  30. * board/config.h - configuration options, board specific
  31. */
  32. #ifndef __CONFIG_H
  33. #define __CONFIG_H
  34. #define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
  35. #define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
  36. #define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
  37. #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
  38. #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
  39. #endif
  40. /* Only one of the following two symbols must be defined (default is 25 MHz)
  41. * CONFIG_PPCHAMELEON_CLK_25
  42. * CONFIG_PPCHAMELEON_CLK_33
  43. */
  44. #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
  45. #define CONFIG_PPCHAMELEON_CLK_25
  46. #endif
  47. #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
  48. #error "* Two external frequencies (SysClk) are defined! *"
  49. #endif
  50. #undef CONFIG_PPCHAMELEON_SMI712
  51. /*
  52. * Debug stuff
  53. */
  54. #undef __DEBUG_START_FROM_SRAM__
  55. #define __DISABLE_MACHINE_EXCEPTION__
  56. #ifdef __DEBUG_START_FROM_SRAM__
  57. #define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
  58. #endif
  59. /*
  60. * High Level Configuration Options
  61. * (easy to change)
  62. */
  63. #define CONFIG_405EP 1 /* This is a PPC405 CPU */
  64. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  65. #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
  66. #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
  67. #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
  68. #ifdef CONFIG_PPCHAMELEON_CLK_25
  69. # define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
  70. #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
  71. # define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
  72. #else
  73. # error "* External frequency (SysClk) not defined! *"
  74. #endif
  75. #define CONFIG_BAUDRATE 115200
  76. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  77. #undef CONFIG_BOOTARGS
  78. /* Ethernet stuff */
  79. #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
  80. #define CONFIG_ETHADDR 00:50:c2:1e:af:fe
  81. #define CONFIG_HAS_ETH1
  82. #define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
  83. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  84. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  85. #undef CONFIG_EXT_PHY
  86. #define CONFIG_NET_MULTI 1
  87. #define CONFIG_PPC4xx_EMAC
  88. #define CONFIG_MII 1 /* MII PHY management */
  89. #ifndef CONFIG_EXT_PHY
  90. #define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
  91. #define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
  92. #else
  93. #define CONFIG_PHY_ADDR 2 /* PHY address */
  94. #endif
  95. #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
  96. /*
  97. * BOOTP options
  98. */
  99. #define CONFIG_BOOTP_BOOTFILESIZE
  100. #define CONFIG_BOOTP_BOOTPATH
  101. #define CONFIG_BOOTP_GATEWAY
  102. #define CONFIG_BOOTP_HOSTNAME
  103. /*
  104. * Command line configuration.
  105. */
  106. #include <config_cmd_default.h>
  107. #define CONFIG_CMD_DATE
  108. #define CONFIG_CMD_DHCP
  109. #define CONFIG_CMD_ELF
  110. #define CONFIG_CMD_EEPROM
  111. #define CONFIG_CMD_I2C
  112. #define CONFIG_CMD_IRQ
  113. #define CONFIG_CMD_JFFS2
  114. #define CONFIG_CMD_MII
  115. #define CONFIG_CMD_NAND
  116. #define CONFIG_CMD_NFS
  117. #define CONFIG_CMD_PCI
  118. #define CONFIG_CMD_SNTP
  119. #define CONFIG_MAC_PARTITION
  120. #define CONFIG_DOS_PARTITION
  121. #undef CONFIG_WATCHDOG /* watchdog disabled */
  122. #define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */
  123. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  124. #define CONFIG_SYS_M41T11_BASE_YEAR 1900
  125. /*
  126. * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  127. */
  128. #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  129. /* SDRAM timings used in datasheet */
  130. #define CONFIG_SYS_SDRAM_CL 2
  131. #define CONFIG_SYS_SDRAM_tRP 20
  132. #define CONFIG_SYS_SDRAM_tRC 65
  133. #define CONFIG_SYS_SDRAM_tRCD 20
  134. #undef CONFIG_SYS_SDRAM_tRFC
  135. /*
  136. * Miscellaneous configurable options
  137. */
  138. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  139. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  140. #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  141. #ifdef CONFIG_SYS_HUSH_PARSER
  142. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  143. #endif
  144. #if defined(CONFIG_CMD_KGDB)
  145. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  146. #else
  147. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  148. #endif
  149. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  150. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  151. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  152. #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
  153. #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
  154. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  155. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  156. #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
  157. #define CONFIG_SYS_BASE_BAUD 691200
  158. /* The following table includes the supported baudrates */
  159. #define CONFIG_SYS_BAUDRATE_TABLE \
  160. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  161. 57600, 115200, 230400, 460800, 921600 }
  162. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  163. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  164. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  165. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  166. /*-----------------------------------------------------------------------
  167. * NAND-FLASH stuff
  168. *-----------------------------------------------------------------------
  169. */
  170. /*
  171. * nand device 1 on dave (PPChameleonEVB) needs more time,
  172. * so we just introduce additional wait in nand_wait(),
  173. * effectively for both devices.
  174. */
  175. #define PPCHAMELON_NAND_TIMER_HACK
  176. #define CONFIG_SYS_NAND0_BASE 0xFF400000
  177. #define CONFIG_SYS_NAND1_BASE 0xFF000000
  178. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE }
  179. #define NAND_BIG_DELAY_US 25
  180. #define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
  181. #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
  182. #define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
  183. #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
  184. #define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
  185. #define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
  186. #define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
  187. #define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
  188. #define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
  189. #define MACRO_NAND_DISABLE_CE(nandptr) do \
  190. { \
  191. switch((unsigned long)nandptr) \
  192. { \
  193. case CONFIG_SYS_NAND0_BASE: \
  194. out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
  195. break; \
  196. case CONFIG_SYS_NAND1_BASE: \
  197. out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
  198. break; \
  199. } \
  200. } while(0)
  201. #define MACRO_NAND_ENABLE_CE(nandptr) do \
  202. { \
  203. switch((unsigned long)nandptr) \
  204. { \
  205. case CONFIG_SYS_NAND0_BASE: \
  206. out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
  207. break; \
  208. case CONFIG_SYS_NAND1_BASE: \
  209. out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
  210. break; \
  211. } \
  212. } while(0)
  213. #define MACRO_NAND_CTL_CLRALE(nandptr) do \
  214. { \
  215. switch((unsigned long)nandptr) \
  216. { \
  217. case CONFIG_SYS_NAND0_BASE: \
  218. out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
  219. break; \
  220. case CONFIG_SYS_NAND1_BASE: \
  221. out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
  222. break; \
  223. } \
  224. } while(0)
  225. #define MACRO_NAND_CTL_SETALE(nandptr) do \
  226. { \
  227. switch((unsigned long)nandptr) \
  228. { \
  229. case CONFIG_SYS_NAND0_BASE: \
  230. out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
  231. break; \
  232. case CONFIG_SYS_NAND1_BASE: \
  233. out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
  234. break; \
  235. } \
  236. } while(0)
  237. #define MACRO_NAND_CTL_CLRCLE(nandptr) do \
  238. { \
  239. switch((unsigned long)nandptr) \
  240. { \
  241. case CONFIG_SYS_NAND0_BASE: \
  242. out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
  243. break; \
  244. case CONFIG_SYS_NAND1_BASE: \
  245. out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
  246. break; \
  247. } \
  248. } while(0)
  249. #define MACRO_NAND_CTL_SETCLE(nandptr) do { \
  250. switch((unsigned long)nandptr) { \
  251. case CONFIG_SYS_NAND0_BASE: \
  252. out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
  253. break; \
  254. case CONFIG_SYS_NAND1_BASE: \
  255. out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
  256. break; \
  257. } \
  258. } while(0)
  259. /*-----------------------------------------------------------------------
  260. * PCI stuff
  261. *-----------------------------------------------------------------------
  262. */
  263. #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
  264. #define PCI_HOST_FORCE 1 /* configure as pci host */
  265. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  266. #define CONFIG_PCI /* include pci support */
  267. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  268. #undef CONFIG_PCI_PNP /* do pci plug-and-play */
  269. /* resource configuration */
  270. #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
  271. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
  272. #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
  273. #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
  274. #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
  275. #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
  276. #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  277. #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
  278. #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
  279. #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
  280. /*-----------------------------------------------------------------------
  281. * Start addresses for the final memory configuration
  282. * (Set up by the startup code)
  283. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  284. */
  285. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  286. /* Reserve 256 kB for Monitor */
  287. /*
  288. #define CONFIG_SYS_FLASH_BASE 0xFFFC0000
  289. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  290. #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
  291. */
  292. /* Reserve 320 kB for Monitor */
  293. #define CONFIG_SYS_FLASH_BASE 0xFFFB0000
  294. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  295. #define CONFIG_SYS_MONITOR_LEN (320 * 1024)
  296. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
  297. /*
  298. * For booting Linux, the board info and command line data
  299. * have to be in the first 8 MB of memory, since this is
  300. * the maximum mapped by the Linux kernel during initialization.
  301. */
  302. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  303. /*-----------------------------------------------------------------------
  304. * FLASH organization
  305. */
  306. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  307. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  308. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  309. #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
  310. #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
  311. #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
  312. #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
  313. /*
  314. * The following defines are added for buggy IOP480 byte interface.
  315. * All other boards should use the standard values (CPCI405 etc.)
  316. */
  317. #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
  318. #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
  319. #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
  320. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  321. /*-----------------------------------------------------------------------
  322. * Environment Variable setup
  323. */
  324. #ifdef ENVIRONMENT_IN_EEPROM
  325. #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
  326. #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
  327. #define CONFIG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
  328. #else /* DEFAULT: environment in flash, using redundand flash sectors */
  329. #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  330. #define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
  331. #define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
  332. #define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
  333. #define CONFIG_ENV_SIZE_REDUND 0x2000
  334. #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
  335. #endif /* ENVIRONMENT_IN_EEPROM */
  336. #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
  337. #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
  338. /*-----------------------------------------------------------------------
  339. * I2C EEPROM (CAT24WC16) for environment
  340. */
  341. #define CONFIG_HARD_I2C /* I2c with hardware support */
  342. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  343. #define CONFIG_SYS_I2C_SLAVE 0x7F
  344. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
  345. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  346. /* mask of address bits that overflow into the "EEPROM chip address" */
  347. /*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
  348. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
  349. /* 16 byte page write mode using*/
  350. /* last 4 bits of the address */
  351. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  352. /*
  353. * Init Memory Controller:
  354. *
  355. * BR0/1 and OR0/1 (FLASH)
  356. */
  357. #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
  358. /*-----------------------------------------------------------------------
  359. * External Bus Controller (EBC) Setup
  360. */
  361. /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
  362. #define CONFIG_SYS_EBC_PB0AP 0x92015480
  363. #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
  364. /* Memory Bank 1 (External SRAM) initialization */
  365. /* Since this must replace NOR Flash, we use the same settings for CS0 */
  366. #define CONFIG_SYS_EBC_PB1AP 0x92015480
  367. #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
  368. /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
  369. #define CONFIG_SYS_EBC_PB2AP 0x92015480
  370. #define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
  371. /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
  372. #define CONFIG_SYS_EBC_PB3AP 0x92015480
  373. #define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
  374. #ifdef CONFIG_PPCHAMELEON_SMI712
  375. /*
  376. * Video console (graphic: SMI LynxEM)
  377. */
  378. #define CONFIG_VIDEO
  379. #define CONFIG_CFB_CONSOLE
  380. #define CONFIG_VIDEO_SMI_LYNXEM
  381. #define CONFIG_VIDEO_LOGO
  382. /*#define CONFIG_VIDEO_BMP_LOGO*/
  383. #define CONFIG_CONSOLE_EXTRA_INFO
  384. #define CONFIG_VGA_AS_SINGLE_DEVICE
  385. /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
  386. #define CONFIG_SYS_ISA_IO 0xE8000000
  387. /* see also drivers/video/videomodes.c */
  388. #define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
  389. #endif
  390. /*-----------------------------------------------------------------------
  391. * FPGA stuff
  392. */
  393. /* FPGA internal regs */
  394. #define CONFIG_SYS_FPGA_MODE 0x00
  395. #define CONFIG_SYS_FPGA_STATUS 0x02
  396. #define CONFIG_SYS_FPGA_TS 0x04
  397. #define CONFIG_SYS_FPGA_TS_LOW 0x06
  398. #define CONFIG_SYS_FPGA_TS_CAP0 0x10
  399. #define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
  400. #define CONFIG_SYS_FPGA_TS_CAP1 0x14
  401. #define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
  402. #define CONFIG_SYS_FPGA_TS_CAP2 0x18
  403. #define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
  404. #define CONFIG_SYS_FPGA_TS_CAP3 0x1c
  405. #define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
  406. /* FPGA Mode Reg */
  407. #define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
  408. #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
  409. #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
  410. #define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
  411. /* FPGA Status Reg */
  412. #define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
  413. #define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
  414. #define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
  415. #define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
  416. #define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
  417. #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
  418. #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
  419. /* FPGA program pin configuration */
  420. #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
  421. #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
  422. #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
  423. #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
  424. #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
  425. /*-----------------------------------------------------------------------
  426. * Definitions for initial stack pointer and data area (in data cache)
  427. */
  428. /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
  429. #define CONFIG_SYS_TEMP_STACK_OCM 1
  430. /* On Chip Memory location */
  431. #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
  432. #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
  433. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
  434. #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
  435. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  436. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  437. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  438. /*-----------------------------------------------------------------------
  439. * Definitions for GPIO setup (PPC405EP specific)
  440. *
  441. * GPIO0[0] - External Bus Controller BLAST output
  442. * GPIO0[1-9] - Instruction trace outputs -> GPIO
  443. * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  444. * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  445. * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  446. * GPIO0[24-27] - UART0 control signal inputs/outputs
  447. * GPIO0[28-29] - UART1 data signal input/output
  448. * GPIO0[30] - EMAC0 input
  449. * GPIO0[31] - EMAC1 reject packet as output
  450. */
  451. #define CONFIG_SYS_GPIO0_OSRH 0x40000550
  452. #define CONFIG_SYS_GPIO0_OSRL 0x00000110
  453. #define CONFIG_SYS_GPIO0_ISR1H 0x00000000
  454. /*#define CONFIG_SYS_GPIO0_ISR1L 0x15555445*/
  455. #define CONFIG_SYS_GPIO0_ISR1L 0x15555444
  456. #define CONFIG_SYS_GPIO0_TSRH 0x00000000
  457. #define CONFIG_SYS_GPIO0_TSRL 0x00000000
  458. #define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
  459. /*
  460. * Internal Definitions
  461. *
  462. * Boot Flags
  463. */
  464. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  465. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  466. #define CONFIG_NO_SERIAL_EEPROM
  467. /*--------------------------------------------------------------------*/
  468. #ifdef CONFIG_NO_SERIAL_EEPROM
  469. /*
  470. !-----------------------------------------------------------------------
  471. ! Defines for entry options.
  472. ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
  473. ! are plugged in the board will be utilized as non-ECC DIMMs.
  474. !-----------------------------------------------------------------------
  475. */
  476. #undef AUTO_MEMORY_CONFIG
  477. #define DIMM_READ_ADDR 0xAB
  478. #define DIMM_WRITE_ADDR 0xAA
  479. #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
  480. #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
  481. #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
  482. #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
  483. #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
  484. #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
  485. #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
  486. #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
  487. #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
  488. #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
  489. /* Defines for CPC0_PLLMR1 Register fields */
  490. #define PLL_ACTIVE 0x80000000
  491. #define CPC0_PLLMR1_SSCS 0x80000000
  492. #define PLL_RESET 0x40000000
  493. #define CPC0_PLLMR1_PLLR 0x40000000
  494. /* Feedback multiplier */
  495. #define PLL_FBKDIV 0x00F00000
  496. #define CPC0_PLLMR1_FBDV 0x00F00000
  497. #define PLL_FBKDIV_16 0x00000000
  498. #define PLL_FBKDIV_1 0x00100000
  499. #define PLL_FBKDIV_2 0x00200000
  500. #define PLL_FBKDIV_3 0x00300000
  501. #define PLL_FBKDIV_4 0x00400000
  502. #define PLL_FBKDIV_5 0x00500000
  503. #define PLL_FBKDIV_6 0x00600000
  504. #define PLL_FBKDIV_7 0x00700000
  505. #define PLL_FBKDIV_8 0x00800000
  506. #define PLL_FBKDIV_9 0x00900000
  507. #define PLL_FBKDIV_10 0x00A00000
  508. #define PLL_FBKDIV_11 0x00B00000
  509. #define PLL_FBKDIV_12 0x00C00000
  510. #define PLL_FBKDIV_13 0x00D00000
  511. #define PLL_FBKDIV_14 0x00E00000
  512. #define PLL_FBKDIV_15 0x00F00000
  513. /* Forward A divisor */
  514. #define PLL_FWDDIVA 0x00070000
  515. #define CPC0_PLLMR1_FWDVA 0x00070000
  516. #define PLL_FWDDIVA_8 0x00000000
  517. #define PLL_FWDDIVA_7 0x00010000
  518. #define PLL_FWDDIVA_6 0x00020000
  519. #define PLL_FWDDIVA_5 0x00030000
  520. #define PLL_FWDDIVA_4 0x00040000
  521. #define PLL_FWDDIVA_3 0x00050000
  522. #define PLL_FWDDIVA_2 0x00060000
  523. #define PLL_FWDDIVA_1 0x00070000
  524. /* Forward B divisor */
  525. #define PLL_FWDDIVB 0x00007000
  526. #define CPC0_PLLMR1_FWDVB 0x00007000
  527. #define PLL_FWDDIVB_8 0x00000000
  528. #define PLL_FWDDIVB_7 0x00001000
  529. #define PLL_FWDDIVB_6 0x00002000
  530. #define PLL_FWDDIVB_5 0x00003000
  531. #define PLL_FWDDIVB_4 0x00004000
  532. #define PLL_FWDDIVB_3 0x00005000
  533. #define PLL_FWDDIVB_2 0x00006000
  534. #define PLL_FWDDIVB_1 0x00007000
  535. /* PLL tune bits */
  536. #define PLL_TUNE_MASK 0x000003FF
  537. #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
  538. #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
  539. #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
  540. #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
  541. #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
  542. #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
  543. #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
  544. /* Defines for CPC0_PLLMR0 Register fields */
  545. /* CPU divisor */
  546. #define PLL_CPUDIV 0x00300000
  547. #define CPC0_PLLMR0_CCDV 0x00300000
  548. #define PLL_CPUDIV_1 0x00000000
  549. #define PLL_CPUDIV_2 0x00100000
  550. #define PLL_CPUDIV_3 0x00200000
  551. #define PLL_CPUDIV_4 0x00300000
  552. /* PLB divisor */
  553. #define PLL_PLBDIV 0x00030000
  554. #define CPC0_PLLMR0_CBDV 0x00030000
  555. #define PLL_PLBDIV_1 0x00000000
  556. #define PLL_PLBDIV_2 0x00010000
  557. #define PLL_PLBDIV_3 0x00020000
  558. #define PLL_PLBDIV_4 0x00030000
  559. /* OPB divisor */
  560. #define PLL_OPBDIV 0x00003000
  561. #define CPC0_PLLMR0_OPDV 0x00003000
  562. #define PLL_OPBDIV_1 0x00000000
  563. #define PLL_OPBDIV_2 0x00001000
  564. #define PLL_OPBDIV_3 0x00002000
  565. #define PLL_OPBDIV_4 0x00003000
  566. /* EBC divisor */
  567. #define PLL_EXTBUSDIV 0x00000300
  568. #define CPC0_PLLMR0_EPDV 0x00000300
  569. #define PLL_EXTBUSDIV_2 0x00000000
  570. #define PLL_EXTBUSDIV_3 0x00000100
  571. #define PLL_EXTBUSDIV_4 0x00000200
  572. #define PLL_EXTBUSDIV_5 0x00000300
  573. /* MAL divisor */
  574. #define PLL_MALDIV 0x00000030
  575. #define CPC0_PLLMR0_MPDV 0x00000030
  576. #define PLL_MALDIV_1 0x00000000
  577. #define PLL_MALDIV_2 0x00000010
  578. #define PLL_MALDIV_3 0x00000020
  579. #define PLL_MALDIV_4 0x00000030
  580. /* PCI divisor */
  581. #define PLL_PCIDIV 0x00000003
  582. #define CPC0_PLLMR0_PPFD 0x00000003
  583. #define PLL_PCIDIV_1 0x00000000
  584. #define PLL_PCIDIV_2 0x00000001
  585. #define PLL_PCIDIV_3 0x00000002
  586. #define PLL_PCIDIV_4 0x00000003
  587. #ifdef CONFIG_PPCHAMELEON_CLK_25
  588. /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
  589. #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
  590. PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  591. PLL_MALDIV_1 | PLL_PCIDIV_4)
  592. #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
  593. PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
  594. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  595. #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  596. PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
  597. PLL_MALDIV_1 | PLL_PCIDIV_4)
  598. #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
  599. PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
  600. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  601. #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  602. PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  603. PLL_MALDIV_1 | PLL_PCIDIV_4)
  604. #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
  605. PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
  606. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  607. #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
  608. PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
  609. PLL_MALDIV_1 | PLL_PCIDIV_2)
  610. #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
  611. PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
  612. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
  613. #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
  614. /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
  615. #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
  616. PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  617. PLL_MALDIV_1 | PLL_PCIDIV_4)
  618. #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
  619. PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
  620. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  621. #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  622. PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
  623. PLL_MALDIV_1 | PLL_PCIDIV_4)
  624. #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
  625. PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
  626. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  627. #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  628. PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  629. PLL_MALDIV_1 | PLL_PCIDIV_4)
  630. #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
  631. PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  632. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  633. #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
  634. PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
  635. PLL_MALDIV_1 | PLL_PCIDIV_2)
  636. #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
  637. PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  638. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
  639. #else
  640. #error "* External frequency (SysClk) not defined! *"
  641. #endif
  642. #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
  643. /* Model HI */
  644. #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
  645. #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
  646. #define CONFIG_SYS_OPB_FREQ 55555555
  647. /* Model ME */
  648. #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
  649. #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
  650. #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
  651. #define CONFIG_SYS_OPB_FREQ 66666666
  652. #else
  653. /* Model BA (default) */
  654. #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
  655. #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
  656. #define CONFIG_SYS_OPB_FREQ 66666666
  657. #endif
  658. #endif /* CONFIG_NO_SERIAL_EEPROM */
  659. #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
  660. #define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
  661. /*
  662. * JFFS2 partitions
  663. */
  664. /* No command line, one static partition */
  665. #undef CONFIG_CMD_MTDPARTS
  666. #define CONFIG_JFFS2_DEV "nand0"
  667. #define CONFIG_JFFS2_PART_SIZE 0x00400000
  668. #define CONFIG_JFFS2_PART_OFFSET 0x00000000
  669. /* mtdparts command line support */
  670. /*
  671. #define CONFIG_CMD_MTDPARTS
  672. #define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
  673. */
  674. /* 256 kB U-boot image */
  675. /*
  676. #define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
  677. "1792k(user),256k(u-boot);" \
  678. "ppchameleonevb-nand:-(nand)"
  679. */
  680. /* 320 kB U-boot image */
  681. /*
  682. #define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
  683. "1728k(user),320k(u-boot);" \
  684. "ppchameleonevb-nand:-(nand)"
  685. */
  686. #endif /* __CONFIG_H */