PLU405.h 15 KB

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  1. /*
  2. * (C) Copyright 2001-2003
  3. * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_405EP 1 /* This is a PPC405 CPU */
  33. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  34. #define CONFIG_PLU405 1 /* ...on a PLU405 board */
  35. #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
  36. #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
  37. #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
  38. #define CONFIG_BAUDRATE 9600
  39. #undef CONFIG_BOOTARGS
  40. #undef CONFIG_BOOTCOMMAND
  41. #define CONFIG_PREBOOT /* enable preboot variable */
  42. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  43. #define CONFIG_NET_MULTI 1
  44. #undef CONFIG_HAS_ETH1
  45. #define CONFIG_PPC4xx_EMAC
  46. #define CONFIG_MII 1 /* MII PHY management */
  47. #define CONFIG_PHY_ADDR 0 /* PHY address */
  48. #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
  49. #define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
  50. #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  51. /*
  52. * BOOTP options
  53. */
  54. #define CONFIG_BOOTP_BOOTFILESIZE
  55. #define CONFIG_BOOTP_BOOTPATH
  56. #define CONFIG_BOOTP_GATEWAY
  57. #define CONFIG_BOOTP_HOSTNAME
  58. /*
  59. * Command line configuration.
  60. */
  61. #include <config_cmd_default.h>
  62. #define CONFIG_CMD_DHCP
  63. #define CONFIG_CMD_PCI
  64. #define CONFIG_CMD_IRQ
  65. #define CONFIG_CMD_IDE
  66. #define CONFIG_CMD_FAT
  67. #define CONFIG_CMD_ELF
  68. #define CONFIG_CMD_NAND
  69. #define CONFIG_CMD_DATE
  70. #define CONFIG_CMD_I2C
  71. #define CONFIG_CMD_MII
  72. #define CONFIG_CMD_PING
  73. #define CONFIG_CMD_EEPROM
  74. #define CONFIG_CMD_USB
  75. #define CONFIG_OF_LIBFDT
  76. #define CONFIG_OF_BOARD_SETUP
  77. #define CONFIG_MAC_PARTITION
  78. #define CONFIG_DOS_PARTITION
  79. #define CONFIG_SUPPORT_VFAT
  80. #undef CONFIG_WATCHDOG /* watchdog disabled */
  81. #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
  82. #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
  83. #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  84. /*
  85. * Miscellaneous configurable options
  86. */
  87. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  88. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  89. #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  90. #ifdef CONFIG_SYS_HUSH_PARSER
  91. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  92. #endif
  93. #if defined(CONFIG_CMD_KGDB)
  94. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  95. #else
  96. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  97. #endif
  98. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  99. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  100. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  101. #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
  102. #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
  103. #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
  104. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  105. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  106. #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
  107. #define CONFIG_SYS_BASE_BAUD 691200
  108. #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
  109. /* The following table includes the supported baudrates */
  110. #define CONFIG_SYS_BAUDRATE_TABLE \
  111. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  112. 57600, 115200, 230400, 460800, 921600 }
  113. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  114. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  115. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  116. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  117. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  118. #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
  119. /* Only interrupt boot if space is pressed */
  120. /* If a long serial cable is connected but */
  121. /* other end is dead, garbage will be read */
  122. #define CONFIG_AUTOBOOT_KEYED 1
  123. #define CONFIG_AUTOBOOT_PROMPT \
  124. "Press SPACE to abort autoboot in %d seconds\n", bootdelay
  125. #undef CONFIG_AUTOBOOT_DELAY_STR
  126. #define CONFIG_AUTOBOOT_STOP_STR " "
  127. #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  128. #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
  129. /*
  130. * NAND-FLASH stuff
  131. */
  132. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  133. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  134. #define NAND_BIG_DELAY_US 25
  135. #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
  136. #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
  137. #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
  138. #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
  139. #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
  140. #define CONFIG_SYS_NAND_QUIET 1
  141. /*
  142. * PCI stuff
  143. */
  144. #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
  145. #define PCI_HOST_FORCE 1 /* configure as pci host */
  146. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  147. #define CONFIG_PCI /* include pci support */
  148. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  149. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  150. /* resource configuration */
  151. #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
  152. #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
  153. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
  154. #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
  155. #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
  156. #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
  157. #define CONFIG_SYS_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */
  158. #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  159. #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
  160. #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
  161. #define CONFIG_SYS_PCI_PTM2PCI 0x08000000 /* Host: use this pci address */
  162. /*
  163. * IDE/ATA stuff
  164. */
  165. #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
  166. #undef CONFIG_IDE_LED /* no led for ide supported */
  167. #define CONFIG_IDE_RESET 1 /* reset for ide supported */
  168. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
  169. /* max. 1 drives per IDE bus */
  170. #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1)
  171. #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
  172. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  173. #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
  174. #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */
  175. #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
  176. /*
  177. * For booting Linux, the board info and command line data
  178. * have to be in the first 8 MB of memory, since this is
  179. * the maximum mapped by the Linux kernel during initialization.
  180. */
  181. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  182. /*
  183. * FLASH organization
  184. */
  185. #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
  186. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  187. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  188. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  189. #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
  190. #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
  191. #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st addr for flash config cycles */
  192. #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd addr for flash config cycles */
  193. /*
  194. * The following defines are added for buggy IOP480 byte interface.
  195. * All other boards should use the standard values (CPCI405 etc.)
  196. */
  197. #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
  198. #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
  199. #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
  200. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
  201. /*
  202. * Start addresses for the final memory configuration
  203. * (Set up by the startup code)
  204. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  205. */
  206. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  207. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
  208. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
  209. #define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
  210. #define CONFIG_SYS_MALLOC_LEN (1024 << 10)
  211. /*
  212. * Environment Variable setup
  213. */
  214. #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
  215. #define CONFIG_ENV_OFFSET 0x100 /* reseve 0x100 bytes for strapping */
  216. #define CONFIG_ENV_SIZE 0x700
  217. /*
  218. * I2C EEPROM (24WC16) for environment
  219. */
  220. #define CONFIG_HARD_I2C /* I2c with hardware support */
  221. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  222. #define CONFIG_SYS_I2C_SLAVE 0x7F
  223. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */
  224. #define CONFIG_SYS_EEPROM_WREN 1
  225. /* 24WC16 */
  226. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  227. /* mask of address bits that overflow into the "EEPROM chip address" */
  228. #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
  229. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The 24WC16 has */
  230. /* 16 byte page write mode using */
  231. /* last 4 bits of the address */
  232. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  233. /*
  234. * External Bus Controller (EBC) Setup
  235. */
  236. #define CAN0_BA 0xF0000000 /* CAN0 Base Address */
  237. #define CAN1_BA 0xF0000100 /* CAN1 Base Address */
  238. #define DUART0_BA 0xF0000400 /* DUART Base Address */
  239. #define DUART1_BA 0xF0000408 /* DUART Base Address */
  240. #define RTC_BA 0xF0000500 /* RTC Base Address */
  241. #define VGA_BA 0xF1000000 /* Epson VGA Base Address */
  242. #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
  243. /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
  244. /* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
  245. #define CONFIG_SYS_EBC_PB0AP 0x92015480
  246. /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
  247. #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
  248. /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
  249. #define CONFIG_SYS_EBC_PB1AP 0x92015480
  250. /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
  251. #define CONFIG_SYS_EBC_PB1CR 0xF4018000
  252. /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
  253. /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  254. #define CONFIG_SYS_EBC_PB2AP 0x010053C0
  255. /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
  256. #define CONFIG_SYS_EBC_PB2CR 0xF0018000
  257. /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
  258. /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  259. #define CONFIG_SYS_EBC_PB3AP 0x010053C0
  260. /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
  261. #define CONFIG_SYS_EBC_PB3CR 0xF011A000
  262. /*
  263. * FPGA stuff
  264. */
  265. #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
  266. /* FPGA internal regs */
  267. #define CONFIG_SYS_FPGA_CTRL 0x000
  268. /* FPGA Control Reg */
  269. #define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
  270. #define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
  271. #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
  272. #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
  273. #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
  274. /* FPGA program pin configuration */
  275. #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
  276. #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
  277. #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
  278. #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
  279. #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
  280. /*
  281. * Definitions for initial stack pointer and data area (in data cache)
  282. */
  283. /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
  284. #define CONFIG_SYS_TEMP_STACK_OCM 1
  285. /* On Chip Memory location */
  286. #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
  287. #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
  288. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
  289. #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
  290. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  291. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  292. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  293. /*
  294. * Definitions for GPIO setup (PPC405EP specific)
  295. *
  296. * GPIO0[0] - External Bus Controller BLAST output
  297. * GPIO0[1-9] - Instruction trace outputs -> GPIO
  298. * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  299. * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  300. * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  301. * GPIO0[24-27] - UART0 control signal inputs/outputs
  302. * GPIO0[28-29] - UART1 data signal input/output
  303. * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  304. */
  305. #define CONFIG_SYS_GPIO0_OSRH 0x00000550
  306. #define CONFIG_SYS_GPIO0_OSRL 0x00000110
  307. #define CONFIG_SYS_GPIO0_ISR1H 0x00000000
  308. #define CONFIG_SYS_GPIO0_ISR1L 0x15555445
  309. #define CONFIG_SYS_GPIO0_TSRH 0x00000000
  310. #define CONFIG_SYS_GPIO0_TSRL 0x00000000
  311. #define CONFIG_SYS_GPIO0_TCR 0x77FE0014
  312. #define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
  313. #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0)
  314. /*
  315. * Internal Definitions
  316. *
  317. * Boot Flags
  318. */
  319. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  320. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  321. /*
  322. * Default speed selection (cpu_plb_opb_ebc) in MHz.
  323. * This value will be set if iic boot eprom is disabled.
  324. */
  325. #if 1
  326. #define PLLMR0_DEFAULT PLLMR0_266_133_66_33
  327. #define PLLMR1_DEFAULT PLLMR1_266_133_66_33
  328. #endif
  329. #if 0
  330. #define PLLMR0_DEFAULT PLLMR0_200_100_50_33
  331. #define PLLMR1_DEFAULT PLLMR1_200_100_50_33
  332. #endif
  333. #if 0
  334. #define PLLMR0_DEFAULT PLLMR0_133_66_66_33
  335. #define PLLMR1_DEFAULT PLLMR1_133_66_66_33
  336. #endif
  337. /*
  338. * PCI OHCI controller
  339. */
  340. #define CONFIG_USB_OHCI_NEW 1
  341. #define CONFIG_PCI_OHCI 1
  342. #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
  343. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  344. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
  345. #define CONFIG_USB_STORAGE 1
  346. /*
  347. * UBI
  348. */
  349. #define CONFIG_CMD_UBI
  350. #define CONFIG_RBTREE
  351. #define CONFIG_MTD_DEVICE
  352. #define CONFIG_MTD_PARTITIONS
  353. #define CONFIG_CMD_MTDPARTS
  354. #define CONFIG_LZO
  355. #endif /* __CONFIG_H */