P2020DS.h 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742
  1. /*
  2. * Copyright 2007-2009 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. /*
  23. * p2020ds board configuration file
  24. *
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. #ifdef CONFIG_MK_36BIT
  29. #define CONFIG_PHYS_64BIT
  30. #endif
  31. /* High Level Configuration Options */
  32. #define CONFIG_BOOKE 1 /* BOOKE */
  33. #define CONFIG_E500 1 /* BOOKE e500 family */
  34. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
  35. #define CONFIG_P2020 1
  36. #define CONFIG_P2020DS 1
  37. #define CONFIG_MP 1 /* support multiple processors */
  38. #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
  39. #define CONFIG_PCI 1 /* Enable PCI/PCIE */
  40. #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
  41. #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
  42. #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
  43. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  44. #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
  45. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  46. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  47. #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
  48. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  49. #define CONFIG_ENV_OVERWRITE
  50. #ifndef __ASSEMBLY__
  51. extern unsigned long calculate_board_sys_clk(unsigned long dummy);
  52. extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
  53. /* extern unsigned long get_board_sys_clk(unsigned long dummy); */
  54. /* extern unsigned long get_board_ddr_clk(unsigned long dummy); */
  55. #endif
  56. #define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */
  57. #define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */
  58. #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
  59. #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
  60. from ICS307 instead of switches */
  61. /*
  62. * These can be toggled for performance analysis, otherwise use default.
  63. */
  64. #define CONFIG_L2_CACHE /* toggle L2 cache */
  65. #define CONFIG_BTB /* toggle branch predition */
  66. #define CONFIG_ENABLE_36BIT_PHYS 1
  67. #ifdef CONFIG_PHYS_64BIT
  68. #define CONFIG_ADDR_MAP 1
  69. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  70. #endif
  71. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
  72. #define CONFIG_SYS_MEMTEST_END 0x7fffffff
  73. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  74. /*
  75. * Base addresses -- Note these are effective addresses where the
  76. * actual resources get mapped (not physical addresses)
  77. */
  78. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  79. #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
  80. #ifdef CONFIG_PHYS_64BIT
  81. #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
  82. #else
  83. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
  84. #endif
  85. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  86. #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
  87. #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
  88. #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
  89. /* DDR Setup */
  90. #define CONFIG_SYS_DDR_TLB_START 9
  91. #define CONFIG_VERY_BIG_RAM
  92. #define CONFIG_FSL_DDR3 1
  93. #undef CONFIG_FSL_DDR_INTERACTIVE
  94. /* ECC will be enabled based on perf_mode environment variable */
  95. /* #define CONFIG_DDR_ECC */
  96. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  97. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  98. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  99. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  100. #define CONFIG_NUM_DDR_CONTROLLERS 1
  101. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  102. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  103. /* I2C addresses of SPD EEPROMs */
  104. #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
  105. #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
  106. /* These are used when DDR doesn't use SPD. */
  107. #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
  108. /* Default settings for "stable" mode */
  109. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
  110. #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
  111. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
  112. #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
  113. #define CONFIG_SYS_DDR_TIMING_3 0x00020000
  114. #define CONFIG_SYS_DDR_TIMING_0 0x00330804
  115. #define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
  116. #define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
  117. #define CONFIG_SYS_DDR_MODE_1 0x00421422
  118. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  119. #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
  120. #define CONFIG_SYS_DDR_INTERVAL 0x61800100
  121. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  122. #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
  123. #define CONFIG_SYS_DDR_TIMING_4 0x00220001
  124. #define CONFIG_SYS_DDR_TIMING_5 0x03402400
  125. #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
  126. #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
  127. #define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
  128. #define CONFIG_SYS_DDR_CONTROL2 0x24400011
  129. #define CONFIG_SYS_DDR_CDR1 0x00040000
  130. #define CONFIG_SYS_DDR_CDR2 0x00000000
  131. #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
  132. #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
  133. #define CONFIG_SYS_DDR_SBE 0x00010000
  134. /* Settings that differ for "performance" mode */
  135. #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
  136. #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
  137. #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
  138. #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
  139. #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
  140. #define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
  141. /*
  142. * The following set of values were tested for DDR2
  143. * with a DDR3 to DDR2 interposer
  144. *
  145. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  146. #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  147. #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
  148. #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
  149. #define CONFIG_SYS_DDR_MODE_1 0x00480432
  150. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  151. #define CONFIG_SYS_DDR_INTERVAL 0x06180100
  152. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  153. #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
  154. #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
  155. #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
  156. #define CONFIG_SYS_DDR_CONTROL 0xC3008000
  157. #define CONFIG_SYS_DDR_CONTROL2 0x04400010
  158. *
  159. */
  160. #undef CONFIG_CLOCKS_IN_MHZ
  161. /*
  162. * Memory map
  163. *
  164. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  165. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
  166. * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
  167. * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
  168. *
  169. * Localbus cacheable (TBD)
  170. * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
  171. *
  172. * Localbus non-cacheable
  173. * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
  174. * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
  175. * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
  176. * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
  177. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  178. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  179. */
  180. /*
  181. * Local Bus Definitions
  182. */
  183. #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
  184. #ifdef CONFIG_PHYS_64BIT
  185. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  186. #else
  187. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  188. #endif
  189. #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
  190. #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
  191. #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
  192. #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
  193. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  194. #define CONFIG_SYS_FLASH_QUIET_TEST
  195. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  196. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  197. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  198. #undef CONFIG_SYS_FLASH_CHECKSUM
  199. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  200. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  201. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  202. #define CONFIG_FLASH_CFI_DRIVER
  203. #define CONFIG_SYS_FLASH_CFI
  204. #define CONFIG_SYS_FLASH_EMPTY_INFO
  205. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  206. #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  207. #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
  208. #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  209. #ifdef CONFIG_PHYS_64BIT
  210. #define PIXIS_BASE_PHYS 0xfffdf0000ull
  211. #else
  212. #define PIXIS_BASE_PHYS PIXIS_BASE
  213. #endif
  214. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
  215. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
  216. #define PIXIS_ID 0x0 /* Board ID at offset 0 */
  217. #define PIXIS_VER 0x1 /* Board version at offset 1 */
  218. #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
  219. #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
  220. #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
  221. #define PIXIS_PWR 0x5 /* PIXIS Power status register */
  222. #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
  223. #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
  224. #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
  225. #define PIXIS_VCTL 0x10 /* VELA Control Register */
  226. #define PIXIS_VSTAT 0x11 /* VELA Status Register */
  227. #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
  228. #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
  229. #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
  230. #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
  231. #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
  232. #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
  233. #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
  234. #define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */
  235. #define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */
  236. #define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */
  237. #define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */
  238. #define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */
  239. #define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */
  240. #define PIXIS_VWATCH 0x24 /* Watchdog Register */
  241. #define PIXIS_LED 0x25 /* LED Register */
  242. #define PIXIS_SW(x) 0x20 + (x - 1) * 2
  243. #define PIXIS_EN(x) 0x21 + (x - 1) * 2
  244. #define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */
  245. #define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */
  246. /* old pixis referenced names */
  247. #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
  248. #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
  249. #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
  250. #define PIXIS_VSPEED2_TSEC1SER 0x8
  251. #define PIXIS_VSPEED2_TSEC2SER 0x4
  252. #define PIXIS_VSPEED2_TSEC3SER 0x2
  253. #define PIXIS_VSPEED2_TSEC4SER 0x1
  254. #define PIXIS_VCFGEN1_TSEC1SER 0x20
  255. #define PIXIS_VCFGEN1_TSEC2SER 0x20
  256. #define PIXIS_VCFGEN1_TSEC3SER 0x20
  257. #define PIXIS_VCFGEN1_TSEC4SER 0x20
  258. #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
  259. | PIXIS_VSPEED2_TSEC2SER \
  260. | PIXIS_VSPEED2_TSEC3SER \
  261. | PIXIS_VSPEED2_TSEC4SER)
  262. #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
  263. | PIXIS_VCFGEN1_TSEC2SER \
  264. | PIXIS_VCFGEN1_TSEC3SER \
  265. | PIXIS_VCFGEN1_TSEC4SER)
  266. #define CONFIG_SYS_INIT_RAM_LOCK 1
  267. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  268. #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
  269. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  270. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  271. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  272. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  273. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  274. #define CONFIG_SYS_NAND_BASE 0xffa00000
  275. #ifdef CONFIG_PHYS_64BIT
  276. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  277. #else
  278. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  279. #endif
  280. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
  281. CONFIG_SYS_NAND_BASE + 0x40000, \
  282. CONFIG_SYS_NAND_BASE + 0x80000,\
  283. CONFIG_SYS_NAND_BASE + 0xC0000}
  284. #define CONFIG_SYS_MAX_NAND_DEVICE 4
  285. #define CONFIG_MTD_NAND_VERIFY_WRITE
  286. #define CONFIG_CMD_NAND 1
  287. #define CONFIG_NAND_FSL_ELBC 1
  288. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  289. /* NAND flash config */
  290. #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  291. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  292. | BR_PS_8 /* Port Size = 8bit */ \
  293. | BR_MS_FCM /* MSEL = FCM */ \
  294. | BR_V) /* valid */
  295. #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  296. | OR_FCM_PGS /* Large Page*/ \
  297. | OR_FCM_CSCT \
  298. | OR_FCM_CST \
  299. | OR_FCM_CHT \
  300. | OR_FCM_SCY_1 \
  301. | OR_FCM_TRLX \
  302. | OR_FCM_EHTR)
  303. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  304. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  305. #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
  306. #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  307. #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
  308. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  309. | BR_PS_8 /* Port Size = 8bit */ \
  310. | BR_MS_FCM /* MSEL = FCM */ \
  311. | BR_V) /* valid */
  312. #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  313. #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
  314. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  315. | BR_PS_8 /* Port Size = 8bit */ \
  316. | BR_MS_FCM /* MSEL = FCM */ \
  317. | BR_V) /* valid */
  318. #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  319. #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
  320. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  321. | BR_PS_8 /* Port Size = 8bit */ \
  322. | BR_MS_FCM /* MSEL = FCM */ \
  323. | BR_V) /* valid */
  324. #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  325. /* Serial Port - controlled on board with jumper J8
  326. * open - index 2
  327. * shorted - index 1
  328. */
  329. #define CONFIG_CONS_INDEX 1
  330. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  331. #define CONFIG_SYS_NS16550
  332. #define CONFIG_SYS_NS16550_SERIAL
  333. #define CONFIG_SYS_NS16550_REG_SIZE 1
  334. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  335. #define CONFIG_SYS_BAUDRATE_TABLE \
  336. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  337. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  338. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  339. /* Use the HUSH parser */
  340. #define CONFIG_SYS_HUSH_PARSER
  341. #ifdef CONFIG_SYS_HUSH_PARSER
  342. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  343. #endif
  344. /*
  345. * Pass open firmware flat tree
  346. */
  347. #define CONFIG_OF_LIBFDT 1
  348. #define CONFIG_OF_BOARD_SETUP 1
  349. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  350. /* new uImage format support */
  351. #define CONFIG_FIT 1
  352. #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
  353. /* I2C */
  354. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  355. #define CONFIG_HARD_I2C /* I2C with hardware support */
  356. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  357. #define CONFIG_I2C_MULTI_BUS
  358. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  359. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  360. #define CONFIG_SYS_I2C_SLAVE 0x7F
  361. #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
  362. #define CONFIG_SYS_I2C_OFFSET 0x3000
  363. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  364. /*
  365. * I2C2 EEPROM
  366. */
  367. #define CONFIG_ID_EEPROM
  368. #ifdef CONFIG_ID_EEPROM
  369. #define CONFIG_SYS_I2C_EEPROM_NXID
  370. #endif
  371. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  372. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  373. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  374. /*
  375. * General PCI
  376. * Memory space is mapped 1-1, but I/O space must start from 0.
  377. */
  378. /* controller 3, Slot 1, tgtid 3, Base address b000 */
  379. #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
  380. #ifdef CONFIG_PHYS_64BIT
  381. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  382. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
  383. #else
  384. #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
  385. #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
  386. #endif
  387. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  388. #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
  389. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  390. #ifdef CONFIG_PHYS_64BIT
  391. #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
  392. #else
  393. #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
  394. #endif
  395. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  396. /* controller 2, direct to uli, tgtid 2, Base address 9000 */
  397. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  398. #ifdef CONFIG_PHYS_64BIT
  399. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  400. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  401. #else
  402. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  403. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  404. #endif
  405. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  406. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  407. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  408. #ifdef CONFIG_PHYS_64BIT
  409. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  410. #else
  411. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  412. #endif
  413. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  414. /* controller 1, Slot 2, tgtid 1, Base address a000 */
  415. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
  416. #ifdef CONFIG_PHYS_64BIT
  417. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  418. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
  419. #else
  420. #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
  421. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
  422. #endif
  423. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  424. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
  425. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  426. #ifdef CONFIG_PHYS_64BIT
  427. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
  428. #else
  429. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
  430. #endif
  431. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  432. #if defined(CONFIG_PCI)
  433. /*PCIE video card used*/
  434. #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
  435. /* video */
  436. #define CONFIG_VIDEO
  437. #if defined(CONFIG_VIDEO)
  438. #define CONFIG_BIOSEMU
  439. #define CONFIG_CFB_CONSOLE
  440. #define CONFIG_VIDEO_SW_CURSOR
  441. #define CONFIG_VGA_AS_SINGLE_DEVICE
  442. #define CONFIG_ATI_RADEON_FB
  443. #define CONFIG_VIDEO_LOGO
  444. /*#define CONFIG_CONSOLE_CURSOR*/
  445. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
  446. #endif
  447. #define CONFIG_NET_MULTI
  448. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  449. #undef CONFIG_EEPRO100
  450. #undef CONFIG_TULIP
  451. #define CONFIG_RTL8139
  452. #ifndef CONFIG_PCI_PNP
  453. #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
  454. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
  455. #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
  456. #endif
  457. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  458. #define CONFIG_DOS_PARTITION
  459. #define CONFIG_SCSI_AHCI
  460. #ifdef CONFIG_SCSI_AHCI
  461. #define CONFIG_SATA_ULI5288
  462. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
  463. #define CONFIG_SYS_SCSI_MAX_LUN 1
  464. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
  465. #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
  466. #endif /* SCSI */
  467. #endif /* CONFIG_PCI */
  468. #if defined(CONFIG_TSEC_ENET)
  469. #ifndef CONFIG_NET_MULTI
  470. #define CONFIG_NET_MULTI 1
  471. #endif
  472. #define CONFIG_MII 1 /* MII PHY management */
  473. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  474. #define CONFIG_TSEC1 1
  475. #define CONFIG_TSEC1_NAME "eTSEC1"
  476. #define CONFIG_TSEC2 1
  477. #define CONFIG_TSEC2_NAME "eTSEC2"
  478. #define CONFIG_TSEC3 1
  479. #define CONFIG_TSEC3_NAME "eTSEC3"
  480. #define CONFIG_PIXIS_SGMII_CMD
  481. #define CONFIG_FSL_SGMII_RISER 1
  482. #define SGMII_RISER_PHY_OFFSET 0x1b
  483. #ifdef CONFIG_FSL_SGMII_RISER
  484. #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
  485. #endif
  486. #define TSEC1_PHY_ADDR 0
  487. #define TSEC2_PHY_ADDR 1
  488. #define TSEC3_PHY_ADDR 2
  489. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  490. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  491. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  492. #define TSEC1_PHYIDX 0
  493. #define TSEC2_PHYIDX 0
  494. #define TSEC3_PHYIDX 0
  495. #define CONFIG_ETHPRIME "eTSEC1"
  496. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  497. #endif /* CONFIG_TSEC_ENET */
  498. /*
  499. * Environment
  500. */
  501. #define CONFIG_ENV_IS_IN_FLASH 1
  502. #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
  503. #define CONFIG_ENV_ADDR 0xfff80000
  504. #else
  505. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  506. #endif
  507. #define CONFIG_ENV_SIZE 0x2000
  508. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  509. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  510. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  511. /*
  512. * Command line configuration.
  513. */
  514. #include <config_cmd_default.h>
  515. #define CONFIG_CMD_IRQ
  516. #define CONFIG_CMD_PING
  517. #define CONFIG_CMD_I2C
  518. #define CONFIG_CMD_MII
  519. #define CONFIG_CMD_ELF
  520. #define CONFIG_CMD_IRQ
  521. #define CONFIG_CMD_SETEXPR
  522. #if defined(CONFIG_PCI)
  523. #define CONFIG_CMD_PCI
  524. #define CONFIG_CMD_NET
  525. #define CONFIG_CMD_SCSI
  526. #define CONFIG_CMD_EXT2
  527. #endif
  528. /*
  529. * USB
  530. */
  531. #define CONFIG_CMD_USB
  532. #define CONFIG_USB_STORAGE
  533. #define CONFIG_USB_EHCI
  534. #define CONFIG_USB_EHCI_FSL
  535. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  536. #undef CONFIG_WATCHDOG /* watchdog disabled */
  537. /*
  538. * Miscellaneous configurable options
  539. */
  540. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  541. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  542. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  543. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  544. #if defined(CONFIG_CMD_KGDB)
  545. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  546. #else
  547. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  548. #endif
  549. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  550. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  551. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  552. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  553. /*
  554. * For booting Linux, the board info and command line data
  555. * have to be in the first 16 MB of memory, since this is
  556. * the maximum mapped by the Linux kernel during initialization.
  557. */
  558. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  559. /*
  560. * Internal Definitions
  561. *
  562. * Boot Flags
  563. */
  564. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  565. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  566. #if defined(CONFIG_CMD_KGDB)
  567. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  568. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  569. #endif
  570. /*
  571. * Environment Configuration
  572. */
  573. /* The mac addresses for all ethernet interface */
  574. #if defined(CONFIG_TSEC_ENET)
  575. #define CONFIG_HAS_ETH0
  576. #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
  577. #define CONFIG_HAS_ETH1
  578. #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
  579. #define CONFIG_HAS_ETH2
  580. #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
  581. #define CONFIG_HAS_ETH3
  582. #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
  583. #endif
  584. #define CONFIG_IPADDR 192.168.1.254
  585. #define CONFIG_HOSTNAME unknown
  586. #define CONFIG_ROOTPATH /opt/nfsroot
  587. #define CONFIG_BOOTFILE uImage
  588. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  589. #define CONFIG_SERVERIP 192.168.1.1
  590. #define CONFIG_GATEWAYIP 192.168.1.1
  591. #define CONFIG_NETMASK 255.255.255.0
  592. /* default location for tftp and bootm */
  593. #define CONFIG_LOADADDR 1000000
  594. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  595. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  596. #define CONFIG_BAUDRATE 115200
  597. #define CONFIG_EXTRA_ENV_SETTINGS \
  598. "perf_mode=stable\0" \
  599. "memctl_intlv_ctl=2\0" \
  600. "netdev=eth0\0" \
  601. "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
  602. "tftpflash=tftpboot $loadaddr $uboot; " \
  603. "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
  604. "erase " MK_STR(TEXT_BASE) " +$filesize; " \
  605. "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
  606. "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
  607. "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
  608. "consoledev=ttyS0\0" \
  609. "ramdiskaddr=2000000\0" \
  610. "ramdiskfile=p2020ds/ramdisk.uboot\0" \
  611. "fdtaddr=c00000\0" \
  612. "fdtfile=p2020ds/p2020ds.dtb\0" \
  613. "bdev=sda3\0"
  614. #define CONFIG_HDBOOT \
  615. "setenv bootargs root=/dev/$bdev rw " \
  616. "console=$consoledev,$baudrate $othbootargs;" \
  617. "tftp $loadaddr $bootfile;" \
  618. "tftp $fdtaddr $fdtfile;" \
  619. "bootm $loadaddr - $fdtaddr"
  620. #define CONFIG_NFSBOOTCOMMAND \
  621. "setenv bootargs root=/dev/nfs rw " \
  622. "nfsroot=$serverip:$rootpath " \
  623. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  624. "console=$consoledev,$baudrate $othbootargs;" \
  625. "tftp $loadaddr $bootfile;" \
  626. "tftp $fdtaddr $fdtfile;" \
  627. "bootm $loadaddr - $fdtaddr"
  628. #define CONFIG_RAMBOOTCOMMAND \
  629. "setenv bootargs root=/dev/ram rw " \
  630. "console=$consoledev,$baudrate $othbootargs;" \
  631. "tftp $ramdiskaddr $ramdiskfile;" \
  632. "tftp $loadaddr $bootfile;" \
  633. "tftp $fdtaddr $fdtfile;" \
  634. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  635. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  636. #endif /* __CONFIG_H */